Pentacene Layer Research Articles

On the relationship between the structure of self-assembled carboxylic acid monolayers on alumina and the organization and electrical properties of a pentacene thin film

The modification of insulating surfaces by self-assembled monolayers (SAMs) is an elegant way of tailoring the gate dielectric of organic field effect transistors (OFET) to pentacene and is commonly used to improve electrical performance. A SAM based on an alkylcarboxylic acid deposited on a thin layer of alumina, serving as the gate dielectric is considered. The relationship between carrier mobility and (i) the length of the carboxylic acid (CH3(CH2)nCOOH; n=9, 14, 18), (ii) substrate preparation and (iii) the SAM and pentacene thin film structures is considered. The size and boundaries of pentacene grains are not limiting factors for carrier mobility, and the most relevant parameter, which depends on whether there is a SAM or not, is the organization of the first pentacene layers in contact with the gate dielectric. The variation of the interplanar distance d(001) of the pentacene layers close to the alumina surface is much greater without SAM than with, and this could explain the lower carrier mobility observed in the case of a bare alumina dielectric. The relationship between the disorder associated with this variation and mobility is discussed.

Spin-pump-induced spin transport in a thermally evaporated pentacene film

We report the spin-pump-induced spin transport properties of a pentacene film prepared by thermal evaporation. In a palladium(Pd)/pentacene/Ni80Fe20 tri-layer sample, a pure spin-current is generated in the pentacene layer by the spin-pumping of Ni80Fe20, which is independent of the conductance mismatch problem in spin injection. The spin current is absorbed into the Pd layer, converted into a charge current with the inverse spin-Hall effect in Pd, and detected as an electromotive force. This is clear evidence for the pure spin current at room temperature in pentacene films prepared by thermal evaporation.

Contact Doping for Vertical Organic Field‐Effect Transistors

Doping is a powerful tool to overcome contact limitations in short‐channel organic field‐effect transistors (OFETs) and has been successfully used in the past to improve the charge carrier injection in OFETs. The present study applies this familiar concept to the architecture of vertical organic field‐effect transistors (VOFETs), which are often severely limited by injection due to their very short channel lengths. The present study shows that the performance of p‐type VOFETs with pentacene as an active material can be significantly enhanced by the addition of the common p‐dopant C60F36 as a thin injection layer underneath the VOFET source electrode, resulting in an increase of On‐state current and On/Off ratio by one order of magnitude. The present study further investigates mixed injection layers of pentacene and the p‐dopant and finds that the improvement is less pronounced than for the pure dopant layers and depends on the concentration of dopant molecules in the injection layer. Through application of the transfer length method to equivalent OFET geometries, the present study is finally able to link the observed improvement to a decrease in transfer length and can thus conclude that this length is a crucial parameter onto which further improvement efforts have to be concentrated to realize true short‐channel VOFETs.

Monolayer field effect transistor as a probe of electronic defects in organic semiconducting layers at organic/inorganic hetero-junction interface

The origin of a large negative threshold voltage observed in monolayer (ML) field effect transistors (FETs) is explored using in-situ electrical measurements through confining the thickness of an active layer to the accumulation layer thickness. Using ML pentacene FETs combined with gated multiple-terminal devices and atomic force microscopy, the effect of electronic and structural evolution of a ML pentacene film on the threshold voltage in an FET, proportional to the density of deep traps, was probed, revealing that a large negative threshold voltage found in ML FETs results from the pentacene/SiO2 and pentacene/metal interfaces. More importantly, the origin of the threshold voltage difference between ML and thick FETs is addressed through a model in which the effective charge transport layer is transitioned from the pentacene layer interfacing with the SiO2 gate dielectric to the upper layers with pentacene thickness increasing evidenced by pentacene coverage dependent threshold voltage measurements.

Effects of Au source/drain thickness on electrical characteristics of pentacene thin-film transistors

We investigate the electrical characteristics of top-contact pentacene thin-film transistors (TFTs) fabricated with various thicknesses of the Au source and the drain (S/D) electrodes, i.e., 20, 30, 50, 70, and 105 nm. Pentacene TFTs exhibit enhancements in the drain current and the fieldeffect mobility with increasing thickness of Au S/D electrodes up to 50 nm, after which the TFT performance degrades with increasing Au thickness. A transmission line method is used to analyze the contact resistance between the Au electrode and the pentacene layer in the TFTs, and ultraviolet photoemission spectroscopy measurements are performed to determine the work function of the Au films. The lowest contact resistance, 73 kΩ·cm, is obtained for the 50-nm-thick Au case and is ascribed to the high work function (4.67 eV) of the film. Consequently, the effects of the Au S/D thickness on the performance of top-contact pentacene TFTs can be understood through the behavior of the charge injection at the Au electrode/pentacene interface.

Optimizing pentacene thin-film transistor performance: Temperature and surface condition induced layer growth modification

In this work we present in situ electrical and surface analytical, as well as ex situ atomic force microscopy (AFM) studies on temperature and surface condition induced pentacene layer growth modifications, leading to the selection of optimized deposition conditions and entailing performance improvements. We prepared p++-silicon/silicon dioxide bottom-gate, gold bottom-contact transistor samples and evaluated the pentacene layer growth for three different surface conditions (sputtered, sputtered+carbon and unsputtered+carbon) at sample temperatures during deposition of 200K, 300K and 350K. The AFM investigations focused on the gold contacts, the silicon dioxide channel region and the highly critical transition area. Evaluations of coverage dependent saturation mobilities, threshold voltages and corresponding AFM analysis were able to confirm that the first 3–4 full monolayers contribute to the majority of charge transport within the channel region. At high temperatures and on sputtered surfaces uniform layer formation in the contact–channel transition area is limited by dewetting, leading to the formation of trenches and the partial development of double layer islands within the channel region instead of full wetting layers. By combining the advantages of an initial high temperature deposition (well-ordered islands in the channel) and a subsequent low temperature deposition (continuous film formation for low contact resistance) we were able to prepare very thin (8ML) pentacene transistors of comparably high mobility.

Room temperature Coulomb blockade effects in Au nanocluster/pentacene single electron transistors

Single-electron transistors incorporating single ∼1 nm gold nanocluster (AuNCs) and pentacene as a complex charge transport system have been used to study the quantum Coulomb blockade and its single electron tunnelling behaviour at room temperature (RT) (300 K). Monodisperse ultra-small (0.86 ± 0.30 nm) AuNCs were deposited by the tilted-target sputtering technique into 12 nm nanogaps fabricated by high-resolution e-beam lithography. Tunnelling resistance was modulated to ∼109 Ω by addition of a pentacene layer, allowing clear observation of quantum staircases and Coulomb oscillations with on/off current modulation ratio of ∼100 in RT current–voltage measurements. The electron addition energy and average quantized energy level spacing were found to be 282 and 80.4 meV, respectively, which are significantly larger than the thermal energy at 300 K (25.9 meV).

Small-molecule organic solar cells with multiple-layer donor

Small-molecule organic solar cells (OSCs) with a multifunction three-layer donor are experimentally investigated to achieve higher power conversion efficiency. The proposed OSC has an indium tin oxide (ITO, anode)/three-layer donor/fullerene (C60, acceptor, 40 nm)/bathocuproine (BCP, cathode buffer, 10 nm)/Ag (cathode, 100 nm) structure. The three-layer donor is composed of 3-nm-thick pentacene/20-nm-thick copper phthalocyanine (CuPc)/5-nm-thick aluminum phthalocyanine chloride (ClAlPc). The OSC achieves a power conversion efficiency of 1.79%, which is 1.7 times as large as that for an OSC with a single-layer donor of 20-nm-thick CuPc. Atomic force microscopy observation is carried out to clarify in detail the surface morphology at typical organic layers. The acceptor C60 is in contact not only with ClAlPc but also with CuPc due to the vertical and wall-like growth of the ClAlPc layer. The open-circuit voltage for the OSC with the ClAlPc/C60 contact is 0.56 V, compared with 0.47 V for the OSC with the CuPc/C60 contact. The thin pentacene layer is uniformly grown on the ITO and serves to achieve a high short-circuit current density Jsc by lowering the barrier height for hole transport between ITO and CuPc. Jsc for the OSC with the thin pentacene layer is 5.60 mA/cm2, compared with 4.32 mA/cm2 for the OSC without the thin pentacene layer.

Pentacene Thin-Film Transistors with Hydrophobic Nanostructures on a Polymeric Gate Insulator

The effects of hydrophobic nanostructures on the growth of pentacene molecules and the electrical characteristics of pentacene thin-film transistors (TFTs) are investigated. X-ray diffraction results show that hydrophobic nanostructures are conducive to the upright growth of pentacene molecules to the substrate. Pentacene TFTs, in which hydrophobic nanostructures with a cowl shape were introduced at the interface between the pentacene layer and the gate insulator, thus exhibit a pronounced enhancement in the field-effect mobility, up to approximately 2.94 cm2/Vs. These results suggest that hydrophobic nanostructures are effective to the ordered growth of pentacene molecules for high-performance organic TFTs.

Analysis of current-voltage characteristics of Au/pentacene/fluorine polymer/indium zinc oxide diodes by electric-field-induced optical second-harmonic generation

By using electric-field-induced optical second-harmonic generation measurement coupled with the conventional current-voltage (I-V) measurement, we studied the carrier transport of organic double-layer diodes with a Au/pentacene/fluorine polymer (FP)/indium zinc oxide (IZO) structure. The rectifying I-V characteristics were converted into the I-E characteristics of the FP and pentacene layers. Results suggest a model in which Schottky-type electron injection from the IZO electrode to the FP layer governs the forward electrical conduction (V > 0), where the space charge electric field produced in the FP layer by accumulated holes at the pentacene/FP interface makes a significant contribution. On the other hand, Schottky-type injection by accumulated interface electrons from the pentacene layer to the FP layer governs the backward electrical conduction (V < 0). The electroluminescence generated from the pentacene layer in the region V > 0 verifies the electron transport across the FP layer, and supports the above suggested model.

Photosensing Properties of Pentacene OFETs Based on a Novel PMMA Copolymer Gate Dielectric

In the present work, bottom-gate top-contact organic field effect transistors (OFETs) were fabricated by evaporating a pentacene semiconductor film on top of a new insulating poly(methyl methacrylate) (PMMA) copolymer containing methacrylate units. The PMMA copolymer was synthesized in order to combine the well-known insulating properties of PMMA with the possibility to be efficiently photocured enabling photopatterning-based organic circuitry integration processes. The properties of the pentacene layer deposited on ITO/PMMA copolymer stack were studied through morphological and structural analyses. Device photoresponses and photoexcitated transients were investigated and compared to reference devices based on standard PMMA gate dielectric.

Enhanced Charge Injection Through Nanostructured Electrodes for Organic Field Effect Transistors

Nanosphere lithography is used to process nanopore‐structured electrodes, which are applied into the fabrication of bottom‐gate, bottom‐contact configuration organic field effect transistors (OFETs) to serve as source/drain elecrodes. The introduction of this nanopore‐structure electrode facilitates the forming of nanopore‐structure pentacene layers with small grain boundaries at the electrode interface, and then reduces the contact resistance, contact‐induces the growth of pentacene and accordingly improves the mobility of charge carriers in the OFETs about 20 times as compared with results in literature through enhancing the charge carrier injection. It is believed that this structure of electrode is a valuable approach for improving organic filed effect transistors.

PENTACENE-BASED ORGANIC THIN FILM TRANSISTOR WITH SiO2 GATE DIELECTRIC

An organic thin film transistor (OTFT) based on pentacene was fabricated with SiO 2 as the gate dielectric material. We have investigated the effects of the thickness of pentacene layer and the organic semiconductor (OSC) material on OTFT devices at two different thicknesses. Au metal was deposited for gate, source and drain contacts of the device by using thermal evaporation method. Pentacene thin film layer was also prepared with thermal evaporation. Our study has shown that the change in pentacene thickness makes a noteworthy difference on the field effect mobility (μFET), values, threshold voltages (VT) and on/off current ratios (Ion/Ioff). OTFTs exhibited saturation at the order of μFET of 3.92 cm2/Vs and 0.86 cm2/Vs at different thicknesses. Ion/Ioff and VT are also thickness dependent. Ion/Ioff is 1 × 103, 2 × 102 and VT is 15 V, 27 V of 40 nm and 60 nm, respectively. The optimized thickness of the pentacene layer was found as 40 nm. The effect of the OSC layer thickness on the OTFT performance was found to be conspicuous.

Cellulose-Derivative-Based Gate Dielectric for High-Performance Organic Complementary Inverters.

been realized using organic thin-fi lm transistors (OTFTs) as the essential element. In the majority of these applications OTFTs are integrated either in the form of arrays or as digital logic. The fundamental building block of digital logic is the inverter, a circuit that inverts an input signal. Much work has been devoted in the last fi ve years to design unipolar inverters using p-typeonly OTFTs. [ 18‐23 ] Unfortunately, unipolar logic based on single gate OTFTs always suffers from high power consumption and low noise margin coupled with high noise margin variability and therefore impedes the fabrication of complex circuits having hundreds or more logic gates. [ 19,22,23 ] In this context, it stands

Clean Transfer of Wafer-Scale Graphene via Liquid Phase Removal of Polycyclic Aromatic Hydrocarbons.

Pentacene (C22H14), a polycyclic aromatic hydrocarbon, was used as both supporting and sacrificing layers for the clean and doping-free graphene transfer. After successful transfer of graphene to a target substrate, the pentacene layer was physically removed from the graphene surface by using intercalating organic solvent. This solvent-mediated removal of pentacene from graphene surface was investigated by both theoretical calculation and experimental studies with various solvents. The uses of pentacene and appropriate intercalation solvent enabled graphene transfer without forming a residue from the supporting layer. Such residues tend to cause charged impurity scattering and unintentional graphene doping effects. As a result, this clean graphene exhibited extremely homogeneous surface potential profiles over a large area. A field-effect transistor fabricated using this graphene displayed a high hole (electron) mobility of 8050 cm(2)/V·s (9940 cm(2)/V·s) with a nearly zero Dirac point voltage.

Atomically thin epitaxial template for organic crystal growth using graphene with controlled surface wettability.

A two-dimensional epitaxial growth template for organic semiconductors was developed using a new method for transferring clean graphene sheets onto a substrate with controlled surface wettability. The introduction of a sacrificial graphene layer between a patterned polymeric supporting layer and a monolayer graphene sheet enabled the crack-free and residue-free transfer of free-standing monolayer graphene onto arbitrary substrates. The clean graphene template clearly induced the quasi-epitaxial growth of crystalline organic semiconductors with lying-down molecular orientation while maintaining the "wetting transparency", which allowed the transmission of the interaction between organic molecules and the underlying substrate. Consequently, the growth mode and corresponding morphology of the organic semiconductors on graphene templates exhibited distinctive dependence on the substrate hydrophobicity with clear transition from lateral to vertical growth mode on hydrophilic substrates, which originated from the high surface energy of the exposed crystallographic planes of the organic semiconductors on graphene. The optical properties of the pentacene layer, especially the diffusion of the exciton, also showed a strong dependency on the corresponding morphological evolution. Furthermore, the effect of pentacene-substrate interaction was systematically investigated by gradually increasing the number of graphene layers. These results suggested that the combination of a clean graphene surface and a suitable underlying substrate could serve as an atomically thin growth template to engineer the interaction between organic molecules and aromatic graphene network, thereby paving the way for effectively and conveniently tuning the semiconductor layer morphologies in devices prepared using graphene.

Dielectric substrate effect on the temperature-dependent electrical properties of pentacene films

Developing better contacts on dielectrics is one of the main challenges for pentacene-based transistor technology. This study investigates the effect of inorganic dielectrics on the temperature-dependent electronic property of pentacene films. It is found that the carrier mobility in the pentacene film deposited on a SiN x dielectric is higher than that in the pentacene film deposited on a SiO2 dielectric. However, the carrier density does not change substantially. The dependence of the carrier mobility upon temperature indicates the dominance of tunneling (hopping) at low (high) temperatures. The Hall-effect analysis by using the polaron theory revealed that the enhanced carrier mobility is due to the modified spacing between molecules in the pentacene layer.

Pn-Heterojunction effects of perylene tetracarboxylic diimide derivatives on pentacene field-effect transistor.

We investigated the heterojunction effects of perylene tetracarboxylic diimide (PTCDI) derivatives on the pentacene-based field-effect transistors (FETs). Three PTCDI derivatives with different substituents were deposited onto pentacene layers and served as charge transfer dopants. The deposited PTCDI layer, which had a nominal thickness of a few layers, formed discontinuous patches on the pentacene layers and dramatically enhanced the hole mobility in the pentacene FET. Among the three PTCDI molecules tested, the octyl-substituted PTCDI, PTCDI-C8, provided the most efficient hole-doping characteristics (p-type) relative to the fluorophenyl-substituted PTCDIs, 4-FPEPTC and 2,4-FPEPTC. The organic heterojunction and doping characteristics were systematically investigated using atomic force microscopy, 2D grazing incidence X-ray diffraction studies, and ultraviolet photoelectron spectroscopy. PTCDI-C8, bearing octyl substituents, grew laterally on the pentacene layer (2D growth), whereas 2,4-FPEPTC, with fluorophenyl substituents, underwent 3D growth. The different growth modes resulted in different contact areas and relative orientations between the pentacene and PTCDI molecules, which significantly affected the doping efficiency of the deposited adlayer. The differences between the growth modes and the thin-film microstructures in the different PTCDI patches were attributed to a mismatch between the surface energies of the patches and the underlying pentacene layer. The film-morphology-dependent doping effects observed here offer practical guidelines for achieving more effective charge transfer doping in thin-film transistors.

Performance enhancement of pentacene and F16CuPc-based low-voltage devices using cross-linked blend gate dielectrics

Herein is reported the fabrication and systematic comparative analysis of low-voltage organic filed-effect transistors (OFETs) and inverters using bare ZrOx dielectrics and inorganic–organic hybrid CZB (cross-linked ZrOx/1,6-bis(trimethoxysily)hexane blend) dielectrics. Solution-processed sol–gel chemistry was employed to prepare the gate dielectrics. Two active layers of p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) were deposited on the dielectrics using the neutral cluster beam deposition method. Compared with bare ZrOx-based transistors and inverters, the CZB-based devices with low leakage current and high capacitance exhibited significantly higher hole and electron carrier mobilities of (0.12 → 1.03) and (1.3 × 10−3 → 4.9 × 10−3) cm2 (Vs)−1, respectively, and enhanced gains of (9.4 → 13.3), together with large output voltage swings and sharp inversions in the voltage transfer characteristics (VTCs). The CZB-based inverters also exhibited improved noise margins due to the higher gain and better symmetry of the VTCs compared with their bare ZrOx-based counterparts. The results indicate that on the basis of the enhanced electrical properties of CZB dielectrics and the growth of high-quality crystalline semiconducting films on CZB dielectric surfaces, such high-performance devices operating at low voltage levels are promising potential components for integrated circuits.

Analysis of improved characteristics of pentacene thin-film transistor with an embedded copper oxide layer

Organic thin-film transistor (OTFT) based on pentacene semiconductor with an embedded copper oxide (CuO) thin layer is investigated. With the 3 nm-thick CuO layer embedded in the pentacene semiconductor, the drain current of the OTFT increases more than 3 times compared with that of pentacene organic field-effect transistor without CuO layer, and the absolute threshold voltage reduces from -21 V to -7.9 V. The hole mobility and current on/off ratio are much improved. It is interpreted by the mechanism based on the analysis of the interface charge transfer between pentacene layer and CuO layer. Results of X-ray photoelectron reveal electron transfer from pentacene to high work function CuO and the formation of charge transfer (CT) complexes based on electron transfer near the contact of CuO and pentacene. The CT complexes between pentacene layer and CuO layer could reduce the exponential density of state near the band edge of pentacene and the pentacene bulk hole trap density, and enhance the pentacene bulk hole carriers injection, which leads to the improvement of the field-effect mobility of OTFT with CuO layer. Electrons are transfered from the highest occupied molecular orbital of pentacene to the thin CuO layer which can generate holes in pentacene. The generated hole has the same effect as that with applying negative gate voltage which influences the threshold voltage. The drain current of the device increases and the threshold voltage shifts from -21 V to -7.9 V. Therefore, the thin CuO layer that is directly embedded in the organic semiconductor layer, serves as the hole-injection layer, which is responsible for reducing the contact barrier of OTFT with CuO layer.