PD SOI MOSFETs Research Articles

Leaky-integrate-fire neuron based on vertically extended drain Si[formula omitted]Ge[formula omitted] source TFET: Ultra-energy-efficient and high speed design

This article investigates the performance of a vertically extended drain double gate Si1−x Gex source tunnel field effect transistor (VD-DG-Si1−x Gex S-TFET) as a leaky integrate-and-fire (LIF) neuron. The proposed VD-DG-Si1−x Gex S-TFET structure has been designed and optimized by deploying the commercially available Silvaco TCAD. The LIF neuron using VD-DG-Si1−x Gex S-TFET requires a low spiking threshold voltage (i.e. 0.20 V) which is 5x, 3x, 5x, 1.3x, 1.55x, 7.5x, and 1.44x times less in comparison to MOSFET, Bulk FinFET, phase change device, SOI MOSFET, DG-JLFET, silicon nanowire, and DL-TFET silicon neuron. The proposed device based neuron demonstrates the least spiking energy (177 ZJ) reported to date which is 18192 times less as compared to BTBT based PDSOI MOSFET neuron. The threshold value of current is achieved at 0.20 V drain voltage which is 15x, 14x, 10x, and 1.5x less as compared to FinFET, PD-SOI MOSFET, LBIMOS, and DL-TFET, respectively. Moreover, the effects of gate metal work function, germanium mole fraction, and temperature on the spike current variations have also been investigated. Here, impact ionization is a key method for generating a neuron spike due to holes accumulated in the potential well of VD-DG-Si1−xGex S-TFET. In addition, a LIF neuron based on VD-DG-Si0.5Ge0.5 S-TFET device exhibits a 9 THz spiking frequency which is approximately 12 times higher than real nerves present in the human body. This work shows a remarkable reduction in the power consumption and the proposed device neuron is a potential start-up solution for a large scale spiking neural networks (SNN) implementation because of its better performance and compact circuitry.

Emulation of neuro-mimetic dynamics via GaSb/Si heterojunction V-DGTFET leaky-integrate-fire silicon neuron

A leaky integrate and fire (LIF) neuron property is emulated using vertically developed double gate GaSb/Si tunnel field effect transistor (V-DGTFET). The suggested device can precisely replicate the neuronal dynamics after considering and proper validating the numerical simulations. Silvaco-TCAD tool is exploited for emulation of neuronal attributes and found in good agreement with earlier published research data. The article reports the membrane threshold voltage of 0.47 V which is 3.2x, 2.13x, 2.13x, 1.28x times less as compared to silicon nanowire, MOSFET, phase change device and Bulk FinFET neuron. The energy required for mimicking the neurons is computed as 0.748 aJ which is 1.2 × 109, 4 × 107, 4.68 × 107, 1.34 × 107, 7.59 × 106, 8.42 × 103, 4.30 × 103 3.34 × 105, 2.41 × 105, 1.52 × 106, 26.7,2, 3.88 × 103 times less compared to CMOS, phase change device, SOI CMOS, PCMO RRAM, SiNPN, Bulk FinFET, BTBT based PDSOI MOS, FBFET, LBIMOS, DGJLFET, Si NIPIN, DL-TFET, silicon nano wire respectively. The biasing at second gate is used to induce potential well at channel region to accumulate hole carriers produced due to impact ionization. The threshold current is achieved at 0.20 V drain voltage which is 15x, 14x, 10x, and 1.5x less as compared to FinFET, PD-SOI MOSFET, LBIMOS, and DLTFET respectively. Furthermore, calculated spiking frequency of V-DGTFET LIF neuron is 534 GHz. Thus, remarkable enhancement in frequency of operation and an ultra-low energy per spike makes this neuron device a potential solution for implementing the neuro-mimetic behaviour at large scale.

Effect of Total Dose Irradiation on Parasitic BJT in 130 nm PDSOI MOSFETs.

In this work, the effects of total dose irradiation on the parasitic bipolar junction transistor (BTJ) in 130 nm PDSOI MOSFETs were investigated. The experimental results demonstrate that irradiation-induced oxide-trap charges can modify the E-B junction barrier, and thereby make the common-emitter gain β0 of the parasitic BJT in NMOS device increase, while decreasing it in a PMOS device. Additionally, irradiation-generated oxide-trap charges in shallow trench isolation (STI) elevate the surface electrostatic potential of the gate above the STI sidewall, thus providing an additional channel from the emitter to the collector. Moreover, these charges may generate parasitic reverse conductive paths at the STI/Si interface under high dose irradiation, thereby enhancing the leakage current in the front gate channel and diminishing the significance of the parasitic BJT. Under irradiation, the electric field intensity difference between two biases leads to higher β0 of the parasitic BJT in PG-biased devices than in ON-biased ones. Furthermore, the lifting effect of irradiation on β0 increases in wide or short channel irradiated devices, which can be explained using simulations and an emitter current crowding effect model.

Ultra-Low Power Reconfigurable Synaptic and Neuronal Transistor for Spiking Neural Network

In this paper, we have proposed a novel reconfigurable synaptic and neuronal transistor (RSNT) at sub-10nm regime for the spiking neural network (SNN). From calibrated TCAD simulations, we demonstrated that the proposed RSNT mimics both synaptic and neuronal functionalities. The proposed RSNT comprises of two gates, front gate (FG) and back gate (BG) to configure as a synapse and neuron, respectively. We investigated the synapse characteristics such as short-term (ST) and long-term (LT) synaptic plasticity (STSP/LTSP). The STSP is distinguished in terms of short-term potentiation/depression and paired-pulse facilitation/depression (PPF/PPD). And the LTSP is characterized by analyzing the long-term potentiation/depression (LTP/LTD) and spike-timing-dependent plasticity (STDP). Moreover, the energy consumption of the RSNT device during the facilitation and depression events is 4.5 pJ and 6.0 pJ, respectively. The reconfigurable leaky integrate-and-fire (LIF) neuron requires 1.2 fJ energy per spike (E <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$_{spike}$</tex-math></inline-formula> ) for firing which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> × less E <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$_{spike}$</tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 9 × lower supply voltage as compared to the PD-SOI MOSFET based LIF neuron. The simulation results assures that the proposed RSNT with various synaptic and LIF neuronal characteristics at sub-10nm regime has potential application for the neuromorphic systems as it increases the integration density and eases the fabrication complexity.

Analysis of Kink Effect in Short-Channel Floating Body PD-SOI MOSFETs

The origin of a greater decrease in kink drain voltage Vkink in floating body PD-SOI MOSFETs with gate lengths shorter than 0.35 μm is newly revealed. The Vkink formula as a function of the internal body voltage and IDS is derived by combining the modified impact ionization multiplication factor with the body-source junction I-V equation. The parameters in this formula are extracted from the measured data of IB vs. IBS and -IB/IDS vs. VDS in the body contacted devices. By calculating the formula using the extracted parameters, it is newly found that a decrease of the drain-source saturation voltage at a shorter channel is a primary cause for the short-channel effect on Vkink reduction.

BTBT Based LIF Junctionless FET Neuron With Plausible Mimicking Efficiency

Amid the quest for nanoscale devices to mimic the biological neuronal dynamics, this article demonstrates a SOI Junctionless Field Effect Transistor (JLFET) based leaky integrate and fire (LIF) neuron in sub-20 nm technology. The band-to-band-tunneling (BTBT) mechanism is considered to imitate the leaky-integration behavior. As JLFET has strongly doped channel that supports fully depletion in the OFF state with considerable band overlapping of channel and drain regions that is subsequently allowing the BTBT in lateral direction. Moreover, the proposed device based LIF neuron requires neither metallurgical junction nor back gate bias to induce the floating body to confine the excess carrier. And, it requires only 0.4 V of supply voltage, which is much lower compared to its equivalent bulk FinFET and PD-SOI MOSFET based LIF neurons and it shows a GHz range of spiking frequency i.e., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 8 orders greater than biological neuron. Hence, it presumes that the proposed SOI JLFET based LIF neuron is more suitable for large scale hardware implementation of spiking neural network (SNN) due to its energy and area efficiency comparable with biological neuron along with CMOS compatibility.

PD-SOI MOSFET의 외부 캐패시턴스 추출을 위한 개선된 RF 방법

High resistivity(HR) partially depleted(PD) silicon-on-insulator(SOI) MOSFET의 accumulation 영역에서 기존의 외부 캐패시턴스 추출 방법의 부정확성을 확인하고 이를 제거하기 위해, 이전의 직접 추출 방법에서 무시되었던 내부 body 저항을 고려한 물리적인 off-state 등가회로를 사용하였다. 이러한 등가회로의 캐패시턴스 값들을 직접 추출하기 위하여 accumulation 영역에서 단순화된 off-state 등가회로를 구하고 Y-parameter 추출 방정식을 유도하여 사용하는 개선된 RF 방법을 제안하였다. 이와 같이 추출된 물리적 등가회로의 S-parameter를 측정 데이터와 30㎓까지 비교함으로써 개선된 추출 방법의 정확성을 검증하였다.

Investigation of the Gate Length and Drain Bias Dependence of the ZTC Biasing Point Instability of N- and P-Channel PD SOI MOSFETs

This paper presents an analysis of the instability of the Zero Temperature Coefficient (ZTC) as a function of the gate length and drain bias for partially depleted SOI MOSFETs operating at high temperatures (from room temperature up to 573K). The study takes into account temperature dependent model parameters such as threshold voltage and channel mobility. The analytical predictions are in very close agreement with experimental results in spite of the simplifications used for the VZTC model as a function of temperature in the linear and the saturation regime.

Simulation-Based Ultralow Energy and High-Speed LIF Neuron Using Silicon Bipolar Impact Ionization MOSFET for Spiking Neural Networks

The silicon bipolar impact ionization MOSFET offers potential for the realization of leaky integrated fire (LIF) silicon neuron due to the presence of parasitic bipolar junction transistor (BJT) in the floating body. In this article, we have proposed an L-shaped gate bipolar impact ionization MOS (L-BIMOS) with reduced breakdown voltage ( ${V}_{B} = {1.68}$ V) and demonstrated the functioning of LIF neuron based on the positive feedback mechanism of parasitic BJT. Using the 2-D TCAD simulations, we manifest that the proposed L-BIMOS exhibits a low threshold voltage (0.2 V) for firing a spike, and the minimum energy required to fire a single spike for L-BIMOS is calculated to be 0.18 pJ, which makes the proposed device 194 times more energy efficient than the PD-SOI MOSFET silicon neuron and ${5}\times {10}^{{3}}$ times more energy efficient than the analog/digital circuit-based conventional neurons. Furthermore, the proposed L-BIMOS silicon neuron exhibits spiking frequency in the gigahertz range when the drain is biased at ${V}_{\text {DG}} = {2.0}$ V.

A transient ionizing radiation SPICE model for PDSOI MOSFET

AbstractIn this paper, a transient ionizing radiation SPICE model for PDSOI MOSFET is proposed for the simulation of the rail‐span collapse. It is based on the present understanding of transient ionizing radiation effects. The model accounts for the generation and collection of radiation induced transient photocurrent, the influence of the device geometry, and the bias conditions. Verilog‐A behavioral modeling language is utilized to implement the physically based models of the transient current sources, eliminating the use of independent current sources and lumped SPICE element models. The model is validated by comparison with the Sentaurus TCAD simulation results. The comparison of simulation and experimental results of the 64K SRAM fabricated by the 0.13 μm PDSOI technology validates the effectiveness of the dose rate model.

Transient Response of 0.18-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;${\mu}$ &lt;/tex-math&gt; &lt;/inline-formula&gt;m SOI MOSFETs and SRAM Bit-Cells to Heavy-Ion Irradiation for Variable SOI Film Thickness

In this paper, the effect of silicon-on-insulator (SOI) thickness scaling in fully and partially depleted SOI (FD-SOI and PD-SOI) devices is analyzed for their transient response to heavy-ion irradiation. We have analyzed radiation performance of FD-/PD-SOI MOSFETs and 6-T SRAM bit-cells, conforming to 0.18- $\mu \text{m}$ technology node, using calibrated 2-D TCAD simulations. We, for the first time, report here that while SRAMs designed with FD-SOI devices have superior hardness to heavy-ion radiation, they are also more sensitive to SOI film thickness than the SRAMs designed with PD-SOI devices. The slopes of the critical linear energy transfer (LETC) to SOI film thickness curves are +1000 and −950 000 $\text {MeV}\cdot \text {cm/mg}$ for PD-SOI and FD-SOI devices at 1.8V supply voltage ( ${V} _{\text {DD}}$ ), respectively. The negative slope for FD-SOI device indicates better radiation performance for thinner silicon films, while a positive slope in PD-SOI device indicates better radiation performance with thicker silicon films. We further investigated the effect of ambient temperature and supply voltage ( ${V} _{\text {DD}}$ ) on SOI thickness scaled FD-/PD-SOI devices. We show that increasing ${V} _{\text {DD}}$ results in increased generated charge due to the heavy-ion at transistor level, whereas LETC of the SRAM bit-cell improves with increasing ${V} _{\text {DD}}$ . We further highlight that the heavy-ion radiation response as a function of ambient temperature depends not only on the thickness of the SOI film but also on the LET of the impinging heavy-ion.

Electrical performance of 130 nm PD-SOI MOSFET with diamond layout

Some special effects of SOI devices with diamond layout are analyzed in this paper based on the silicon data from 130 nm PD-SOI T-gate MOSFET. LCE and PAMDLE induced current gain dependence on geometry parameters of devices with fixed gate area and fixed smallest channel lengths are presented. BVDS of different diamond devices are studied and discussed and a specified geometry has been found with better BVDS performance. For the special shape of channel region, the hot-carrier effect induced body current is collected in the experiment and the mechanism of body current increasing has been analyzed theoretically.

A Simulation Model for the H-gate PDSOI MOSFET

A Simulation Model for the H-gate PDSOI MOSFET

The Impact of Mechanical Strain on Reliability Issue for PD SOI MOSFETs

This work studies the impact of mechanical strain on reliability issue for partial depleted silicon-on-insulator metal-oxide-semiconductor field effect transistors (PD SOI p-MOSFETs), including negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-MOSFETs and n-MOSFETs, respectively. Based on AEI model, the mechanical compressive strain was introduced into the SOI p-MOSFET under NBT stress. It shows the strained FB device exhibits a much less NBTI degradation, since significant accumulation of electron induced by strain-induced band gap narrowing, reducing the EOX during NBT stress. Additionally, the degradation of HCS on SOI n-MOSFETs is also studied. It can be seen that the FB device shows worse degradation than GB device due to FBEs. However, the impact of mechanical strain results more serious degradation on HCS for GB device. Therefore, based on the lucky electron mode, we found that strain-induced band gap narrowing dominates the increase in impact ionization rate, aggravating HCS.

Investigation of Random Telegraph Signal with PD SOI MOSFETs

not Available.

Investigation of Mechanisms and Random Telegraph Signals in Static and Dynamic BTI Stress on PD SOI MOSFETs

not Available.

The Impact of Mechanical Strain on Reliability Issue for PD SOI MOSFETs

not Available.

Enhanced gate-induced floating-body effect in PD SOI MOSFET under external mechanical strain

The influence of tensile mechanical strain on gate-induced floating-body effect (GIFBE) in advanced partially depleted SOI n-MOSFETs was investigated. Both drain current and mobility enhance after applying strain due to the reduction of average transfer effective mass. However, it was found that the GIFBE becomes serious under the mechanical strain. To explain this phenomenon, we first clarify the mechanism of GIFBE using different operation conditions. The experiment results indicate that the GIFBE can be attributed to the anode hole injection (AHI) rather than the widely accepted mechanism of electron band (EVB) tunneling. Based on the AHI model, the enhanced GIFBE under the mechanical strain is mainly due to the narrowing of band gap induced by the strain in the poly-gate.

Improved Charge Sheet Model for PD SOI Sub-Micron MOSFETs

This paper presents an Improved Charge Sheet Compact Model (ICSM) especially valuable to describe the nonlinearities present in the triode region and in the transfer characteristics in saturation. Modeled characteristics were compared with measured for analog PD SOI MOSFETs with body contact, having channel lengths from 220 nm to 120 nm. A very good agreement was observed for all analyzed I-V curves, derivatives and harmonic analysis. The model uses only analytical expressions and was implemented in SMARTSPICE.

Dose rate dependence of the back gate degradation in thin gate oxide PD-SOI MOSFETs by 2-MeV electron irradiation

The degradation of the electrical properties of thin gate oxide PD-SOI n-MOSFETs by 2-MeV electrons at different dose rates is presented. The degradation of the back channel and its dependence on dose rate are clarified. The characteristics of the PD-SOI MOSFETs are degraded, and the degradation becomes higher for a low dose rate. The magnitude of the hysteresis characteristics in the drain current becomes smaller after irradiation, and the degradation for a low dose rate is higher than for a high dose rate. It is found that the degradation of the front characteristics is related to the back gate degradation by the coupling effect.