After some early successes with electroless Cu for printed circuit board wiring (1), and the use of electroless Co-based magnetic films over non-magnetic electroless nickel films on rigid Al disks in the magnetic storage industry, for several years, electroless deposition was never far from researchers’ interest in the field of microelectronics. This was in part due to the hope that it might replace some of the expensive vacuum metallization methods with less expensive and selective, or self-aligned, deposition methods. Electrolytic Cu deposition won out over electroless Cu deposition for CMOS BEOL (back-end-of-line) interconnect applications for a variety of reasons, including superior filling characteristics, conductivity, electromigration resistance, solution additives, relatively more stable solutions, absence of co-evolution of H2 gas, and higher deposition rates. A decade or more ago, it looked as if it electroless Co(W)(P) (2) was the ideal candidate to replace PVD Ta-based liners for CMOS BEOL builds, but despite meeting selectivity, diffusion barrier and reliability requirements, it was discarded, in part for cost reasons. In addition to the subtlety of its mechanisms and range of solution formulations, electroless deposition has much to offer in terms of niche applications, which explains why it is often turned to first by researchers seeking creative deposition methods in the still emerging field of nanofabrication. Examples pertinent to both “mainstream” and exploratory uses of electroless deposition will be discussed in this talk, including: capping layers to prevent interconnect Cu oxidation; diffusion barriers, and novel uses in nanofabrication. However, a brief discussion of the strong and weak points of electroless deposition in the context of use in nano/microfabrication will first be undertaken. While electroless deposition is capable of depositing only a limited number of metals and alloys compared to electrodeposition, materials with unique properties, such as Ni(P) (corrosion resistance) and Co(P) (magnetic properties), are readily obtained by electroless deposition. It is in principle easier to obtain coatings of uniform thickness and composition using the electroless process, since one does not have the current density uniformity problem of electrodeposition. Most electroless solutions operate in a mode approximating kinetic control. Strongly-adsorbing solution stabilizers, usually present in ppm-type concentrations, tend to decrease the deposition rate, though the classic, environmentally-unfriendly stabilizers like Pb2+ have been largely phased out. Rates will be lower for features smaller than the stabilizer diffusion layer thickness, while the edges of features, which experience higher stabilizer levels due to enhanced nonplanar diffusion, may experience reduced deposition rates, or may remain uncoated in extreme cases. To compound this problem, dissolved O2 gas effects the mixed potential of the surface being coated in the electroless solution since it is capable of being reduced; since the dissolved O2 is present in low concentration, similar nonplanar diffusion effects on coverage uniformity are observed. The presence of solution stabilizers and dissolved O2 may impart a practical lower limit to feature size that can be reproducibly fabricated using electroless deposition; solution agitation will play a major role in determining this practical feature size limit. We recently developed a maskless, electroless, high-P-content, Ni(P) process to protect the final Cu bitline wiring level in our STTM MRAM test vehicle to enable functional testing in an air atmosphere at elevated temperatures for evaluation of MRAM device memory state retention. The process was developed as a replacement for the final Al level, and had a drastically shorter process time. We demonstrated an electroless Ni(P) that selectively deposited on Cu bit lines with effective spacing approaching 200 nm without shorting, for coating thicknesses up to ca. 50 nm, with excellent bitline coverage (few pinholes). This was achieved through optimization of Cu surface cleanliness using a wet clean solution, followed by surface catalyzation using an acidic Pd solution, and finally immersion in the electroless Ni(P) solution for a fixed time. Testing (R & MR type) of Ni(P)-coated wafers, showed virtually unchanged resistance and MR for MRAM 4Kb arrays encompassing a large range of device critical dimensions (CDs). Figure 1 shows a topdown SEM image of a region of electroless Ni(P)-coated Cu bitlines. [1]. Please refer to papers in IBM J. Res. Develop., Vol. 28, Issue 6, year 1984, available online. [2]. See, e.g., Y. Shacham-Diamand, Y. Sverdlov and N. Petrov, J. Electrochem. Soc., 148(3) (2001) C162. Acknowledgements The authors gratefully acknowledge the efforts of the staff of the Microelectronics Research Laboratory (MRL) at the IBM T. J. Watson Research Center, where some of the fabrication work described in this talk was carried out. Figure 1
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Sep 25, 2020
Chantal Diverchy + 3
Open Access