PD SOI NMOS Research Articles

Computational model for predicting structural stability and stress transfer of a new SiGe stressor technique for NMOS devices

A new method to induce tensile stress in a PDSOI NMOS device for RF applications is proposed, which is based on relaxing a SiGe layer built underneath silicon. By means of TCAD simulations, we demonstrate that stress transfer from SiGe to Si occurs by means of at least two different mechanisms: SiGe relaxation due to amorphization and the formation of Stacking Faults during recrystallization. By considering both phenomena, a tensile stress of 0.5 GPa can be injected into the silicon channel. Moreover, the impact of annealing steps on the detrimental out-of-SiGe Ge diffusion has been simulated by considering an inter-diffusion model, showing the importance of adapting the PDSOI process flow to account for the presence of the new stressor.

The characterization of the built-in bipolar junction transistor in H-gate PD-SOI NMOS

The built-in bipolar junction transistor of H-gate partially depleted SOI NMOS was characterized by measuring the common-emitter output curve and calculating the common-emitter current gain. Unoptimized doping results in a low common-emitter current gain. The bias state of the front gate of the MOS has a significant influence on the characteristics of the built-in BJT. The geometry effect of the device is also studied. It is proved by mathematical analysis that the emitter current crowding effect also exists on the built-in BJT.

X-band T/R switch with body-floating multi-gate PDSOI NMOS transistors

This paper presents an X-band transmit/receive switch using multi-gate NMOS transistors in a silicon-on-insulator CMOS process. For low loss and high power handling capability, floating body multi-gate NMOS transistors are adopted instead of conventional stacked NMOS transistors, resulting in 53% reduction of transistor area. Comparing to the stacked NMOS transistors, the multi gate transistor shares the source and drain region between stacked transistors, resulting in reduced chip area and parasitics. The impedance between bodies of gates in multi-gate NMOS transistors is assumed to be very large during design and confirmed after measurement. The measured input 1 dB compression point is 34 dBm. The measured insertion losses of TX and RX modes are respectively 1.7 dB and 2.0 dB at 11 GHz, and the measured isolations of TX and RX modes are >27 dB and >20 dB in X-band, respectively. The chip size is 0.086 mm2 without pads, which is 25% smaller than the T/R switch with stacked transistors.

基于自热修正的SOI NMOSFETs 热载流子注入效应寿命预测方法

Self-heating effect (SHE) is one of the key concerns for the reliability issues of SOI MOSFETs. The unavoidable SHE during HCI test may underestimate the devices performance and lead to the inaccurate lifetime prediction. In this paper, a new method is proposed to accurately predict the lifetime of 0.18 μm PD-SOI NMOS device based on DC HCI stress. The temperature increase (Tsh) caused by SHE is quantitatively extracted by gate resistance measurement. Then, the degradation part due to SHE is removed to accurately extrapolate lifetime of PD-SOI NMOSFET device using substrate/drain current ratio model. As a result, the extrapolated lifetime of 0.18 μm SOI NMOS illustrates a significant difference by 63.5% whether considering removal of SHE or not, indicating that the impact of SHE on the reliability issue of SOI device can not be ignored, otherwise leading to the inaccurate lifetime prediction.

Total ionizing dose effect in 0.2 μm PDSOI NMOSFETs with shallow trench isolation

This paper presents the total ionizing dose radiation performance of 0.2μm PDSOI NMOS devices under different bias conditions. The hump effect is observed in the transfer characteristic of the back gate device instead of the front gate device after radiation. A STI bottom corner parasitic transistor model is proposed to explain this phenomenon. It also provides a simple way to extract the effective sheet charge density along the STI sidewall. Three-dimensional simulation was applied to explain the radiation effect. It shows that charge trapped in the shallow trench isolation, particularly at the bottom region of the trench oxide where the STI and the BOX are connected, is the dominant contributor to the off-state drain-to-source leakage current. The dimension of the transistor plays an important role on influencing the device’s performance after radiation. Larger off-state leakage current and radiation induced threshold voltage shift are reported in the narrow channel device than in the wide channel one. Different TID responses due to the STI process variation are also discussed.

Function of the parasitic bipolar transistor in the 40 nm PD SOI NMOS device considering the floating body effect

This paper reports the function of the parasitic bipolar device in the 40nm PD SOI NMOS device with the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during DC and transient operations could be modelled. During the turn-on transient by imposing a step voltage from 0V to 2V on the gate, the case with the a slower rise time shows a relatively faster turn-on in the drain current due to a stronger function of the parasitic bipolar device from smaller displacement currents through the gate oxide, as reflected in the current gain, as verified by the experimentally measured result.

Gate length dependence of SOI NMOS device response to total dose irradiation

The gate length dependence of PD SOI NMOS device on total dose irradiation is investigated, which is exposed to 60Co gamma ray at a dose rate of 50 rad(Si)/s. The result shows that the transistor with shorter gate length shows larger radiation-induced interface trap density, which leads to the maximum transconductance degradation. The local floating body effect induces the output characteristic variation of irradiated MOSFET with gate length. After irradiation, the breakdown voltage of short channel SOI device decreases. Due to the buried oxide, the radiation-induced degradation of short channel SOI device is much serious compared with that of long channel SOI device.

Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect

This paper reports an analysis of floating body effect related gate tunneling leakage current behavior of the 40 nm PD SOI NMOS device using bipolar/MOS equivalent circuit approach. As confirmed by the experimentally measured data, the bipolar/MOS equivalent circuit approach could predict the gate tunneling leakage current behavior, which is strongly affected by the parasitic bipolar device in the floating body as observed from the perpendicular electric field along the path of the U-shaped edges of the polysilicon gate.

Shallow trench isolation-related narrow channel effect on the kink behaviour of 40nm PD SOI NMOS device

This paper reports the shallow trench isolation (STI)-related narrow channel effect (NCE) on the kink behaviour of the 40 nm PD SOI NMOS device. As verified by the experimentally measured data, with a smaller channel width, the onset of the kink effect behaviour occurs at a higher drain voltage and the breakdown voltage is also larger due to the weaker parasitic bipolar device in the floating thin film as a result of a smaller electron recombination lifetime caused by the STI-related defect effect.

Analysis of STI-induced mechanical stress-related Kink effect of 40 nm PD SOI NMOS devices biased in saturation region

This paper reports the shallow trench isolation (STI)-induced mechanical stress-related Kink effect behaviour of the 40 nm PD SOI NMOS device. As verified by the experimentally measured data and the 2D simulation results, the Kink effect behaviour in the saturation region occurs at a higher V D for the 40 nm PD device with a smaller S/D length (SA) of 0.17 μm as compared to the one with the SA of 1.7 μm due to the higher body-source bandgap narrowing (BGN) effect on the parasitic bipolar device (BJT) from the higher STI-induced mechanical stress, offset by the impact ionization (II) enhanced by the BGN in the high electric field region near the drain.

ON THE RELATIONSHIP BETWEEN EFFECTIVE ELECTRON MOBILITY AND KINK EFFECT FOR SHORT-CHANNEL PD SOI NMOS DEVICES

Here, a new approach for calculating the triggering drain bias at the onset of the kink effect, kink voltage, V kink , for PD SOI NMOS devices utilizing electron drift properties in the channel is given. This approach directly relates electron mobility in the channel to the kink effect and enables one to determine kink voltage knowing the device technology. It also gives the possibility for calculating mobility from the kink voltage. Theory is compared to the previously published experimental results and based on this match, the behavior of the kink voltage for PD SOI NMOS components for various technology parameters is predicted. Explanation for the appearance of the kink in the volt regime below the band gap of silicon is also given. From this consideration, design rules for PD SOI NMOS devices are derived in order to soothe the kink effect.

Breakdown Behavior of 40-nm PD-SOI NMOS Device Considering STI-Induced Mechanical Stress Effect

This letter reports the shallow-trench-isolation (STI)-induced mechanical-stress-related breakdown behavior of the 40-nm PD-SOI NMOS device. As verified by the experimentally measured data and the 2D simulation results, breakdown occurs at a higher drain voltage for the device with a smaller S/D length of 0.17 mum due to the weaker function of the parasitic bipolar device, which is offset by the stronger impact ionization in the post-pinchoff region coming from the bandgap narrowing generated by the STI-induced mechanical stress.