Pattern Jitter Research Articles

An improved algorithm for timing error detection based on all-digital receiver

In view of the wide application of the Gardner algorithm in timing synchronization loop and its limitation of the band-limited signals, an enhanced Gardner timing error detection algorithm, which has a simple structure and can effectively reduce the deviation of the timing error and system self- noise, is proposed in this paper by comparison of the Gardner algorithm and its correction algorithm in both the pattern jitter and timing errors on the basis of the asynchronous sampling. The simulation results show that E-Gardner algorithm has a significant improvement in the performance of QPSK modulation signal’s clock capture and error detection in the case of a small roll-off factor under the Gaussian with Rayleigh fading channel.

Minimizing the Jitter of Duty Cycle Distortion Correction Technology Based on Cross Point Eye Diagram Correction

Pattern jitter is a primary contributor to the increase of the bit error rate (BER) in high-speed communications, which occurs in large part due to duty cycle distortion (DCD). By considering DCD caused by transmission links and the distribution of jitter in DCD due to the pattern of the transmission link, this paper proposes a precise control method based on the cross point of the eye diagram to minimize the jitter associated with DCD and to effectively decrease the BER of high-speed digital communications. By capitalizing on the theoretical basis that the main form of DCD is the offset of the cross point of the eye diagram, the technology presented here reconstructs the pattern waveform by using a digital method and incorporates a time variable to precisely control the data edge position during the reconstruction process, thereby stabilizing the cross point at 50% to correct its drift. Accordingly, after fanning out the original pattern buffer and then passing two controllable delay lines with different delays through the buffer in a process that is driven by digital logic operation, the cross point of the waveform is reconstructed by changing the relative time delay of the two signals. As a result, the change in the position of the cross point of the eye diagram is transformed into the precise control of the relative time delay, minimizing the DCD jitter. The theoretical model is verified by experiments, indicating that this method can control the cross point of the non-return-to-zero (NRZ) pattern in the range of 30% to 70% under 3 Gbps with a resolution as great as 1%. Furthermore, this approach can solve the problem of cross point drift of the eye diagram and can significantly decrease the BER caused by DCD jitter.

Signal Integrity Performance Analysis of Mutual Coupling Reduction Techniques Using DGS in High Speed Printed Circuit Boards

In this article, the Signal Integrity performance analysis of mutual coupling reduction with defective ground structures (DGS) in high speed PCBs has been investigated. The performances of these structures are analyzed, in terms of Time domain, Error Vector Magnitude (EVM), eye pattern and timing jitter. A NRZ test signal with Quadrature Phase Shift keying modulation, with a carrier frequency of 3.5 GHz is used for the EVM measurements. From the EVM measurements, it is observed that the PCB with Circular DGS has the lowest EVM of 1.195 % rms compared to other techniques. Further, the eye pattern and jitter analysis show that the circular DGS has the lowest jitter value of 8 ps at 1Gbps data rate. Finally, the electromagnetic compatibility of proposed method is checked with the surface current distribution and radiated emission analysis. These investigations show that the adoption of the circular DGS in the high speed PCB design, reduces the spacing between two traces without degrading the signal quality.

Hybrid Screening Technology by Error Diffusion Algorithm

As the traditional AM and FM screening are of their own shortcomings, hybrid screening has become a mainstream screening methods. According to the principle of hybrid screening, this paper studies the application of different separations hybrid screening methods, on the basis of the AM screening, pattern jitter FM screening and error diffusion theory.

A fast-acquisition PLL using split half-duty sampled feedforward loop filter

We reduce the pattern jitter and acquisition time of a phase-locked loop (PLL) by adopting the split half-duty sampled feedforward loop filter. A prototype designed and fabricated in a 0.18μm standard CMOS technology has a 40% lower acquisition time than a PLL without operating in fast acquisition mode. Its peak-to-peak jitter is 26% less than that of a PLL with a conventional 2nd-order RC loop filter.

A Rate and History-Preserving Resampling Algorithm for Neural Spike Trains

Resampling methods are popular tools for exploring the statistical structure of neural spike trains. In many applications, it is desirable to have resamples that preserve certain non-Poisson properties, like refractory periods and bursting, and that are also robust to trial-to-trial variability. Pattern jitter is a resampling technique that accomplishes this by preserving the recent spiking history of all spikes and constraining resampled spikes to remain close to their original positions. The resampled spike times are maximally random up to these constraints. Dynamic programming is used to create an efficient resampling algorithm.

A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique

The PLL circuit described here performs the function of data and clock recovery for random data patterns by using a sample-and-hold technique, and four component circuits (a phase comparator, a delay circuit, a voltage-controlled oscillator, and a S/H switch with a low-pass-filter) were specially designed to further stabilize the PLL operation. A test chip fabricated using Si bipolar process technology demonstrated error-free operation with an input of 2/sup 23/-1 PRBS data at 156 Mb/s. The rms data pattern jitter was reduced to only 1.2 degrees with only an external power supply bypass capacitor.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Inherent pattern jitter of STM-64 format signal and a reduction method

The inherent pattern jitter of the STM-64 format signal is found to be increased by the DC level fluctuation of incoming data and the output power variation of the timing tank in the section overhead bytes which become longer than the time constant of the timing tank. This pattern jitter is reported to be success fully suppressed by using an already proposed timing recovery circuit with a 1/2T differentiator, which operates as a pattern transformer.

Zero-crossing DPLL bit synchronizer with pattern jitter compensation

A digital phase-locked loop (DPLL) bit synchronizer that tracks the zero crossings of a bandlimited binary signal is discussed. The synchronizer reduces pattern jitter or self noise with a compensation signal in the synchronizer feedback loop without using a prefilter. Analytical results are derived for the timing jitter variance (additive noise and self noise) of the synchronizer. Computer simulations and laboratory measurements are shown to verify the effectiveness of the pattern jitter compensation techinque for a synchronizer operating with both spectral raised cosine signaling pulses as well as for signaling pulses generated by a realizable filter network. Implementation of the pattern jitter compensation method in an adaptive synchronizer structure for applications where a priori knowledge of the signaling pulse shape is not available is also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new pattern jitter free frequency error detector

One method to enable fast acquisition of a phase-locked loop (PLL) in spite of large frequency offsets and small PLL bandwidths is to use an additional AFC (automatic frequency control) loop. A suitable frequency error detector (FED) for large frequency offsets is the well-known balanced quadricorrelator. This FED is shown to produce great pattern jitter if it is to work with digital modulated MQAM and MPSK signals (M>2) and random data. The authors describe how this pattern jitter for MQAM and MPSK signals can be overcome completely. Another understanding of the balance quadricorrelator is also given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A single-chip three-level regenerator IC for high-speed optical transmission systems applying duo-binary coding schemes

A three-level regenerator IC operating at 160 Mbit/s or more has been developed for high-speed optical transmission systems, such as local area network and computer links. It was a modified duo-binary class-II coding scheme and provides good performance for long-period pattern transients. Two decision circuits and a nonlinear timing extraction circuit consisting of 430 transistors and resistors are monolithically integrated on a single 2.5/spl times/2.5-mm/SUP 2/ chip using 3-/spl mu/m Si bipolar IC technology. The ICs are primarily designed for a 160-Mbit/s transmission bit rate, with a 1.2-1/24 mark ratio, a 5 V/spl plusmn/10% supply voltage, and 0-70/spl deg/C temperature range. The following characteristics are achieved: 5 mV decision sensitivity, +9.8/-7.8/spl deg/ static pattern jitter, /spl plusmn/7/spl deg/ timing phase shift, transition time of 0.95 ns, and power dissipation of less than 470 mW.

Jitter Accumulation for Periodic Pattern Signals

It is important to accurately evaluate and reduce jitter accumulation in long-haul digital repeatered lines. Jitter accumulation caused by random pattern signals has already been analyzed. However, periodic pattern signals such as pseudorandom signals are usually used to measure jitter accumulation. This paper describes the difference between the jitter accumulation for both signals and the necessary conditions to accurately estimate jitter accumulation for random pattern signals by using periodic pattern signals. First, it is shown theoretically that systematic jitter for periodic signals saturates, showing a ripple pattern. The limit of increase is determined by the ratio of tank bandwidth and pattern repetition frequency. Up to a certain number of regenerators determined by the ratio, systematic jitter increases in rough proportion to the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\sqrt{N}</tex> slope. It is also shown that the equation to estimate random pattern jitter accumulation is determined by the measured value for periodic pattern signals. Second, jitter characteristics are simulated by optical signal circulating experiments. The results are in agreement with the analysis. In addition, the reduction effects on periodic signal jitter accumulation caused by timing signal delay and nonlinearity of the limiter in the timing circuit are shown.

Transformation and relational-structure schemes for visual pattern recognition

Two models for visual pattern recognition are described; the one based on application of internal compensatory transformations to pattern representations, the other based on encoding of patterns in terms of local features and spatial relations between these local features. These transformations and relational-structure models are each endowed with the same experimentally observed invariance properties, which include independence to pattern translation and pattern jitter, and, depending on the particular versions of the models, independence to pattern reflection and inversion (180 degrees rotation). Each model is tested by comparing the predicted recognition performance with experimentally determined recognition performance using as stimuli random-dot patterns that were variously rotated in the plane. The level of visual recognition of such patterns is known to depend strongly on rotation angle. It is shown that the relational-structure model equipped with an invariance to pattern inversion gives responses which are in close agreement with the experimental data over all pattern rotation angles. In contrast, the transformation model equipped with the same invariances gives poor agreement to the experimental data. Some implications of these results are considered.

400 Mbit/s Digital Repeater Circuitry Provided by a New Design Method and Beam Lead GHz Transistors

A stable, compact, and high-performance regenerative repeater circuitry, suitable for digital transmission systems up to several hundred Mbit/s, has been provided through utilization of new devices, such as 7 GHz beam lead shielded junction transistors, and through a new computer-aided design method, and has been successfully applied to the 400 Mbit/s experimental coaxial cable PCM system. Major features of this repeater circuitry are: (1) an equalizing amplifier with low noise figure (7.6 dB), small intersymbol interference (12%), and automatic line equalization of 21 dB tracking range at 200 MHz; (2) a regenerative output circuit with bipolar pulses of 2.4 Vop amplitude and 700 ps rise time; and (3) total performance with sufficient noise margin (10 dB for error rate 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-11</sup> over a line of 56 dB loss at 200 MHz), small static pattern jitter (20°pp), smaller size ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">270 \times 160 \times 52</tex> mm), and lower power (5.8 W). These have been achieved by use of: (1) new devices such as beam lead transistors with f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> of 7 GHz, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Le</tex> of 0.2 nH and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Cob</tex> of 0.4 pF and tantalum thin film hybrid integrated circuits; and (2) a new CAD system including block simulation, network design/ simulation, layout design subsystems which use transmission quality (error rate and jitter) as a design criterion, and which can also be directly connected to the manufacture automation systems, e.g., for mask preparation, and transistor mounting by bonding.