Pattern Count Research Articles

Compact pattern set generation for accelerated small delay defect testing

Faster-than-at-speed testing (FAST) approach significantly enhances the detection quality of small delay defects (SDD). However, it encounters the challenge of an increased number of test options. Also, selecting the optimal test clock periods is crucial to prevent test escapes and avoid overtesting the circuit. This paper presents a state-of-the-art test clock data set-based feedback-driven clock selection algorithm to enhance quality while maintaining a compact pattern set with fewer test clock periods. The algorithm's advantages become apparent when combined with an appropriate base pattern repository. For this purpose, the proposed method employs various combinations of timing-aware (TA) patterns, topped off with transition delay fault (TDF) patterns. The effectiveness of the proposed framework is validated by generating the test options that maximize the Weighted Slack Percentage (WeSPer) quality metric using a test optimization technique. The technique was validated using the ISCAS89 and ITC99 benchmark circuits. It exhibited a superior performance by reducing the pattern count to approximately 2x times the TDF patterns with a reduced number of test clock periods. Additionally, it achieved a 100% utilization of the selected test clock periods, while incurring only a maximal WeSPer loss of 0.15%.

A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow

Minimizing the testing cost is crucial in the context of the design for test (DFT) flow. In our observation, the test patterns generated by ATPG tools in test compression mode still contain redundancy. To tackle this obstacle, we propose a post-flow static test compaction method that utilizes a partial fault dictionary instead of a full fault dictionary to sharply reduce time and memory overhead, and leverages a dedicated Pure MaxSAT solver to re-compact the test patterns generated by ATPG tools. We also observe that ATPG tools offer a more comprehensive selection of candidate patterns for compaction in the “n-detect” mode, leading to superior compaction efficiency. In our experiments conducted on benchmark circuits ISCAS89, ITC99, and an open-source RISC-V CPU, we employed two methodologies. For commercial tool, we utilized a non-intrusive approach, while we adopted an intrusive method for open-source ATPG. Under the non-intrusive approach, our method achieved a maximum reduction of 34.69% in pattern count and a maximum 29.80% decrease in test cycles as evaluated by a leading commercial tool. Meanwhile, under the intrusive approach, our method attained a maximum 71.90% reduction in pattern count as evaluated by an open-source ATPG tool. Notably, fault coverage remained unchanged throughout the experiments. Furthermore, our approach demonstrates improved performance compared with existing methods.

Optimizing architectural multi-dimensional forms; a hybrid approach integrating approximate evolutionary search, clustering and local optimization

Parametric tools in architecture allow for the design of complex and multi-dimensional forms on building facades. Among these, geometric patterns can mitigate direct sunlight and enhance energy efficiency. However, conventional simulation methods and available optimization tools are prohibitively expensive for optimizing such complex forms. To address this challenge, this study proposes two innovative hybrid workflows that integrate parametric modeling, evolutionary approximate and accurate models (NSGA-III), clustering through k-means algorithm, and local search (Tabu search) technique. The outcomes obtained from employing these hybrid approaches demonstrate a substantial reduction in computational time and costs while simultaneously achieving optimal results. Additionally, an extensive comparison between the two proposed methodologies is presented encompassing factors such as performance metrics and computational expenses incurred during implementation. The findings derived from pattern optimization reveal several key insights: increasing pattern counts; dispersing them across the facade; minimizing the distance between the pattern wall from windows; adopting a south-facing orientation with positive vertical rotation – all contribute towards diminishing energy consumption (measured by Energy Use Intensity or EUI) within cold climates. However, material selection for these patterns primarily affects visual comfort levels.

Using Pattern Counts to Quantify the Difference Between a Pair of Three-Dimensional Realizations

AbstractWhen comparing different ways of modeling discrete three-dimensional realizations such as facies, it is useful to have a measure of difference (or similarity) in the geometry of these realizations. We propose a method for evaluating such difference by comparing pattern counts for a small template. Tests on synthetic datasets demonstrate that the proposed difference effectively differentiates between realizations of a Boolean model and those generated using multiple-point statistics with the Boolean realizations as training images. We also observed that multiple-point statistics realizations based on similar training images yield smaller differences to one another compared to those based on training images from dissimilar concepts. This suggests that the proposed difference is a useful tool for comparing discrete three-dimensional realizations.

Parallel computational ghost imaging with modulation patterns multiplexing and permutation inspired by compound eyes

Real-time computational ghost imaging (CGI) has received significant attention in recent years to overcome the trade-off between long acquisition time and high reconstructed image quality of CGI. Inspired by compound eyes, we propose a parallel computational ghost imaging with modulation patterns multiplexing and permutation to achieve a faster and high-resolution CGI. With modulation patterns multiplexing and permutation, several small overlapping fields-of-view can be obtained; meanwhile, the difficulty in alignment of illumination light field and multiple detectors can be well resolved. The method combining compound eyes with multi-detectors to capture light intensity can resolve the issue of a gap between detector units in the array detector. Parallel computation facilitates significantly reduced acquisition time, while maintaining reconstructed quality without compromising the sampling ratio. Experiments indicate that using m × m detectors reduce modulation pattern count, projector storage, and projection time to around 1/m2 of typical CGI methods, while increasing image resolution to m2 times. This work greatly promotes the practicability of parallel computational ghost imaging and provides optional solution for real-time computational ghost imaging.

Asymptotic normality of pattern counts in conjugacy classes

Asymptotic normality of pattern counts in conjugacy classes

Fingerprint patterns in relation to an altered neurodevelopment in patients with autism spectrum disorder

AbstractDermatoglyphic patterns are permanently established and matured before the 24th week of gestation. Their frequencies and localization might be a good indicator of developmental instability in individuals with an altered neurodevelopment and show potential as biomarkers of autism spectrum disorder (ASD). In this study, fingerprint pattern counts and fluctuating asymmetry in the distribution of patterns are compared between 67 boys diagnosed with ASD (aged 5.11 ± 2.51 years) and 83 control boys (aged 8.58 ± 3.14 years). Boys with ASD had a higher rate of discordance in their fingerprint patterns (p = .0026), showing more often bilateral differences in the occurrence of certain patterns. A chi‐square test revealed that the difference in pattern frequencies between boys with ASD and the control group is the most significant in frequencies of whorls, tented arches, and ulnar loops. Boys with ASD have significantly fewer ulnar loops, significantly more whorls, and tented arches in the right hand. The achieved results are in favor of the suggestion that prenatal influences, which play a role in the development of bilateral differences in fingerprint patterns up to the 24th week of gestation, may be a potential cause of an altered neurodevelopment in ASD individuals.

A Novel Test Pattern Optimization Method Using Recurrent Neural Network

Testing modern integrated circuit (IC) is challenging with introduction of System-on Chip (SOC). Enormous test pattern count is required to authenticate the IC which inflates power consumption. Henceforth, it is mandatory to incorporate power minimization techniques at circuit design phase. Optimizing test patterns is one such effective technique that curtails test power without altering circuit design. In this paper, a new test pattern reordering algorithm is proposed based on Recurrent Neural Network. Hopfield Neural Network (HNN) constitutes an optimized solution for solving traveling salesman problem (TSP). Since, test pattern reordering can be interpreted as TSP, optimized test pattern order is attained with HNN. Energy function of this algorithm falls into local minimum, so to eradicate this issue, the algorithm is modified. Test patterns are reordered with minimal hamming distance among consecutive test patterns. The proposed algorithm is implemented in ISCAS’89 Sequential Benchmark circuits. Experimental results prove that significant reduction in transition count is accomplished with proposed algorithm without compromising fault coverage.

A New Static Compaction of Deterministic Test Sets

Test set compaction is one of the key steps of the postproduction test known to bring down test pattern counts. This, in turn, allows one to reduce the corresponding test data volume, test application time, and hence the cost of testing. This article presents a method that strives to reduce the number of automatic test pattern generation (ATPG)-produced deterministic test patterns to deliver compact test sets. In principle, the new scheme works with a meaningful representation of test patterns by using external and internal necessary assignments (NAs) to determine small groups of potentially compatible faults. These faults are subsequently retargeted by the robust satisfiability (SAT)-based ATPG that produces a single test pattern for the entire group, thus making the resultant test set smaller in size. Experimental results obtained for 12 large industrial cores and stuck-at faults confirm superiority of the proposed scheme over the state-of-the-art test set compaction techniques and are reported herein.

Stein’s method for conditional central limit theorem

In the seventies, Charles Stein revolutionized the way of proving the central limit theorem by introducing a method that utilizes a characterization equation for Gaussian distribution. In the last 50 years, much research has been done to adapt and strengthen this method to a variety of different settings and other limiting distributions. However, it has not been yet extended to study conditional convergences. In this article we develop a novel approach, using Stein’s method for exchangeable pairs, to find a rate of convergence in the conditional central limit theorem of the form (Xn∣Yn=k), where (Xn,Yn) are asymptotically jointly Gaussian, and extend this result to a multivariate version. We apply our general result to several concrete examples, including pattern count in a random binary sequence and subgraph count in Erdős–Rényi random graph.

Evaluation of the Relative Performance of the Subflattenings Method for Phylogenetic Inference

The algebraic properties of flattenings and subflattenings provide direct methods for identifying edges in the true phylogeny—and by extension the complete tree—using pattern counts from a sequence alignment. The relatively small number of possible internal edges among a set of taxa (compared to the number of binary trees) makes these methods attractive; however, more could be done to evaluate their effectiveness for inferring phylogenetic trees. This is the case particularly for subflattenings, and the work we present here makes progress in this area. We introduce software for constructing and evaluating subflattenings for splits, utilising a number of methods to make computing subflattenings more tractable. We then present the results of simulations we have performed in order to compare the effectiveness of subflattenings to that of flattenings in terms of split score distributions, and susceptibility to possible biases. We find that subflattenings perform similarly to flattenings in terms of the distribution of split scores on the trees we examined, but may be less affected by bias arising from both split size/balance and long branch attraction. These insights are useful for developing effective algorithms to utilise these tools for the purpose of inferring phylogenetic trees.

Pattern-Functions, Statistics, and Shallow Permutations

We study relationships between permutation statistics and pattern-functions, counting the number of times particular patterns occur in a permutation. This allows us to write several familiar statistics as linear combinations of pattern counts, both in terms of a permutation and in terms of its image under the fundamental bijection. We use these enumerations to resolve the question of characterizing so-called "shallow" permutations, whose depth (equivalently, disarray/displacement) is minimal with respect to length and reflection length. We present this characterization in several ways, including vincular patterns, mesh patterns, and a new object that we call "arrow patterns." Furthermore, we specialize to characterizing and enumerating shallow involutions and shallow cycles, encountering the Motzkin and large Schröder numbers, respectively.

Efficient Test Compression Configuration Selection

Test costs for large industrial designs increase rapidly in recent years. On-chip test compression hardware has become a pragmatic technology to cut down the overall test costs by reducing the test data volume. Determining the input and output channel counts of test compression hardware that results in minimum test data volume is thus a critical issue. In this article, efficient methods to estimate test pattern counts for an extensive range of input/output counts are developed. These methods require only a small number of ATPG runs. The estimation results can then be utilized to determine the test data volume for each input/output configuration. The configuration with the estimated lowest test data volume thus can be determined. The pattern count results of each configuration for a design can also be used to determine the best suitable configuration when the design is to be embedded in an SoC system.

Anomaly-based Network Intrusion Detection using Ensemble Machine Learning Approach

In this study, an Intrusion Detection System (IDS) is designed based on Machine Learning classifiers, and its performance is evaluated for the set of attacks entailed in the UNSW- NB15 dataset. UNSW- NB15 dataset contains 2,540,226 realistic network data instances and 49 features. Most research uses a representative sample of this dataset with present training and testing subsets, which includes 257,673 records in total. The dataset was submitted to visual data analysis to discover poten-tial reasons or flaws which likely challenge Machine Learning classifiers. Pre-processing strategies are necessary before this data can be used for data-driven prototype development for IDS because of the class representation imbalance with pattern counts and feature overlap. The method used for pre-processing is implemented by min-max scaling in the normalization phase, followed by applying Elastic Net and Sequential Feature Selection (SFS) algorithms. This work employed ensemble methods using three base classifiers, namely Balanced Bagging, XGBoost, and RF-HDDT, augmented to address the imbalance issue. Parameters of Balanced Bagging and XGBoost are tuned for the imbalanced data, and the Hellinger distance metric supplements random Forest to address the limitations of the default distance metric. Two new algorithms are proposed to address the class overlap issue in the dataset and applied during training. These two algorithms are leveraged to help improve the performance on the testing dataset by affecting the final classification decision made by three base classifiers as part of the ensemble classifier, which employs a majority vote combiner. The performance evaluation of the proposed method for binary and multi-category classification was evaluated using standard metrics, including those generated from the confusion matrix, and compared to other studies using the same dataset. The proposed design outperforms those reported in the literature by a significant margin for binary and multi-category classification cases.

Efficient Bayesian estimation of permutation entropy with Dirichlet priors

Estimation of permutation entropy (PE) using Bayesian statistical methods is presented for systems where the ordinal pattern sampling follows an independent, multinomial distribution. The desired PE posterior distribution is demonstrated to closely approximate a standard Beta distribution whose hyperparameters can be computed directly from ordinal pattern counts. It is further shown that this Bayesian approach is a generalization of previously-published frequentist methods. Because Bayesian posterior distributions can be estimated for very short time series, this method enables PE analysis on data sets currently not compatible with existing methods due to their limited size. To demonstrate the power and flexibility of this technique, the PE of a semiconductor laser with optical feedback (SLWOF) is shown to be time-variant by visualizing how the PE posterior distribution varies over sequences of small (1000 point) partitions of the output time-series.

X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan

Hybrid test schemes comprising on-chip test compression and logic built-in self-test are expected to play a pivotal role in the design of new integrated circuits and delivering high quality tests. As architectural differences between these two paradigms are gradually blurring, and both schemes efficiently share test logic, they become more vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to unwrapped-for-test analog modules. Typically, X values degrade test results, and thus test response compaction schemes must be duly protected. This article presents maXpress-an X-tolerant tunable compactor deploying a new scan chain selection mechanism capable of completely masking X states, as required by many in-system or one-directional streaming test applications, within redefinable groups of scan chains and designated scan shift cycles. The proposed scheme is also supporting separate observation scan chains that, in contrast to conventional scan, capture faulty effects every shift cycle, while their content is gradually shifted into a compactor shared with the remaining chains. In addition to a new layout-friendly architecture, the article proposes algorithms to automate maXpress control settings based on scan chain selection rules deployed to suppress X states. Experimental results obtained for industrial designs show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on a resultant test coverage and test pattern counts.

Improving Quality of Manufacturing Test using Cell-Aware ATPG

The existing fault models like stuck-at, small delay defect, transition, and bridge fault models and their associated patterns are becoming less efficient, as the technology moves to increasingly smaller geometries. It is because traditional defect models target the faults only on IC gate boundaries, and the interconnects between the cells, but a significant population of defects (perhaps up to 50%) occurs within the cells or gates which are not specifically targeted by existing ATPG fault models. In this paper, a new ATPG methodology known as the Cell-aware test is implemented explicitly to target the defects caused by cell-internal open and short faults and improve the manufacturing test quality by minimizing the test escapes. This work explains how a Cell-Aware ATPG method performs a characterization on the GDSII data of library cell`s to produce a CAT library view (UDFM), test Pattern generation, and comparison between Traditional and Cell-Aware ATPG. The Cell-Aware ATPG is implemented using Tessent Testkompress, traditional ATPG is also developed to study and analyze both ATPG methodologies comparatively. Experiment results show a significant improvement in faults being targeted at an expense of an increase in pattern count and run-time. Obtained 71.28% and 59.38% test coverage for UDFM static and UDFM delay respectively. Achieved significant improvement in the test escapes with Cell-Aware Patterns when compared to traditional ATPG patterns.

SPARC: Time Series Transcriptomic Analysis of the Nucleus of the Solitary Tract During the Development of Hypertension

Essential hypertension affects millions of people and is known have a neurogenic component where regions in the brain and brainstem involved in the autonomic nervous system govern the regulation of blood pressure set point. While some work has been done to profile gene expression levels in the nucleus of the solitary tract (NTS) in males, to date no work has specifically looked at how gene expression changes in the NTS drive hypertension development in females. We have conducted a time series mRNA profiling analysis in female spontaneously hypertensive rats (SHR) in comparison to wild type Wistar Kyoto (WKY) allowing us to compare and contrast the results with previously obtained data in males. Rats were sacrificed over the development of and during chronic hypertension at 8, 12, 16, and 24 weeks of age and brainstems were removed and stored in OCT. Brainstems were sectioned on a cryostat and the NTS was extracted using a micropunch. Total RNA was extracted and samples were submitted for RNAseq. We used a data analysis approach focusing on comparative pattern counts (COMPACT) to exhaustively identify the dominant and subtle differential expression patterns (Kuttippurathu et al., BMC Genomics, 2016). Over 2000 genes that show both strain and age dependent differential expression were examined further to interrogate differences in expression patterns between SHR and WKY. Broad analysis reveals that genes involved in the adaptive immune response are differentially regulated in the SHR compared to WKY. Using COMPACT to examine specific patterns, we found that expression levels of many genes involved in transport and secretion of catecholamines do not change over time in WKY but are specifically downregulated in SHR before the onset of hypertension at 8 weeks of age. Interestingly, pathways such as arachidonic acid metabolism that have been implicated in hypertension development in males did not show significant differences between SHR and WKY in females. These results provide valuable insight into the regulatory networks governing hypertension development in females and allows us to compare and contrast this to what is known in males.Support or Funding InformationSupported by the NIH Common Fund SPARC Program award OT2 OD023848 and NIH NHLBI Multiscale Modeling award U01 HL133360.

Individuals with nonsyndromic orofacial clefts have increased asymmetry of fingerprint patterns.

Dermatoglyphic patterns on the fingers often differ in syndromes and other conditions with a developmental component, compared to the general population. Previous literature on the relationship between orofacial clefts–the most common craniofacial birth defect in humans–and dermatoglyphics is inconsistent, with some studies reporting altered pattern frequencies and/or increased asymmetry and others failing to find differences. To investigate dermatoglyphics in orofacial clefting, we obtained dermatoglyphic patterns in a large multiethnic cohort of orofacial cleft cases (N = 367), their unaffected family members (N = 836), and controls (N = 299). We categorized fingerprint pattern types from males and females who participated at five sites of the Pittsburgh Orofacial Cleft study (Hungary, United States of America (Pennsylvania, Texas), Spain, and Argentina). We also calculated a pattern dissimilarity score for each individual as a measure of left-right asymmetry. We tested for group differences in the number of arches, ulnar and radial loops, and whorls on each individual’s hands, and in the pattern dissimilarity scores using ANOVA. After taking sex and site differences into account, we did not find any significant pattern count differences between cleft and non-cleft individuals. Notably, we did observe increased pattern dissimilarity in individuals with clefts, compared to both their unaffected relatives and controls. Increased dermatoglyphic pattern dissimilarity in individuals with nonsyndromic orofacial clefts may reflect a generalized developmental instability.

Reduction of Test Data with Hybrid Test Points

ATPG vectors for a combinational circuit exhibit correlations among the bits of a test vector. We propose a BIST circuit design methodology using spectral methods which utilizes the correlation information. This circuit serves dual purposes. It generates BIST vectors that are similar to the ATPG vectors with higher test coverage as compared to random and weighted random vectors. The same circuit can also function as a test data de-compressor for compressed ATPG vectors applied from an external tester. Logic built-in self-test (LBIST) is now increasingly used with on-chip test compression as a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs targeted for safety-critical systems. Test points, common in LBIST-ready designs, can help to reduce test time and the overall silicon overhead so that one can get desired test coverage with the minimal number of patterns. Typically, LBIST test points are dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG pattern counts cannot guarantee desired random testability. We present a hybrid test point technology designed to reduce deterministic pattern counts and to improve fault detection likelihood by means of the same minimal set of test points. The hybrid test points are subsequently deployed in a scan-based LBIST scheme addressing stringent test requirements of certain application domains such as the automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage. The new scheme is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per cycle-driven hybrid observation test points that capture faulty effects every shift cycle into dedicated scan chains. We also exhibit test data compression capabilities of the proposed BIST architecture. This architecture provides a maximum test data compression exceeding and a proportional test time reduction for serial interface reseeding.