Path Delay Faults Research Articles

Weak and Strong Non-Robust Tests for Functionally Possible Path Delay Faults

Weak and Strong Non-Robust Tests for Functionally Possible Path Delay Faults

Functionally Possible Path Delay Faults With High Functional Switching Activity

Functionally Possible Path Delay Faults With High Functional Switching Activity

Self-Test Library Generation for In-Field Test of Path Delay Faults

New semiconductor technologies for advanced applications are more prone to defects and imperfections related, among several different causes, to the manufacturing process, aging and cross-talks. These phenomena negatively affect the circuit’s timing and can be effectively modeled by means of the path delay fault (PDF) model. While path delay testing is currently supported by commercial Automatic Test Pattern Generation tools for scan designs, functional testing covering PDFs is not widely adopted, mainly because of the high cost for test generation. On the other side, functional test is already widely adopted for in-field test of stuck-at faults, which is often performed resorting to the execution of suitable test programs (Self Test Libraries, or STLs). This approach is attractive, since it can be performed at-speed with limited time constraints and high flexibility, making it a suitable in-field test solutions. Previous work assessed the feasibility and validity of functional approaches based on test programs targeting PDFs. In this work, we present the first systematic method for the development of very high fault coverage test programs for PDFs, which largely outperform test programs written for other fault models. Moreover, the proposed method allows the identification of functionally untestable faults. The effectiveness of the proposed approach was proven on an open-source RISC-V processor core, where 100% coverage of the functionally testable longest paths was achieved, compared with an initial coverage of 0.52% achieved with test programs targeting stuck-at faults. Results demonstrate that shorter paths are also effectively covered.

Path Unselection for Path Delay Fault Test Generation

Path selection procedures identify path delay faults whose tests detect small delay defects. Path selection criteria are positive in the sense that they point to paths that should be selected, e.g., the longest paths. However, the longest paths are in many cases untestable, and the number of paths can be large when the longest testable paths are considered. For this scenario, it is advantageous to have a negative path selection procedure that excludes paths from consideration as targets for test generation. This provides the flexibility to identify detectable path delay faults among a reduced number of path delay faults. Such a procedure is developed in this article and referred to as a path unselection procedure. The procedure performs linear-time traversals of the circuit to unselect fan-out branches, and thus exclude from consideration paths that are shorter than the ones it keeps. It also uses available information about detectable and undetectable path delay faults to unselect fan-out branches or avoid unselecting them. To demonstrate its use, the procedure is applied to benchmark circuits as part of an iterative test generation procedure whose goal is to target manageable numbers of the longest path delay faults.

Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults

Undetectable faults result from logic redundancies and constraints on applicable tests. The presence of an undetected (undetectable or aborted) fault implies that a test, which would have covered its site, is missing from the test set. When undetected transition faults form a path, the missing tests imply that (small) delay defects along the path may not be detected even if they are detectable. The goal of this article is to provide additional coverage for paths of undetected transition faults by using two-cycle gate-exhaustive faults for subcircuits (gates) that wrap the paths. The use of gate-exhaustive faults alleviates the need to model delay defects along the paths, or use path delay faults that may also be undetectable. The article defines the target paths, and gates that wrap them, for which two-cycle gate-exhaustive faults can be defined. Experimental results for benchmark circuits demonstrate the discussion.

GEPDFs: Path Delay Faults Based on Two-Cycle Gate-Exhaustive Faults

Path delay faults model small delay defects that affect the operation of the circuit when they accumulate along a path. For lines on a path, the propagation conditions can be related to those of transition faults. Two-cycle defect-aware, cell-aware and gate-exhaustive faults model delay defects with more complex activation conditions than transition faults. This article observes that detecting gate-exhaustive faults along a path results in the detection of small delay defects with more complex activation conditions than transition faults. Such path delay faults are referred to as gate-exhaustive path delay faults. This article defines gate-exhaustive path delay faults and describes a path selection procedure to support test generation. The experimental results for benchmark circuits demonstrate the possibility of detecting gate-exhaustive path delay faults.

Constructing a Sequence Detecting Robustly Testable Path Delay Faults in Sequential Circuits

Constructing a Sequence Detecting Robustly Testable Path Delay Faults in Sequential Circuits

Testing and Diagnosis of Delay Faults in Finfet VLSI Circuits using Non-Incremental Genetic Algorithm

FinFet transistors are used in major semiconductor organizations which play a significant role in the development of the silicon industries. Due to few embedded memories and other circuit issues the transistors have specific faults in manufacturing, designing of the circuit etc. This paper presents an advanced test algorithm to diagnose those faults. The circuit with different gates is designed to identify the places having faults. In addition, algorithms such as non-incremental algorithms is used to find critical path, path delay and PDF of Critical path delay and Genetic Algorithm for optimisation of Critical path delay for sensitive test vector and no of iterations. The transfer characteristics curve is plotted along with the delay curve which helps in finding out the simulation parameters such as noise margin, propagation delay. The results in the methodology calculate the probability density function of the critical path by estimating mean, standard deviation and variance. The advantages of the integration of the two algorithms in this paper help in analyzing the specific faults in the circuits and the error correction of the broken link in the path analysis and has enhanced performance. Furthermore, more complicated circuits are analyzed for fault detection with different approach. In this paper the research work on testing, diagnosis, estimation of Critical path and PDF of Critical path delay faults for FinFET based Combinational Circuits for 20nm and 32 nm Technologies are presented for the first time using latest Non Incremental Genetic algorithm.

Extra Clocking of LFSR Seeds for Improved Path Delay Fault Coverage

Test data compression is based on storage of compressed tests and use of on-chip decompression logic for test application. Further reductions in the input test data volume are achieved by methods that apply several different tests based on every compressed test. This article makes the new observation that by keeping the same number of compressed tests and applying several different tests based on every compressed test, it is possible to improve the quality of the test set applied to the circuit. This article studies such an approach for path delay faults (PDFs) using a linear-feedback shift register (LFSR) as the decompression logic. Because of the nature of PDFs, targeting an extended subset of PDFs increases the confidence that important PDFs are detected. However, the benefit of detecting additional faults may not justify an increase in the number of stored tests. The approach suggested in this article is used for detecting an extended subset of target PDFs using the same set of LFSR seeds. Extra clocking of the LFSR is used for obtaining scan-in states for several new two-cycle tests based on the same seed. Experimental results for benchmark circuits demonstrate the effectiveness of this approach.

Applying ROBDDs for Logical Circuit Delay Testing

Increasing frequency of functioning and decreasing transistor sizes in high performance logical circuits may result in illegal capacities, inductivities, resistances, and so on that generate decreasing estimated circuit frequency. These defects cannot be detected by physical methods. The main way of solving the problem is based on delay testing of logical circuits within the path delay fault (PDF) model. In this paper, facilities of enhancing PDF test sequence quality based on application of Reduced Ordered Binary Decision Diagrams (ROBDDs) that compactly represent all test pairs of neighbor test patterns for the circuit path are studied. Test patterns (Boolean vectors) are neighbor if they differ by only one component. It is established that using of these ROBDDs cut the lengths of test sequences by more than 1/3 in comparison with traditional scan test sequences simultaneously enhancing test sequence quality. In particular, we derive test sequences for robust testable PDFs of sequential circuits decreasing their power consumption and peak power values.

Artificial neural network model for arrival time computation in gate level circuits

ABSTRACT Advances in the VLSI process technology lead to variations in the process parameters. These process variations severely affect the delay computation of a digital circuit. Under such variations, the various delays, i.e. net delay, gate delay, etc., are no longer deterministic. They are random in nature and are assumed to be probabilistic. They keep changing, based on factors such as process, voltage, temperature, and a few others. This calls for efficient tools to perform timing checks on a design. This work presents a technique to compute the arrival time of a digital circuit. The arrival time (AT) is computed using two different timing engines, namely, static timing analysis (STA) and statistical static timing analysis (SSTA). This work also aims to eliminate number of false paths. It uses a fast and efficient filtering method by utilizing ATPG stuck-at faults and path delay faults. ISCAS-89 benchmark circuits are used for implementation. The results obtained using the probabilistic approach are more accurate than the conventional STA. It has been verified with an Artificial Neural Network (ANN) model. The arrival time calculated using SSTA shows 7% improvement over that of STA. The absolute error is reduced twofold in the case of the ANN model for SSTA.

Worst Case Test Vectors for Sequential Circuits in Flash-Based FPGAs Exposed to Total Dose

We introduce a methodology for identifying worst case test vectors (WCTVs) for delay failures induced by total dose in sequential circuits implemented in flash-based field-programmable gate arrays (FPGAs) using design-for-testability (DFT) techniques and path delay faults using commercially available DFT and automatic test pattern generation (ATPG) tools. We verified this methodology experimentally using Microsemi ProASiC3 FPGAs and Cobalt 60 facility. The experimental results show a significant impact on the total dose failure level when using WCTVs in total-dose testing of FPGA devices.

LFSR-Based Test Generation for Path Delay Faults

Two challenges are combined when compressed tests are computed for path delay faults: 1) path delay faults that are important to detect are associated with long paths, and many of these faults are undetectable and 2) it may not be possible to compress a given test for a path delay fault. This paper addresses these challenges in the context of test data compression methods that are based on a linear-feedback shift-register (LFSR). The basic approach that this paper uses modifies initially random seeds for the LFSR into seeds that produce tests for detecting target faults. This approach can find seeds even if the available tests cannot be compressed into seeds. In addition, the procedure described in this paper also selects detectable path delay faults to address the presence of undetectable path delay faults in the set of target faults. For this purpose it uses a metric that measures the similarity between target and detected path delay faults, and attempts to compute seeds that increase the values of this metric. Experimental results are presented to demonstrate the ability of the procedure to detect path delay faults in benchmark circuits.

Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering

The efficient representation and manipulation of a large number of paths in a Directed Acyclic Graph (DAG) requires the usage of special data structures that may become of exponential size with respect to the size of the graph. Several methodologies targeting Electronic Design Automation problems such as timing analysis, physical design, verification and testing involve path representation and necessary manipulation. Previous works proposed an encoding using Zero-suppressed Binary Decision Diagrams (ZDDs), which has been shown experimentally to cope well when representing structural or logical paths in VLSI circuits. However, it is well known that the ordering of the variables in a ZDD highly affects its size and, therefore, the efficiency of the methodologies utilizing these data structures. In this work, we show that using a reverse topological order for the ZDD variables bounds the number of nodes in the ZDD representing structural paths to the number of edges in the DAG considered, hence, making the ZDD size linear to the DAG’s size. This result, supported here both theoretically and experimentally, is very important as it can render methodologies with questionable scalability applicable to larger industrial designs. We demonstrate the applicability of the proposed variable ordering in one such methodology which utilizes ZDDs to grade the Path Delay Fault coverage of a given test set.

Finding Test Pairs for PDFs in Logic Circuits Based on Using Operations on ROBDDs

A method of finding all test pairs for robust testable Path Delay Faults (PDFs) is suggested. In foreign literature, the authors find only one or several subsets of the test pairs. In this paper, the test pairs are formed from sequential sets and represented compactly by the Reduced Ordered Binary Decision Diagram (ROBDD). In this paper, the test pairs are formed from adjacent test patterns. All such test pairs are compactly represented by the ROBDD. Having got all test pairs for a path, we may derive a test sequence detecting the robust PDFs of the path in sequential circuits without using Scan techniques. In addition, having got the above-mentioned ROBDDs for a set of paths, we may find compact test sets for the Scan techniques oriented to decreased power consumption during testing. Finding all test pairs is reduced to deriving a Boolean difference for the path considered. The Boolean difference is obtained by applying operations on ROBDDs involved from the combinational part fragments of a sequential circuit. The Boolean difference is also represented by the ROBDD.

A New Hybrid Test Pattern Generator for Stuck-at –Fault and Path Delay Fault in Scan Based Bist

Testing for delay and stuck-at faults needs a pattern of two checks and test sets square measure sometimes more. Built self-test (BIST) schemes square measure enticing for such comprehensive testing. The BIST check pattern generators (TPGs) for such testing ought to be designed accustomed guarantee high pattern-pair coverage. Within the planned work, necessary and decent conditions to complete/ supreme pattern-pair coverage for consecutive circuit has been derived. A replacement check data-compression theme that's a hybrid approach between external testing and inbuilt self-test (BIST) is analyzed. The planned approach is predicated on weighted pseudorandom testing and uses a unique approach for pressing and storing the load sets. Most existing check generation tools square measure either inefficient in mechanically characteristic the longest checkable methods thanks to the high process complexness or don't support at speed test mistreatment existing sensible design-for-testability structures, like scan style. During this work a check generation methodology for scan-based synchronous consecutive circuits is conferred, below 2 at-speed check methods employed in trade. The approach provides a balanced trade-off between accuracy and potency. Experimental results show promising runtime and fault coverage enhancements over existing ways.

Проектирование отказоустойчивых последовательностных схем для константных неисправностей и неисправностей задержек путей

Проектирование отказоустойчивых последовательностных схем для константных неисправностей и неисправностей задержек путей

Selecting Replacements for Undetectable Path Delay Faults

Path selection procedures select the path delay faults that are the most important to detect as targets for test generation. When the criteria for path selection can be evaluated locally at the gate level, it is possible to consider the detectability of path delay faults during the path selection process. This flexibility does not exist if path selection is performed based on more complex conditions, or by a tool that cannot be modified to take into consideration the detectability conditions for path delay faults. For this scenario, this brief describes a procedure that accepts a set $P$ of path delay faults, and replaces every undetectable path delay fault $p \in P$ with a detectable path delay fault $r$ that is as similar to $p$ as possible. This brief defines similarity as the length of the longest contiguous subpath that is common to $p$ and $r$ . Experimental results demonstrate the extent to which similarity can be maintained when path delay faults that are associated with the longest paths are considered for benchmark circuits.

A Hybrid Delay Design-for-Testability for Nonseparable RTL Controller-Data Path Circuits

Path delay testing has become crucial nowadays due to the advancement in process technology. Only enhanced scan (ES) among the scan approaches provides a solution to test the path delay fault (PDF) with large area overhead and the long test application time. This paper proposes a hybrid DFT method for nonseparable controller-data path RTL circuits. A snooping system is introduced which reduces the test application time. It performs the PDF testing between the controller and data path, and for the not-Clear control lines in the data path. The proposed method shared primary inputs and outputs to overcome the extra pin. However, the area overhead for the proposed approach is slightly large for the circuit with a small bit-width data path, which reduced drastically by the increase in the bit-width. The proposed approach supports the at-speed testing and is based on the PDF model. The experimental results showed that the proposed approach reduces the area overhead and drastically reduces the test application time in comparison with the enhanced scan (ES) and hierarchical two-pattern testability (HTPT) approach. Moreover, the technique can achieve a fault coverage identical to that achieved by the ES technique.

Path delay test generation at functional level

The path delay tests, which are used to test the maximum speed of the circuit, usually are generated at the structural level. The authors suggested the path delay fault test generation approach for non-scan sequential circuits at the functional level. The circuit is considered as a black box model having the primary inputs, primary outputs and state bits. The state bits of the model are transformed into pseudo-primary inputs and pseudo-primary outputs. The circuit is represented as the iterative logic array model, consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles, which has to be chosen before test generation. To assess the length of the path at the functional level they suggested a new criterion. The length of the path is assessed by the number of the sensitive paths connected to the particular input and to the particular output. The experimental results are provided for the ITC'99 benchmark circuits. The generated functional test for path delay faults can be used either on its own if there is no structural test or it can be used as a supplement to the structural test.