Finding Test Pairs for PDFs in Logic Circuits Based on Using Operations on ROBDDs

Abstract

A method of finding all test pairs for robust testable Path Delay Faults (PDFs) is suggested. In foreign literature, the authors find only one or several subsets of the test pairs. In this paper, the test pairs are formed from sequential sets and represented compactly by the Reduced Ordered Binary Decision Diagram (ROBDD). In this paper, the test pairs are formed from adjacent test patterns. All such test pairs are compactly represented by the ROBDD. Having got all test pairs for a path, we may derive a test sequence detecting the robust PDFs of the path in sequential circuits without using Scan techniques. In addition, having got the above-mentioned ROBDDs for a set of paths, we may find compact test sets for the Scan techniques oriented to decreased power consumption during testing. Finding all test pairs is reduced to deriving a Boolean difference for the path considered. The Boolean difference is obtained by applying operations on ROBDDs involved from the combinational part fragments of a sequential circuit. The Boolean difference is also represented by the ROBDD.