Delay testable logical circuit design

Increasing frequency of functioning and decreasing transistor sizes in high performance logical circuits may result in illegal capacities, inductivities, resistances, and so on that generate decreasing estimated circuit frequency. These defects cannot be detected by physical methods. The main way of solving the problem is based on delay testing of logical circuits within the path delay fault (PDF) model. In this paper, facilities of enhancing PDF test sequence quality based on application of Reduced Ordered Binary Decision Diagrams (ROBDDs) that compactly represent all test pairs of neighbor test patterns for the circuit path are studied. Test patterns (Boolean vectors) are neighbor if they differ by only one component. It is established that using of these ROBDDs cut the lengths of test sequences by more than 1/3 in comparison with traditional scan test sequences simultaneously enhancing test sequence quality. In particular, we derive test sequences for robust testable PDFs of sequential circuits decreasing their power consumption and peak power values.

A method of finding all test pairs for robust testable Path Delay Faults (PDFs) is suggested. In foreign literature, the authors find only one or several subsets of the test pairs. In this paper, the test pairs are formed from sequential sets and represented compactly by the Reduced Ordered Binary Decision Diagram (ROBDD). In this paper, the test pairs are formed from adjacent test patterns. All such test pairs are compactly represented by the ROBDD. Having got all test pairs for a path, we may derive a test sequence detecting the robust PDFs of the path in sequential circuits without using Scan techniques. In addition, having got the above-mentioned ROBDDs for a set of paths, we may find compact test sets for the Scan techniques oriented to decreased power consumption during testing. Finding all test pairs is reduced to deriving a Boolean difference for the path considered. The Boolean difference is obtained by applying operations on ROBDDs involved from the combinational part fragments of a sequential circuit. The Boolean difference is also represented by the ROBDD.

We present methods to generate a Binary Decision Diagram (BDD) with minimum expected path length. A BDD is a generic data structure which is widely used in several fields. One important application is the representation of Boolean functions. A BDD representation enables us to evaluate a Boolean function: Simply traverse the BDD from the root node to the terminal node and retrieve the value in the terminal node. For a BDD with minimum expected path length will be also minimized the evaluation time for the corresponding Boolean function. Three efficient algorithms for constructing BDDs with minimum expected path length are proposed.

We present methods to generate a Binary Decision Diagram (BDD) with minimum expected path length. A BDD is a generic data structure which is widely used in several fields. One important application is the representation of Boolean functions. A BDD representation enables us to evaluate a Boolean function: Simply traverse the BDD from the root node to the terminal node and retrieve the value in the terminal node. For a BDD with minimum expected path length will be also minimized the evaluation time for the corresponding Boolean function. Three efficient algorithms for constructing BDDs with minimum expected path length are proposed.

Traditional scan based transition delay fault tests can potentially miss variability induced delay faults on long interconnects. On the other hand, an ATPG may not be successful in deriving test patterns for all paths. The paper proposes a BDD based synthesis method where all the paths are testable under the path delay fault model without addition of extra inputs. Each ROBDD (Reduced-Ordered-Binary Decision Diagram) node is covered by an Invert-AND-OR sub-circuit. The paper proves that the synthesized circuit is fully testable for path delay faults, either by robust tests or validatable non-robust tests.

Symbolic representation of path delay-faults can achieve high degree of compaction relative to more explicit forms. Large numbers of path delay-faults exist in common digital circuits. Ordered binary decision diagrams (OBDDs) provide a convenient data structure to represent these large number of path delay faults during the process of fault simulation computing the path delay-fault coverage for a given delay test-set. We present some experimental results from applying these algorithms to common benchmark examples that demonstrate the viability of our approach.

On the size of binary decision diagrams representing Boolean functions

Chain reduction enables reduced ordered binary decision diagrams (BDDs) and zero-suppressed binary decision diagrams (ZDDs) to each take advantage of the others' ability to symbolically represent Boolean functions in compact form. For any Boolean function, its chain-reduced ZDD (CZDD) representation will be no larger than its ZDD representation, and at most twice the size of its BDD representation. The chain-reduced BDD (CBDD) of a function will be no larger than its BDD representation, and at most three times the size of its CZDD representation. Extensions to the standard algorithms for operating on BDDs and ZDDs enable them to operate on the chain-reduced versions. Experimental evaluations on representative benchmarks for encoding word lists, solving combinatorial problems, and operating on digital circuits indicate that chain reduction can provide significant benefits in terms of both memory and execution time.

Chain reduction enables reduced ordered binary decision diagrams (BDDs) and zero-suppressed binary decision diagrams (ZDDs) to each take advantage of the others’ ability to symbolically represent Boolean functions in compact form. For any Boolean function, its chain-reduced ZDD (CZDD) representation will be no larger than its ZDD representation, and at most twice the size of its BDD representation. The chain-reduced BDD (CBDD) of a function will be no larger than its BDD representation, and at most three times the size of its CZDD representation. Extensions to the standard algorithms for operating on BDDs and ZDDs enable them to operate on the chain-reduced versions. Experimental evaluations on representative benchmarks for encoding word lists, solving combinatorial problems, and operating on digital circuits indicate that chain reduction can provide significant benefits in terms of both memory and execution time.

Decision diagrams (DDs) are data structures commonly used for representation of discrete functions with large number of variables. Binary DDs (BDDs) are used for representation and manipulation with Boolean functions. Complexity of a BDD is usually measured by its size, that is defined as the number of non-terminal nodes in the BDD. Minimization of the sizes of DDs is a problem greatly considered in literature and many related algorithms (exact and heuristic) have been proposed. However, there are many functions for which BDDs when minimized are still large and can have even an exponential size in the number of variables. An approach to derive compact decision diagram representations for such functions is transformation of BDDs into Multi-valued DDs (MDDs) and Heterogeneous MDDs (HMDDs). Complexity of MDDs and HMDDs is measured by the cost which is a generalization of the notion of the size by taking into account complexity of nodes in MDDs and HMDDs. This paper presents a method for transformation of BDD into HMDD with minimal cost. The proposed method reduces the time for determination of the type of nodes in HMDDs by introducing a matrix expressing dependency (interconnections) among nodes at different levels. Comparing to other methods for conversion of BDDs into HMDDs, the method reduces the number of traverses of a BDD necessary for collecting enough information to construct an equivalent HMDD. For an experimental verification of its efficiency, the method is applied to construction of HMDDs for some benchmark functions and their arithmetic and Walsh spectra.

Boolean functions are often represented by ordered binary decision diagrams (OBDDs) introduced by Bryant [2]. Liaw and Lin [7] have proved upper and lower bounds on the minimal OBDD size of almost all Boolean functions. Now tight bounds are proved for the minimal OBDD size for arbitrary or optimal variable orderings and for the minimal read-once branching program size of almost all functions. Almost all Boolean functions have a sensitivity of almost 1, i. e. the minimal OBDD size for an optimal variable ordering differs from the minimal OBDD size for a worst variable ordering by a factor of at most 1 + ɛ(n) where ɛ(n) converges exponentially fast to 0.

The use of Binary Decision Diagrams (BDDs) has proliferated in numerous fields. When a system criterion is formulated in form of a Boolean function, its BDD is constructed. Each node in the BDD is further mapped into another form to be exploited in the system analysis. However, the cost of the resultant mapping form is directly related to the BDD size which can be effectively reduced through applying proper variable reordering followed by applying reduction rules that preserve the fidelity of the BDD in correctly representing the input Boolean function. Although several algorithms have been proposed in the literature to find the optimal order of variables in the BDD, the scalability of such algorithms is a serious barrier when it comes to complex systems with exponential explosion in the possible number of orders in the search space. Furthermore, solely exploring the search space in BDD reordering is not sufficient since better permutations might be obtained with slight tuning of the candidate solutions. Thus, a sufficient degree of equilibrium between exploration and exploitation should be preserved during the evolution of the reordering algorithm. In this paper, we propose a BDD optimizer driven by either Genetic Algorithm (GA) or swarm engines. The proposed GA-based BDD reordering optimizer iteratively processes an essentially large population with a randomized mixing of low destructive crossover/mutation operators. The proposed swarm-based optimizer, on the other hand, maps a vector of real numbers into a permutation to further construct its companion BDD. The generation of the next vector is guided by recent parameter and parameter-less swarm algorithms that are armed with effective mechanisms to simultaneously conduct exploration and exploitation. Experimental results show that our proposed optimizer effectively reduces the resultant BDD size for input Boolean functions with almost linear computational complexity. Furthermore, it has been found that exploiting recent swarm optimizers with spiral movement in BDD reordering problem can outperform GA for large scale Boolean functions. Finally, as a real-world application, our proposed algorithm is applied to reversible logic synthesis to show the achieved reduction in the Quantum Cost (QC) associated with BDD-based synthesis.

This paper discusses the complexity of reduced ordered binary decision diagrams (ROBDDs) for Boolean functions with XOR/XNOR min-terms. Knowing the number of variables and the number of product terms of Boolean function containing only XOR/XNOR min-terms, one can predict the number of nodes in its ROBDD representation without building the binary decision diagram (BDD). A mathematical model for this prediction has been developed. This model can be used to find the maximum number of nodes for a given number of variables. Theoretical and experimental results are reported to underline the efficiency of this approach. The experimental results show that even though the XOR/XNOR min-terms cannot be simplified using Boolean laws or any other simplification method leading to a better min-term representation, the ROBDD will perform the simplification using the ROBDD reduction rules. The required memory is analysed for different methods of representation, and this analysis showed that ROBDDs are memory efficient structures to store and represent large numbers of XOR/XNOR min-terms in Boolean functions.

A novel approach that employs ordered binary decision diagrams (OBDDs) is contributed to factorize multi-level logic functions by requiring as few literals as possible. A logic function with PLA format is represented as an OBDD form first. A heuristic decision method of variable ordering, called theorder lookahead method, is derived for the construction of OBDDs. This method is based on the constant cofactor and the number of erasable logic terms for each input variable. The total execution time of the OBDD construction by the above ordering decisions is very fast for some MCNC benchmarks. With the above OBDDs, we introduce a simple yet effective graph manipulation, calledEXT, to obtain a minimal number of literals in the Boolean function. This greedyEXT algorithm consists mainly of two phases. The first phase, calledgraph analysis, identifies the similarities between nodes on the same level in the OBDD. The second phase, calledtree analysis, utilizes the above features to extract the common parts of the nodes. TheEXT procedure runs from the bottom level up to the top level of the OBDD. The computational complexity depends on the number of nodes in the OBDD. The results of simulations show thatEXT has a very fast CPU execution time and a competitive literal ratio with other methods for some MCNC benchmarks.EXT will produce the smallest literal number, especially for structured or symmetric circuits.

Min delay violations are traditionally not modeled as possible faults as a result of manufacturing defects. Usually, path delay faults are implicitly assumed to be paths' max delay violations. This, in turn, is based on the assumption that min delay violations are designed out. Most previous manufacturing defect/fault analysis works have not considered their effect on clock circuits. More recently, as burn-in becomes ineffective and process variations become more of an issue, latent defects, device degradation or wear out in the field would potentially also cripple the clock distribution network. Consequently, we should start considering also path (min) delay faults when designing on-line testable circuits, similar to what we currently do for path (max) delay faults. The challenges that this poses to the existing on-line testing strategies are discussed. Examples showing the possible incorrect behavior of a self-checking circuit as a result of this kind of faults are given. New on-line testing strategies should consequently be devised to deal with these faults.