Passive Interconnect Research Articles

A Port‐Hamiltonian Approach to Visual Servo Control of a Pick and Place System

AbstractIn this paper, we take a port‐Hamiltonian approach to address the problem of image‐based visual servo control of a pick and place system. Through a coordinate transformation and a passive interconnection between mechanical system and camera dynamics we realize a closed‐loop system that is port‐Hamiltonian. The resulting control strategy depends only on the camera states and it can be proven that the closed‐loop system is also asymptotically stable. Furthermore, a region of attraction is defined for which asymptotic stability holds.

Scalable Optical Interconnect Architecture Using AWGR-Based TONAK LION Switch With Limited Number of Wavelengths

This paper analyzes the scalability in arrayed waveguide grating router (AWGR)-based interconnect architectures and demonstrates active AWGR-based switching using a distributed control plane. First, the paper analyses an all-to-all single AWGR passive interconnection with N nodes and proposes a new architecture that overcomes the scalability limitation given by wavelength registration and crosstalk, by introducing multiples of smaller AWGRs (W × W) operating on a fewer number of wavelengths . Second, this paper demonstrates active AWGR switching with a distributed control plane, to be used when the size of the interconnection network makes the all-to-all approach using passive AWGRs impractical. In particular, an active AWGR-based TONAK switch is introduced. TONAK combines an all-optical NACK technique, which removes the need for electrical buffers at the switch input/output ports, and a TOKEN technique, which enables a distributed all-optical arbiter to handle packet contention. The experimental validation and performance study of the AWGR-based TONAK switch is presented, demonstrating the feasibility of the TONAK solution and the high throughput and low average packet latency for an up to 75% offered load.

Establishment of Dynamic Lightpaths in Filterless Optical Networks

In this paper, we study the performance of dynamic routing and wavelength assignment (RWA) in filterless optical networks. These types of broadcast and select networks benefit from breakthroughs in advanced transmission technologies for replacing optical filters and active photonic switching devices, such as wavelength selective switches, with passive optical interconnections between nodes, creating passive optical light trees. We introduce an RWA scheme for establishing passive optical lightpaths in a filterless context and managing unfiltered channels at intermediate egress nodes, which, by propagating downstream of the terminating nodes, participate in wavelength usage and increase the risk of wavelength exhaustion. Simulation results are presented for six network topologies, along with the performance evaluation of active photonic and filterless optical network solutions with static and dynamic RWA schemes. We show that the performance of the proposed scheme depends on the average degree of node connectivity.

DOCSIS provisioning of ethernet PON (DPoE)

The tremendous demand on carriers for bandwidth in the access network, as well as demands on carriers to manage that bandwidth, continues to drive the technical evolution of access networks. As one approach to satisfy these demands, DOCSIS® Provisioning of EPON (DPoE), combines two access technologies: Ethernet passive optical network (EPON) and Data Over Cable Service Interface Specification ( DOCSIS). DOCSIS makes possible mature service provisioning mechanisms based on centralized back-office automation. EPON provides a transport layer between the DPoE System and a number of connected DPoE optical network units (D-ONUs) for distances of 20 km and more. The completely passive interconnection structure of EPON also reduces capital expenditures (CAPEX) and operational expenditures (OPEX) by requiring no electrical power outside of the hub.

Passive Circuit Technologies for mm-Wave Wireless Systems on Silicon

The performance characteristics of transmission lines, silicon integrated waveguides, tunable LC resonators and passive combiners/splitters and baluns are described in this paper. It is shown that Q-factor for an on-chip LC tank peaks between 20 and 40 GHz in a 65 nm RF-CMOS technology; well below the bands proposed for many mm-wave applications. Simulations also predict that the Q-factor of differential CPW transmission lines on-chip can exceed 20 at 60 GHz in RF-CMOS when a floating shield is applied, outperforming unshielded variants employing more advanced metal stacks. A PA circuit demonstrator for advanced on-chip passive power combiners, splitters and baluns realizes peak-PAE of 18% and Psat better than 20 dBm into a 50 Ω load at 62 GHz. An outlook to the enablement of digitally intensive mm-wave ICs and low-loss passive interconnections (0.15 dB/mm measured loss at 100 GHz) concludes the paper.

PEEC method: circuit models for electromagnetic field problems

Purpose – The paper aims to give the reader a consolidated state of art in the full‐wave modeling of passive interconnection systems using equivalent circuits and presents several advantageous techniques developed by the authors.Design/methodology/approach – The paper presents the theory of generalized partial element equivalent circuit (PEEC) modeling in the frequency domain (FD) and time domain (TD) developed by the authors. The widely spread simplified approaches are derived from this general formulation and the most important issues (e.g. stability in the TD) are considered. The theoretical part is completed by a simulation example, which shows the efficiency of studied methods.Findings – Novel approaches for co‐simulation of passive interconnections in their circuit environment.Practical implications – The PEEC method is widely used in the practice of computational electromagnetics, e.g. by the authors in the practical electromagnetic compatibility simulation.Originality/value – The paper is based on...

On equivalence between internal and external model‐based repetitive learning controllers for nonlinear passive systems

AbstractIn this paper a new class of globally stable finite dimensional repetitive controllers for nonlinear passive systems is proposed. The proposed internal model‐based repetitive controller has a structure in the form of a parallel connection of linear oscillators and one integrator. The passive interconnection of the controller and the nonlinear passive systems provides the same stability conditions as the controller with the exact feed‐forward compensation of system dynamics. The existing internal and external model‐based repetitive controllers can be derived as the special cases of the proposed controller.Copyright © 2010 John Wiley and Sons Asia Pte Ltd and Chinese Automatic Control Society

Design and Simulation of Filterless Optical Networks: Problem Definition and Performance Evaluation

Filterless optical networks based on advanced transmission technologies and passive optical interconnections between nodes offer a lower-cost alternative to optical networks based on active photonic switching. A design and simulation platform is proposed for studying these novel network architectures and looking at their performance characteristics. Simulation results are presented for three reference network topologies, along with a comparative cost and performance study of active photonic and passive filterless optical network solutions.

A Passive Differential Termination and Signal Sensing Device for High-Speed (40 Gb/s) Test Applications

Differential input-ouput buffers are frequently utilized in high-speed communication systems. Often, a transmit buffer is connected to a 100-Ω differential receive buffer through a passive interconnect link with no means of verifying the true differential signal quality of the transmitter. Additionally, many electrical protocol specifications are defined assuming differential transmitter termination into 100 Ω with no common-mode reference. Commercially available, active probe test equipment can be cost prohibitive or have limited functionality due to unwanted parasitics inherent in the active devices. This paper describes a passive high-bandwidth 100-Ω differential termination device for characterizing high-speed differential buffers using standard test equipment.

100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm2 Nb Multi-Layer Process

A single flux quantum (SFQ) logic cell library has been developed for the 10kA/cm 2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5 kA/cm 2 to 10 kA/cm 2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400 GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100 GHz.

Nanopackaging research at Georgia Tech

The vision of GT-PRC's 3D systems is to go beyond 3D ICs to miniaturize the entire electronic or bioelectronic system components to nanoscale, such as passive components, system interconnections, thermal structures, and power supplies. Recent advances in the synthesis of nanomaterials with outstanding properties combined with novel processing technologies can lead to highly miniaturized, highly functional, and lowcost components and systems (Table 2). The nano to microscale wiring on system packages, off-chip nanointerconnections, and functional nanocomponents for RF, digital, and biofunctions will eventually migrate systems to nanoscale. Nanopackaging, therefore, should transform the handheld devices of today to become megafunctional convergent systems with computing, communications, and sensor capabilities.

Superconductor-to-Semiconductor Interface Circuit for High Data Rates

We present a new kind of rapid-single-flux-quantum (RSFQ) output driver together with a pseudomorphic high electron mobility transistor (p-HEMT) amplifier both operating at liquid helium temperature. The passive interconnect including the interchip connection between the RSFQ output driver and the first transistor stage of the semiconductor amplifier is the key element for signal matching and was optimized for minimizing the reflections to the RSFQ circuit. The RSFQ output driver is based on a single-flux-quantum to dc converter and a voltage doubler. The circuit is realized in the Niobium based 1 kA/cm2 process of FLUXONICS Foundry and provides up to 438-muV output voltage. We demonstrate high-speed experiments of the output driver in combination with two different semiconductor amplifier circuits at liquid helium temperature. The output voltage of a 2-Gb/s data stream was measured to be about 3.5 mV.

A Millimeter-Wave LC Cross-Coupled VCO for 60 GHz WP AN Application in a 0.13-μm Si RF CMOS Technology

Recently, the demand on ㎜-wave (millimeter-wave) applications has increased dramatically. While circuits operating in the ㎜-wave frequency band have been traditionally implemented in Ⅲ-V or SiGe technologies, recent advances in Si MOSFET operation speed enabled ㎜-wave circuits realized in a Si CMOS technology. In this work, a 58 ㎓ CMOS LC cross-coupled VCO (Voltage Controlled Oscillator) was fabricated in a 0.13-㎛ Si RF CMOS technology. In the course of the circuit design, active device models were modified for improved accuracy in the ㎜-wave range and EM (electromagnetic) simulation was heavily employed for passive device performance predicttion and interconnection parasitic extraction. The measured operating frequency ranged from 56.5 to 58.5 ㎓ with a tuning voltage swept from 0 to 2.3 V. The minimum phase noise of -96 ㏈c/㎐ at 5 ㎒ offset was achieved. The output power varied around -20 ㏈m over the measured tuning range. The circuit drew current (including buffer current) of 10 ㎃ from 1.5 V supply voltage. The FOM (Figure-Of-Merit) was estimated to be -165.5 ㏈c/㎐.

Sparse and Passive Reduced-Order Interconnect Modeling by Eigenspace Method

The passive and sparse reduced-order modeling of a RLC network is presented, where eigenvalues and eigenvectors of the original network are used, and thus the obtained macromodel is more accurate than that provided by the Krylov subspace methods or TBR procedures for a class of circuits. Furthermore, the proposed method is applied to low pass filtering of a reduced-order model produced by these methods without breaking the passivity condition. Therefore, the proposed eigenspace method is not only a reduced-order macromodeling method, but also is embedded in other methods enhancing their performances.

Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process

This paper presents a multiparameter moment-matching-based model order reduction technique for parameterized interconnect networks via a novel two-directional Arnoldi process (TAP). It is referred to as a Parameterized Interconnect Macromodeling via a TAP (PIMTAP) algorithm. PIMTAP inherits the advantages of previous multiparameter moment-matching algorithms and avoids their shortfalls. It is numerically stable and adaptive. PIMTAP model yields the same form of the original state equations and preserves the passivity of parameterized RLC networks like the well-known method passive reduced-order interconnect macromodeling algorithm for nonparameterized RLC networks.

Passive Finite-Dimensional Repetitive Control of Robot Manipulators

In this paper, a new class of finite-dimensional repetitive controllers for robot manipulators is proposed. The global asymptotic stability is proved for the unperturbed system. The passivity-based design of the proposed repetitive controller avoids the problem of tight stability conditions and slow convergence of the conventional, internal model-based, repetitive controllers. The passive interconnection of the controller and the nonlinear mechanical systems provides the same stability conditions as the controller with the exact feed-forward compensation of robot dynamics. The simulation results on a three degrees of freedom spatial manipulator illustrate the performances of the proposed controller.

PWM Converter Power Density Barriers

Power density of power electronic converters in different applications has roughly doubled every 10 years since 1970. Behind this trajectory was the continuous advancement of power semiconductor device technology allowing an increase of converter switching frequencies by a factor of 10 every decade. However, today's cooling concepts, and passive components and wire bond interconnection technologies could be major barriers for a continuation of this trend. For identifying and quantifying such technological barriers this paper investigates the volume of the cooling system and of the main passive components for the basic forms of power electronics energy conversion in dependency of the switching frequency and determines switching frequencies minimizing the total volume. The analysis is for 5 kW rated output power, high performance air cooling, advanced power semiconductors, and single systems in all cases. A power density limit of 28 kW/dm3@300 kHz is calculated for an isolated DC-DC converter considering only transformer, output inductor and heat sink volume. For single-phase AC-DC conversion a general limit of 35 kW/dm3 results from the DC link capacitor required for buffering the power fluctuating with twice the mains frequency. For a three-phase unity power factor PWM rectifier the limit is 45 kW/dm3@810 kHz just taking into account EMI filter and cooling system. For the sparse matrix converter the limiting components are the input EMI filter and the common mode output inductor; the power density limit is 71 kW/dm3@50 kHz when not considering the cooling system. The calculated power density limits highlight the major importance of broadening the scope of research in power electronics from traditional areas like converter topologies, and modulation and control concepts to cooling systems, high frequency electromagnetics, interconnection technology, multi-functional integration, packaging and multi-domain modeling and simulation to ensure further advancement of the field along the power density trajectory.

Design and implementation of a pipelined 8 bit-serial single-flux-quantum microprocessorwith cache memories

A pipelined 8 bit-serial single-flux-quantum microprocessor integrating cache memories, calledCORE1γ, has been designedand implemented. The CORE1γ has 16 byte and 8 byte shift-register-based cache memories for instructions and for data,respectively. The microprocessor overlaps four instructions in pipeline executions. Thepipeline stages are optimized to control the cache memories and a new circuit component isdeveloped to manage the pipeline execution according to whether each cache hits or misses.Advanced passive transmission line techniques with use of the cell library of the2.5 kA cm−2 niobium standard process are utilized to implement theCORE1γ accompanied by extremely complex interconnects. TheCORE1γ is made up of 295 passive interconnects, and 22302 Josephson junctions are integrated on a6.36 × 6.36 mm2 area. The logic simulation shows that the peak performance is estimated at 1000 millionoperations per second, and it is kept even during memory access as long as the cachememories hit.

Interval-Valued Reduced-Order Statistical Interconnect Modeling

We show how advances in the handling of correlated interval representations of range uncertainty can be used to approximate the mass of a probability density function as it moves through numerical operations and, in particular, to predict the impact of statistical manufacturing variations on linear interconnect. We represent correlated statistical variations in resistance-inductance-capacitance parameters as sets of correlated intervals and show how classical model-order reduction methods - asymptotic waveform evaluation and passive reduced-order interconnect macromodeling algorithm - can be retargeted to compute interval-valued, rather than scalar-valued, reductions. By applying a simple statistical interpretation and sampling to the resulting compact interval-valued model, we can efficiently estimate the impact of variations on the original circuit. Results show that the technique can predict mean delay and standard deviation with errors between 5% and 10% for correlated parameter variations up to 35%.

Model order reduction using spline-based dynamic multi-point rational interpolation for passive circuits

The efficient modeling of integrated passive components and interconnects is vital for the realization of high performance mixed-signal systems. In this paper, we develop a dynamic multi-point rational interpolation method based on Krylov subspace techniques to generate reduced order models for passive components and interconnects that are accurate across a wide-range of frequencies. We dynamically select interpolation points by applying a cubic spline-based algorithm to detect complex regions in the system's frequency response. The results indicate that our method provides greater accuracy than techniques that apply uniform interpolation points.