Abstract
A pipelined 8 bit-serial single-flux-quantum microprocessor integrating cache memories, calledCORE1γ, has been designedand implemented. The CORE1γ has 16 byte and 8 byte shift-register-based cache memories for instructions and for data,respectively. The microprocessor overlaps four instructions in pipeline executions. Thepipeline stages are optimized to control the cache memories and a new circuit component isdeveloped to manage the pipeline execution according to whether each cache hits or misses.Advanced passive transmission line techniques with use of the cell library of the2.5 kA cm−2 niobium standard process are utilized to implement theCORE1γ accompanied by extremely complex interconnects. TheCORE1γ is made up of 295 passive interconnects, and 22302 Josephson junctions are integrated on a6.36 × 6.36 mm2 area. The logic simulation shows that the peak performance is estimated at 1000 millionoperations per second, and it is kept even during memory access as long as the cachememories hit.
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