Passive CMOS Research Articles

Breakdown performance of guard ring designs for pixel detectors in 150 nm CMOS technology

Silicon pixel sensors manufactured using commercial CMOS processes are promising instruments for high-energy particle physics experiments due to their high yield and proven radiation hardness. As one of the essential factors for the operation of detectors, the breakdown performance of pixel sensors constitutes the upper limit of the operating voltage. Six types of passive CMOS test structures were fabricated on high-resistivity wafers. Each of them features a combination of different inter-pixel designs and sets of floating guard rings, which differ from each other in the geometrical layout, implantation type, and overhang structure. A comparative study based on leakage current measurements in the sensor substrate of unirradiated samples was carried out to identify correlations between guard ring designs and breakdown voltages. TCAD simulations using the design parameters of the test structures were performed to discuss the observations and, together with the measurements, ultimately provide design features targeting higher breakdown voltages.

Characterisation, simulation and test beam data analysis of stitched passive CMOS strip sensors

In the passive CMOS Strips Project, strip sensors were designed at the University of Bonn and produced by LFoundry in 150 nm technology, with an additional backside processing from IZM Berlin. Up to five individual reticules were connected by stitching at the foundry in order to obtain the typical strip lengths required for the LHC Phase-II upgrade of ATLAS or CMS trackers. Sensors electrical properties were simulated using Sentaurus TCAD and the results were compared to experimentally measured data. Detector modules were also constructed from several sensors and thoroughly studied in two beam campaigns at DESY. All of these measurements were performed before and after irradiation. This contribution provides an overview of simulation results, its comparison to measured data and in particular presents first test beam results for irradiated and unirradiated passive CMOS strip sensors. We are demonstrating that large area sensors with sufficient radiation hardness can be obtained by stitching during the CMOS process, and presenting our plans for the next submission in the framework of this project.

A Compact and Wideband mmWave Passive CMOS Circulator Based on Switched All-Pass Networks

A Compact and Wideband mmWave Passive CMOS Circulator Based on Switched All-Pass Networks

Techniques for the Investigation of Segmented Sensors Using the Two Photon Absorption-Transient Current Technique

The two photon absorption-transient current technique (TPA-TCT) was used to investigate a silicon strip detector with illumination from the top. Measurement and analysis techniques for the TPA-TCT of segmented devices are presented and discussed using a passive strip CMOS detector and a standard strip detector as an example. The influence of laser beam clipping and reflection is shown, and a method that allows to compensate these intensity-related effects for investigation of the electric field is introduced and successfully employed. Additionally, the mirror technique is introduced, which exploits reflection at a metallised back side to enable the measurement directly below a top metallisation while illuminating from the top.

Characterization of passive CMOS sensors with RD53A pixel modules

Both the current upgrades to accelerator-based HEP detectors (e.g. ATLAS, CMS) and also future projects (e.g. CEPC, FCC) feature large-area silicon-based tracking detectors. We are investigating the feasibility of using CMOS foundries to fabricate silicon radiation detectors, both for pixels and for large-area strip sensors. A successful proof of concept would open the market potential of CMOS foundries to the HEP community, which would be most beneficial in terms of availability, throughput and cost. In addition, the availability of multi-layer routing of signals will provide the freedom to optimize the sensor geometry and the performance, with biasing structures implemented in poly-silicon layers and MIM-capacitors allowing for AC coupling. A prototyping production of strip test structures and RD53A compatible pixel sensors was recently completed at LFoundry in a 150nm CMOS process. This presentation will focus on the characterization of pixel modules, studying the performance in terms of charge collection, position resolution and hit efficiency with measurements performed in the laboratory and with beam tests. We will report on the investigation of RD53A modules with 25x100 μm2 cell geometry.

Characterization of irradiated passive CMOS sensors for tracking in HEP experiments

The upgrades to accelerator-based HEP detectors (e.g. ATLAS, CMS) as well as future projects (e.g. CEPC, FCC) feature large-area silicon-based tracking detectors. Using production lines of industrial CMOS foundries to fabricate silicon radiation detectors, both for pixels and for large-area strip sensors would be most beneficial in terms of availability, throughput and cost. First samples of pixel sensors coming from the LFoundry production line have already been tested and showed good performance up to irradiation levels of 1×1016neq cm−2 for their potential operations as sensors for the CMS inner tracker. This paper will focus on the characterization of pixel modules at high irradiation levels, up to 2×1016neq cm−2, studying the performance in terms of charge collection, position resolution and hit efficiency with measurements performed in the laboratory and with beam tests.

Characterization of irradiated RD53A pixel modules with passive CMOS sensors

We are investigating the feasibility of using CMOS foundries to fabricate silicon detectors, both for pixels and for large-area strip sensors. The availability of multi-layer routing will provide the freedom to optimize the sensor geometry and the performance, with biasing structures in poly-silicon layers and MIM-capacitors allowing for AC coupling. A prototyping production of strip test-structures and RD53A compatible pixel sensors was recently completed at LFoundry in a 150 nm CMOS process. This paper will focus on the characterization of irradiated and non-irradiated pixel modules, composed by a CMOS passive sensor interconnected to a RD53A chip. The sensors are designed with a pixel cell of 25 × 100 μm2 in case of DC coupled devices and 50 × 50 μm2 for the AC coupled ones. Their performance in terms of charge collection, position resolution, and hit efficiency was studied with measurements performed in the laboratory and with beam tests. The RD53A modules with LFoundry silicon sensors were irradiated to fluences up to .

Characterization of passive CMOS strip sensors

Recent advances in CMOS imaging sensor technology, e.g. in CMOS pixel sensors, have proven that the CMOS process is radiation tolerant enough to cope with certain radiation levels required for tracking layers in hadron collider experiments. With the ever-increasing area covered by silicon tracking detectors cost effective alternatives to the current silicon sensors and more integrated designs are desirable. This article describes results obtained from laboratory measurements of silicon strip sensors produced in a passive p-CMOS process. Electrical characterization and charge collection measurements with a 90Sr source and a laser with infrared wavelength showed no effect of the stitching process on the performance of the sensor.

Radiation tolerant, thin, passive CMOS sensors read out with the RD53A chip

The radiation hardness of passive CMOS pixel sensors fabricated in 150nm LFoundry technology is investigated. CMOS process lines are especially of interest for large-scale silicon detectors as they offer high production throughput at comparatively low cost. Moreover, several features like poly-silicon resistors, MIM-capacitors and several metal layers are available which can help enhance the sensor design. The performance of a 100µm thin passive CMOS sensor with a pixel pitch of 50µm at different irradiation levels, 5 × 1015neqcm−2 and 1 × 1016neqcm−2, is presented. The sensor was bump-bonded and read out using the RD53A readout chip. After the highest fluence a hit-detection efficiency larger than 99% is measured for minimum ionising particles. The measured equivalent noise charge is comparable to conventional planar pixel sensors. Passive CMOS sensors are thus an attractive option for silicon detectors operating in radiation harsh environments like the upgrades for the LHC experiments.

Characterization of small-pixel passive CMOS sensors in 150 nm LFoundry technology using the RD53A readout chip

Passive CMOS pixel sensors in 150nm CMOS technology offered by LFoundry were designed and assembled into hybrid pixel modules. Advantages of commercial CMOS processes are high throughput at comparatively low costs which makes them attractive for the usage of large-area detectors. Further benefits originate from multiple metal layers, metal–insulator–metal capacitors, and polysilicon layers which can be used to enhance the sensor design. Thinned sensors were bump-bonded to the RD53A readout chip and characterized in laboratory environment and with a minimum ionizing 2.5GeV electron beam. Their performance in terms of noise and hit-detection efficiency equals that of conventional planar pixel sensors.

A Low-Loss Compact 60-GHz Phase Shifter in 65-nm CMOS

This paper presents a 60-GHz low-loss compact 4-b phase shifter in a 65-nm CMOS. It is based on a 1-b high-pass/low-pass structure and a 3-b switched-filter structure, and employs fully custom-designed capacitors with a high quality factor for low insertion loss. The phase shifter with custom-designed capacitors reduces an insertion loss by 2.6 dB at 60 GHz. The average insertion loss is 8.1 dB at 60 GHz, and the return loss is better than 10.6 dB over a range of 57–66 GHz. The measured 16-output state of the fabricated phase shifter has a phase resolution of 22.5° with an rms phase error less than 5.5° over the 57–66 GHz range. The fabricated phase shifter has a compact core size of 0.42 mm $\times0.22$ mm. To the best of our knowledge, this phase shifter achieves the lowest insertion loss and the smallest core area of all the published 60-GHz 360° -coverage passive CMOS phase shifters.

Study of Passive CMOS Mixers Effects on Image Rejection Ratio

In this brief, modeling and simulation of quadrature passive mixers are analyzed, focusing on the impact they have on the image rejection ratio (IRR). For this purpose, a 65-nm CMOS technology is used.

A New Passive CMOS Mixer With LO Shaping Technique for mmWave Applications

A mmWave (mmW) passive mixer topology based on a novel LO waveform-shaping technique using non-linear transmission line (NLTL) is proposed. The NLTL is constructed using series inductors and shunt varactors. It boosts the LO signal swing and reshapes the LO waveform to have higher amplitude and narrower pulses, resulting in higher gain, better linearity, and lower Noise Figure (NF) of the mixer. Mixers operating at 60 GHz are designed and implemented using 65 nm CMOS process. Simulation results show the mixer with the proposed technique obtains an NF of 5.5 dB, an input-referred $\text{P}_{1 \text{dB}}$ $(\text{IP}_{1 \text{dB}})$ of 0 dBm, and a voltage conversion gain of 1.2 dB with 0 dBm LO signal and zero dc power consumption. Silicon measurement results show that the proposed LO shaping technique improves the conversion gain by 2.5 dB and the $\text{IP}_{1 \text{dB}}$ by 3 dB.

Low-Loss Integrated Passive CMOS Electrical Balance Duplexers With Single-Ended LNA

A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky surface acoustic wave (SAW) and bulk acoustic wave (BAW) duplexers in third-generation (3G)/fourth-generation (4G) cellular transceivers. A balancing network creates a replica of the transmitter (TX) signal for cancellation at the input of a single-ended low-noise amplifier (LNA) to isolate the receive path from the TX. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra baluns at the antenna side. The balancing network enables a single-ended LNA with reliable high TX power operation up to 22 dBm by alleviating the common-mode coupling. The duplexer achieves around 50-dB transmitter-receiver (TX-RX) isolation within a 1.6-2.2-GHz range. The cascaded noise figure (NF) of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in a 0.18-μm CMOS process and occupy an active area of 0.35 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A high linearity downconverter for digital broadcasting system

An integrated downconverter with high linearity for digital broadcasting system receivers is implemented in a 0.13 μm CMOS process with an active area of 0.1 mm2. The current-mode scheme is adopted to improve linearity performance by avoiding voltage fluctuation. A passive CMOS switching pair is utilized to improve the even-order linearity of the downconverter. A current amplifier is used to provide low input impedance which will easily lead to a wide operating bandwidth and high linearity. Moreover, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers and also low input impedance. The digital-assisted DC offset calibration improves the second-order distortion of the downconverter. This design achieves a maximum gain of 40 dB and a dynamic range of 10 dB. Measured noise figure is 8.2 dB, an IIP2 of 63 dBm, an IIP3 of 17 dBm at the minimum gain of 30 dB. The downconverter consumes about 7.7 mA under a supply of 1.2 V.

A –$21.2$-dBm Dual-Channel UHF Passive CMOS RFID Tag Design

Previous research results showed that UHF passive CMOS RFID tags had difficulty to achieve sensitivity less than -20 dBm. This paper presents a dual-channel 15-bit UHF passive CMOS RFID tag prototype that can work at sensitivity lower than -20 dBm. The proposed tag chip harvests energy and backscatters uplink data at 866.4-MHz (for ETSI) or 925-MHz (for FCC) channel and receives downlink data at 433-MHz channel. Consequently, the downlink data transmission does not interrupt our tag from harvesting RF energy. To use the harvested energy efficiently, we design a tag chip that includes neither a regulator nor a VCO such that the harvested energy is completely used in receiving, processing, and backscattering data. Without a regulator, our tag uses as few active analog circuits as possible in the receiver front-end. Instead, our tag uses a novel digital circuit to decode the received data. Without a VCO, the design of our tag can extract the required clock signal from the downlink data. Measurement result shows that the sensitivity of the proposed passive tag chip can reach down to -21.2 dBm. Such result corresponds to a 19.6-m reader-to-tag distance under 36-dBm EIRP and 0.4-dBi tag antenna gain. The chip was fabricated in TSMC 0.18- μm CMOS process. The die area is 0.958 mm ×0.931mm.

Simulation of the Photodetection in the PPS CMOS Sensors

The paper contains an analysis and simulation of passive pixel based sensors. The passive pixel CMOS image acquisition sensor (PPS) is the key part of a visible image capture systems. The PPS is a complex circuit composed by an optical part and an electrical part, both analog and digital. The goal of this paper is to simulate the functionality of the photodetection process that happens in the PPS sensor. The photodetector is responsible with the conversion from photons to electrical charges and then into current. In the optical part, the sensor is analyzed by a spectral image processing algorithm which uses as input data: the lenses array transmittance, the red, green and blue filters and the quantum efficiency of the PPS. In the electrical part of simulation, the program is computing the signal to noise ratio of the sensor taking into account the photon shot, white and fixed pattern noises. Our basic analysis is based on camera equation to which we add the noises.

Large-Signal Measurements and Nonlinear Characterization of an Analog Frontend for Passive UHF CMOS RFID Transponders

This work focuses on the comprehensive measurement-based nonlinear characterization of an integrated analog frontend, which is implemented into a passive multifunctional radio-frequency-identification (RFID) transponder. It explains the necessity and the practical execution of large-signal characterization and nonlinear analyses of the frontend at ultra-high-frequencies. The fundamentals of the implemented source-pull measurement setup are described in detail and the results of selected measurements are presented. To the authors knowledge, this is the first time that a passive RFID frontend is characterized by nonlinear large-signal measurements.

A Low-Loss Image-Reject Mixer Using Source Follower Isolation Method for DRM/DAB Tuner Applications

A novel low-loss image-reject mixer (IRM) using the source follower isolation method for digital radio mondiale/digital audio broadcasting applications is presented. It is based on double-quadrature mixers (DQMs) and passive polyphase filters (PPFs). The DQM is designed with four passive CMOS mixers. A source follower is inserted between the RF PPF and DQM to decrease the conversion loss of the IRM. Compared with the traditional isolation method, the source follower isolation method shows much higher on-resistance while looking into the RF port of the mixer; meanwhile, the chip area will be greatly decreased. This chip is fabricated in a 0.18-μm CMOS technology. The total conversion loss is 10.5 dB, and the conversion loss per stage of PPFs is 2.1 dB on average. The image-reject ratio is larger than 40 dB in the bandwidth of 1.536 MHz without trimming and calibration. The PldB gain compression point is 7.6 dBm. The chip core area is 1.1 × 1.3 mm2.

A 5‐GHz energy‐efficient tunable pulse generator for ultra‐wideband applications using a variable attenuator for pulse shaping

SUMMARYA new energy‐efficient tunable pulse generator is presented in this paper using 0.13‐µm CMOS technology for short‐range high‐data‐rate 3.1–10.6 GHz ultra‐wideband applications. A ring oscillator consisting of current‐starved CMOS inverters is quickly switched on and off for the duration of the pulse, and the amplitude envelope is shaped with a variable passive CMOS attenuator. The variable passive attenuator is controlled using an impulse that is created by a low‐power glitch generator (CMOS NOR gate). The glitch generator combines the falling edge of the clock and its delayed inverse, allowing the duration of the impulse to be changed over a wide range (500–900 ps) by varying the delay between the edges. The pulses generated with this technique can provide a sharp frequency roll off with high out‐of‐band rejection to help meet the Federal Communications Commission mask. The entire circuit operates in switched mode with a low average power consumption of less than 3.8 mW at 910 MHz pulse repetition frequency or below 4.2 pJ of energy per pulse. It occupies a total area of 725 × 600 µm2 including bonding pads and decoupling capacitors, and the active circuit area is only 360 × 200 µm2. Copyright © 2011 John Wiley &amp; Sons, Ltd.