Passivation Cracks Research Articles

Evaluation of tensile property and strengthening mechanism of Zirconia reinforced molybdenum alloy

In this experiment, the nano-ZrO2 particles reinforced molybdenum alloy with excellent mechanical properties were prepared through liquid-liquid doping process, and the comparison with TZM alloy prepared by solid-solid doping process was conducted. During the liquid-liquid doping process, the ZrO2 particles ensured the dispersion of the second phase in alloy because they reached molecular-level uniformity, and the hydrothermal synthesis preparation process enabled the ZrO2 particles in alloy to reach nanometer size level. In Mo-ZrO2 alloy, the small and dispersed ZrO2 can effectively block dislocation and passivation cracks; both the room temperature and high temperature performance of Mo-1.5 %ZrO2 alloy was better than that of TZM alloy. Based on the hindered recrystallization process, improved recrystallization temperature, as well as enhanced recrystallization strength thanks to the alloy pinning effect of ZrO2, the maximum tensile stress of Mo-1.5 %ZrO2 alloy at 1000 ℃ was about 14 % higher than pure molybdenum, and the maximum tensile stress of Mo-1.5 %ZrO2 alloy at 1400 ℃ was at least 45 % higher than pure molybdenum. Quantitative analysis shows that the strengthening effect of the second phase was the best during the recrystallization process.

A Mechanistic Model for Plastic Metal Line Ratcheting Induced BEOL Cracks in Molded Packages

Metal line ratcheting and passivation cracking in back-end-of-line (BEOL) structures are significant reliability concerns for molded packages that are in widespread use at the present time. When metal lines plastically deform due to ratcheting, the passivation overcoat accumulates stress at the corner upon temperature cycling and is eventually susceptible to fracture. Since packaging materials’ interaction with the die is the cause of the failure, the problem is inherently multiscale in nature requiring the analysis model to span from package dimension to BEOL length scale. In this article, the mechanistic cause for stress accumulation is elucidated. Furthermore, a global–local modeling strategy is applied to model the passivation crack initiation and growth. A global model with coarse mesh was built of the package. The local region around the interconnect metal line in the die was modeled using boundary conditions extracted from the global model. A novel load decomposition technique is developed to identify the loading mode that best correlates with the experimentally observed fracture. It is shown that shear is the dominant loading mode inducing the observed die cracks. Furthermore, it is demonstrated that the thermal expansion mismatch between the mold compound and the lead frame with the silicon die induces the shear load on the BEOL structure. Due to the fact that mold compound is applied at a temperature that is higher than that seen during thermal cycling, the direction of the induced shear load is constant regardless of whether the package is heated or cooled. As the metal line plastically yields during every temperature cycle, the plastic deformation ratchets or accumulates in the same direction over the course of the thermal cycling test. The yielding of metal line results in stiffness reduction, leading to steady accumulation of stress in the passivation corner, causing it to fracture eventually.

Experimental Study on Mitigation of Lifetime-Limiting Dielectric Cracking in Extreme Temperature 4H-SiC JFET Integrated Circuits

While NASA Glenn Research Center’s “Generation 10” 4H-SiC Junction Field Effect Transistor (JFET) integrated circuits (ICs) have uniquely demonstrated 500 °C electrical operation for durations of over a year, this experimental work has also revealed that physical cracking of chip dielectric passivation layers ultimately limits extreme-environment operating lifetime [1-3]. The prevention of such dielectric passivation cracks should therefore improve IC high temperature durability and yield, leading to more beneficial technology adoption into aerospace, automotive, and energy systems. This report describes Generation 10.2, 11.1, and 11.2 die tested under unbiased and unpackaged accelerated age testing at 500 °C, 600 °C, 720 °C, and 800 °C in air-atmosphere ovens for 100-and 200-hour duration. Additional samples were separately subjected to 10 thermal cycles between the same high temperatures (with 10-hour high-temperature soak each cycle) and 50 °C. It is shown that having two stoichiometric Si3N4 layers in the interconnect dielectric stack substantially decreases the amount of dielectric cracking observed following these oven tests.

Residual stress effect governing electromigration-based free-standing metallic micro/nanowire growth behavior

In this study, the effect of residual stress in a film on the growth behavior of a free-standing metallic micro/nanowire due to electromigration (EM) is examined. The growth of a wire is accompanied by atomic diffusion, accumulation of atoms, and release of compressive EM-induced localized hydrostatic stress due to the accumulation of atoms. Hence, the growth of the wire dominantly depends on the EM-induced localized stress caused by the accumulation of atoms. Because rigid passivation generates a strong localized stress field in the metallic interconnect, with greater accumulation of atoms, the EM-induced localized stress state for wire growth is influenced by passivation conditions, including the thickness and residual stress associated with passivation. Two samples with different passivation thicknesses, resulting in different levels of residual stress, were used to elucidate the influence of passivation conditions on the growth performance of Al microwires. The growth rate was experimentally measured. An x-ray diffraction system was used to obtain the value of residual stress in passivation, demonstrating that a higher absolute value of compressive residual stress results in a lower growth rate. In contrast, a lower absolute value increases the growth rate of the wire and can decrease the delamination risk of the topmost passivation, deposited by sputtering. Contrarily, a passivation that is too thin, resulting in a lower absolute value of compressive stress, increases the risk of passivation crack due to the accumulation of atoms by EM. A suitable passivation thickness for a desired wire growth must be determined based on this finding.

Analyzing and Eliminating Die Passivation Crack in a Power Leadframe Package using Submodeling Approach

This paper presents the submodeling approach in thermo-mechanical simulation of the die passivation crack encountered in a power leadframe package subjected to temperature cycling condition. Without using modeling and simulation in resolving semiconductor package development issues, the process would be very costly and time-consuming. For die passivation crack, the details of the different layers of the die passivation need to be modeled and this would result in a large simulation model with considerable solution time. However, a technique known as submodeling can be used to reduce solution time without sacrificing accuracy of results. In this study, submodeling was successfully used to analyze the stresses in the critical passivation layer that resulted in the best design that eliminated the passivation crack. The modeling result showed that the crack could be eliminated by using the right passivation material layer combination and thickness. An increase in the thickness of the material layers and the additional of sublayers have provided significant stress reduction in the topmost critical passivation layer resulting in crack elimination.

Glass Frit Wafer Bonding for Encapsulating Monolithic Integrated CMOS-MEMS Devices

CMOS-MEMS integration is getting a more and more important topic with growing expectations and requirements on the function and performance of micro sensors. The integration of ASICs and memories to MEMS sensor structures allows by calibration the compensation of side effects (temperature influences, stress influences, …) and manufacturing tolerances. Thus, very accurate sensors, at acceptable cost structures for high volume applications become feasible. These high volume applications are often for mobile devices or other use cases where the form factor is important as well – here the wafer level integration and the wafer level packaging (wafer bonding) also offer many opportunities. This paper addresses a 0.35µm CMOS process (X-FAB XH035 technology) based integrated sensors. The sensor structure is constructed by using standard features of the CMOS components. To reach the required performance on chip, ASIC including memories are needed. All these features are on one and the same wafer – MEMS and CMOS are side by side monolithically integrated in the same piece of silicon. To make the sensor functional, parts of the CMOS structures need to be undercut by silicon etching from the wafer front side. This requires the opening of the CMOS passivation to get access to the silicon and a very special release etch process. In a next step, these released very fragile structures need to be protected mechanically on wafer level by bonding a structured cap wafer. Additionally, in this step a hermetically sealed cavity with the MEMS structure is formed. By a dicing process the silicon over the wire bond pad area is finally removed to enable wafer probing (Fig. 1 and 2 show this configuration). By advanced packaging processes (die and wire bonding and special plastic moulding) the final device is realized in a small and thin package. In this very complex technology wafer bonding is a key process. Glass frit wafer bonding was chosen as bonding process as it allows a quite simple process set up. The Glass paste can be printed on top of the structured cap wafer and after the multiple temperature step glass conditioning (firing) the wafer can be bonded on the processed MEMS/CMOS wafer. However, many side effects need to be considered in this process to fulfil the sensor performance spec and to get a stable production process. These aspects are here shortly named and will be discussed in detail in the related full paper: The bonding has to be done on top of CMOS structures, actually on top of the CMOS passivation. The passivation stack itself should not be changed - so the bonding surface is silicon nitride, due to its hydrophobic nature it is rather difficult to bond. Additionally, any damages of passivation need to be avoided. Due to the fact that any glass frit is containing sharp filler particles to adapt the thermal coefficient of extension of the glass to the silicon, a paste material has to be used with low particle sizes to prevent a damaging of the passivation. By additionally using a flat passivation, variant local stress can be avoided - this is preventing from passivation cracks. The bond interface has to be of high quality. The bond needs to be mechanically strong and hermetically sealed. The requirement for this is a very good screen printing process – fig. 3 shows such an optimal structure. By means of screen printing process improvements this could be stably achieved. The second important point here is the bonding temperature: it has to be high enough to let the glass flow wet the surface to allow a sealing and strong bonding. Here optimizations resulted in a nearly 100 % yield of sealed devices and prevented the removal of any caps in the later process steps like dicing. This application of the glass fit bonding shows that this process can be used for very sophisticated applications. The investigation provided a new understanding of the material, the bonding process and boundary conditions. Acknowledgements: The authors would like to thank Dr. Frank Seifert (Fraunhofer ENAS Chemnitz) for supporting the screen printing process optimization and Dr. Appo van der Wiel (Melexis) for advising about device integration aspects. Figure 1

Reduction of Thermal Stress - Part II: Passivation Thickness Optimization of FLATPV Surface Bump Design

Abstract Surface undulations on semiconductor devices can increase chip package interaction stress that leads to possible passivation cracking. This is especially so for flip chip interconnects which have solder balls that are in contact with the passivation layer. The solder balls have a larger Coefficient of Thermal Expansion (CTE) compared to the passivation layers and this can lead to increase in fracture rate especially during reflow cooling. The other factor is the underfill material. The flat passivation design can reduce the chip package interaction for underfill material but it needed to be evaluated numerically for wafer level stress before being touted as a solution towards reducing passivation cracks. In Part II of this series of papers, the flat passivation layer thicknesses were numerically simulated and modified using response surface methodology design of experiments (RSM DOE) techniques. The optimized passivation layer thickness showed decreased stress which was validated using a simulation confirmation run.

(Invited) Trench-Gated MOSFET Instability Caused by High Temperature Reverse-Bias Stress

The trench-gated MOSFET is widely used in power management applications because of its ultra-low on resistance [1]. Studies of trench-gate MOSFET reliability and degradation of blocking voltage and leakage current as well as edge termination effects are becoming increasingly important as the device dimensions shrink and its applications are diversified. The HTRB (high temperature reverse-bias) and HAST (highly accelerated temperature & humidity stress test) are often used in reliability assessment of planar discrete power MOSFETs [2] and are currently used in trench-gated MOSFET. The both HTRB stress and HAST stress apply a reverse bias voltage on the drain side with the source and gate grounded at elevated temperature in a MOSFET device. However, the HAST stress is at 85% HR relative humidity under pressure condition. The possible failure modes for HTRB and HAST stress are IDSS (drain to source) leakage current increase or shift, breakdown voltage shift or degradation, and Vth (threshold voltage) shift or instability. The failure mechanism under various failures is complex. They depend on not only device design and process, but also package process and its materials such as mold compound, as well as interaction between device and package. In this paper, we discuss the instability of n-channel trench-gated MOSFET under HTRB and HAST reliability stresses. The devices are packaged by using state-of-the-art “low pitch” wafer-level-chip-scale package (WLCSP) without the use of mold compound or leads frame. We have observed that the HTRB and HAST stress increases gate oxide interface trap density. However humid HAST stress is observed to further introduce mobile positive charge in the gate oxide of the trench-gated MOSFET. This positive charge is argued to comprise protons (H+s) [3]. The proton is generated through electric-field assisted interaction and hole injection into the gate oxide at the bottom of the trench. The mobility of these protons is observed to cause gate-voltage induced modulation in the threshold voltage and leakage current of the trench-gated MOSFET. In order to determine the mechanism by which H+s are introduced in the oxide, SEM inspection of the n-channel trench-gated MOSFET deprocessed to passivation showed the presence of passivation cracks in the device’s edge termination which cause moisture penetrated in the device during the HAST stress. Furthermore, the experimental and simulation results lead us to conclude that in this study we are observing negative bias temperature instability (NBTI) in a parasitic p-MOSFET structure arising at the bottom of the trench in an n-channel trench-gated MOSFET during HTRB stress [4]. The NBTI is enhanced by the presence of moisture in the oxide.

High-Temperature Reverse-Bias Stressing of Thin Gate Oxides in Power Transistors

A 160Å-thick gate oxide in n-channel U-shaped trench-gated MOSFETs (UMOSFETs) of ~0.5 microns trench width, ~1 microns channel length was high-temperature reverse-bias (HTRB) stressed, in either a dry or a 85%-relative-humidity ambient, for 96 hours at 130 °C in blocking mode with the source, body and gate grounded and a voltage of 20 V applied to the drain. After a humid stress, room-temperature (RT) measuements revealed that in some of the UMOSFETs the threshold voltage, Vth, decreased from ~0.6 V down to ~0.1 V, whereas the drain-to-source leakage current, IDSS, increased by three orders of magnitude. Changes in Vth and IDSS were found to be gate-controlled at RT. In UMOSFETs that were stressed in a dry ambient the degradation was insignificant and none of the above effects were observed. The observed behavior is a fingerprint of mobile ions which are able to move across the oxide driven by the electric field generated by the applied gate-voltage. The sign of the shift in Vth and its dependence on the applied gate-voltage polarity indicates that the mobile ions are positively charged. The observation that these ions are introduced during humid HTRB stress favors the identification of these ions as the hydrogen protons (H+). This identification is further supported by our observation that these ions are able to move at RT unlike several other metallic ions, such as Sodium, that require temperatures higher than RT for them to become mobile in the oxide. Indeed our experiments showed that H+ ions introduced in the UMOSFETs exhibit concentration gradient driven diffusion at RT even in the absence of an applied gate voltage. The HTRB does not only stress the pn junction at the drain, but also stresses the gate oxide at the bottom of the trench. Under the HTRB stress biasing conditions, the bottom of the trench behaves like a parasitic p-channel MOSFET with the N drift region as the channel and the p-well regions as the source and drain. Consequently, the HTRB stress of the n-channel UMOSFET manifests itself as a negative-bias temperature-instability “NBTI” [1] on the parasitic p-channel MOSFET. SEM inspection of UMOSFETs deprocessed to passivation showed the presence of passivation cracks on the edge termination only in devices that degraded with the HTRB stressing. Our results lead us to conclude that only humid HTRB/NBTI stress causes changes in Vth and IDDSalthough interface charge was observed to increase by both dry or humid stress. During the stress water or hydrogen species diffuse into the gate oxide through passivation cracks at the edge of the UMOSFET, and react with the gate oxide in the presence of holes and release protons [2,3]. The protons are not confined to the gate oxide at the trench-bottom and are able to migrate up the oxide on the trench sidewalls. Based on our results, the impact of the HTRB/NBTI stress on device design is discussed.

High temperature bias-stress-induced instability in power trench-gated MOSFETs

We report on the high-temperature reverse-bias (HTRB) stress reliability of trench-gated n-channel metal-oxide-silicon field-effect transistors (n-UMOSFETs). The degradation induced by the HTRB is examined using changes in transistor parameters, optical microscopy, and scanning electron microscopy. The HTRB causes degradations in the threshold voltage and drain leakage of the n-UMOSFET and these degradations are particularly large when the stress is applied in a humid ambient. The observations were interpreted in terms of water molecule diffusion into the gate oxide through passivation cracks in the edge termination of the n-UMOSFET during HTRB in a humid ambient. The water molecules catalyze proton (H+) generation through electric-field assisted interactions and hole injection into the gate oxide at the bottom of the trench. Also, H+ is observed to be very stable in the gate oxide and to migrate between the gate-oxide and oxide–Si interfaces driven by an applied gate-voltage. It is proposed that the employed HTRB configuration and level give rise to negative-bias temperature instability (NBTI) in a parasitic p-channel MOSFET structure occurring in the trench base of the n-UMOSFET, and that NBTI is a serious reliability concern in power UMOSFETs subjected to stress in a moist ambient.

Process Development and Reliability of Microbumps

The use of flip-chip bonding technology on gold-tin (AuSn) microbumps for flip-chip packaging is becoming increasingly important in the electronics industry. Some of the main advantages of AuSn system over solder flip-chip technology are suitability for very fine pitch interconnection and fluxless bonding. Fluxless flip-chip assembly is in demand especially for medical applications and optoelectonics packaging. Here, we report the assembly process development of a silicon stacked module assembled with AuSn microbumps to meet the stringent reliability. The effects of bond pressure distribution, bond temperature and alignment accuracy were found to be critical in this stacked silicon using AuSn microbumps. A three-factor design of experiment was carried out to investigate the effects of assembly parameters such as bonding pressure, temperature and time on contact resistance and AuSn solder wetting on the electroless nickel and gold under bump metallization. Results showed that higher bond force is undesirable and contributes to passivation cracking and deformed AuSn joint with AuSn solder being squeezed out of the joint during bonding. The reliability result of the flip-chip assembly of stacked silicon module using AuSn microbumps was presented.

Packaging Challenges on Shrink Chip Technology

As technology grows, semiconductor industry evolved towards tinier & thinner packages to meet market demand. To create competitiveness, chip size shrinkage at front-end wafer fabrication is essential for newer packages technology. With the tireless effort from front-end fab, die size & thickness are reduced up to 30%. There are changes on wire bond pad as well, pad opening is reduced & pad metallization is changed to NiPPdAu with barrier metal underneath. This paper will discuss in details mainly on die bonding & wire bonding challenges for shrink chip technology. Critical defects such as vertical crack die, die surface contamination & passivation crack were observed during process development stage. Several efforts were made to address them accordingly. Finally this paper will share on new failure mechanism observed during ramp up, evaluations for risk assessment & future improvement ideas to overcome mass production obstacles.

On the Way to Zero Defect of Plastic-Encapsulated Electronic Power Devices—Part II: Molding Compound

Concerning thermomechanically induced failures, such as metal line deformation and passivation cracks, there is a practicable way to achieve the zero-defect limit of plastic-encapsulated power devices. This limit can be reached by evaluating the influence of the major components involved and, consequently, by selecting the appropriate materials and measures. On the other hand, the interdependence between all components must always be kept in mind, i.e., chip and package have to be regarded as an entity. An important finding was that applying simply one improvement step will not necessarily lead to the desired goal. Only the implementation of all improvement steps considering their interdependence is the key for the perfect overall system chip and package. In Part II of this series of papers, the thermomechanical influence of the molding compound (MC) on the chip, i.e., the root cause of metal deformation and passivation cracks, was studied in great detail. Concerning the generation of these failures, the coefficient of thermal expansion was shown to play a key role. However, for a full understanding of the thermomechanically induced damage, the viscoelastic properties of the MC have to be considered.

On the Way to Zero Defect of Plastic-Encapsulated Electronic Power Devices—Part I: Metallization

Concerning thermomechanically induced failures, such as metal line deformation and passivation cracks, there is a practicable way to achieve the zero-defect limit of plastic-encapsulated power devices. This limit can be reached by evaluating the influence of the major components involved and, consequently, by selecting the appropriate materials and measures. On the other hand, the interdependence between all components must always be kept in mind, i.e., chip and package have to be regarded as an entity. An important finding was that applying simply one improvement step will not necessarily lead to the desired goal. Only the implementation of all improvement steps considering their interdependence is the key for the perfect overall system chip and package. In Part I of this series of papers, the yield stress of the power metallization is shown to play a crucial role for the generation of metal deformation and passivation cracks. Understanding the ratcheting mechanism led to the development of a new layered metallization material with a distinctly increased yield stress, resulting in a considerably reduced failure generation.

On the Way to Zero Defect of Plastic-Encapsulated Electronic Power Devices—Part III: Chip Coating, Passivation, and Design

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Concerning thermomechanically induced failures such as metal-line deformation and passivation cracks, there is a practicable way to achieve the zero-defect limit of plastic-encapsulated power devices. This limit can be reached by, first, evaluating the influence of the major components involved and, consequently, by selecting the appropriate materials and measures, and, second, by always keping in mind the interdependence between all components, i.e., chip and package have to be regarded as an entity. An important finding was that applying simply one improvement step will not necessarily lead to the desired goal. Only the implementation of all improvement steps considering their interdependence is the key for the perfect overall system chip and package. In Part III of this series of papers, the influence of passivation and die coating materials on thermomechanical damage is investigated. Finally, it is shown that an intelligent chip design, in combination with a stiff Al multilayer, a low-stress molding compound (low coefficient of thermal expansion and high Young's modulus), a new passivation material, and an appropriate polyimide layer, may reduce the thermomechanical damage to zero, even for electronic power devices. </para>

Factors to Influence Thermal-Cycling Reliability of Passivation Layers in Semiconductor Devices Utilizing Lead-on-Chip (LOC) Die Attach Technique

This article shows various factors that influence the thermal-cycling reliability of semiconductor devices utilizing the lead-on-chip (LOC) die attach technique. This work details how the modification of LOC package design as well as the back-grinding and dicing process of semiconductor wafers affect passivation reliability. This work shows that the design of an adhesion tape rather than a plastic package body can play a more important role in determining the passivation reliability. This is due to the fact that the thermal-expansion coefficient of the tape is larger than that of the plastic package body. Present tests also indicate that the ceramic fillers embedded in the plastic package body for mechanical strengthening are not helpful for the improvement of the passivation reliability. Even though the fillers can reduce the thermal-expansion of the plastic package body, microscopic examinations show that they can cause direct damage to the passivation layer. Furthermore, experimental results also illustrate that sawing-induced chipping resulting from the separation of a semiconductor wafer into individual devices might develop into passivation cracks during thermal-cycling. Thus, the proper design of the adhesion tape and the prevention of the sawing-induced chipping should be considered to enhance the passivation reliability in the semiconductor devices using the LOC die attach technique.

On chip–package stress interaction

In this paper, the interaction between chip and package is investigated. A series of experiments are conducted to investigate the effect of the package type on occurrence of passivation cracks in IC structures. Virtual prototyping is used to generate more accurate and efficient stress design rules for IC backend structures, in combination with packaging processes and geometry. The addressed failure mode of passivation cracks is found to depend on the package type or family: for exposed pad packages this failure mode is easier to occur. It is demonstrated that for successful development of IC backend structures and processes, it is essential to take into account the influence of the package in the earlier phase of IC backend development. The so-called integral design rules, accounting for all the major loading sources and history of the complete product creation process has to be used for the development of new generation semiconductors devices.

Influence of Delamination of Epoxy/Dielectric Interfaces on Pattern Shift and Passivation Cracking under Aeronautical Conditions

Interfacial delamination is a recognized failure mode in Integrated circuits (ICs). A major cause for this failure is the mismatch of Thermal Expansion Coefficients, Young’s modulus, and Poisson’s ratios of the package materials. Here, the influence of delamination between epoxy and dielectric layers on pattern shift and passivation cracking in IC package under aeronautical conditions, mainly temperature and load cycles, is studied by maximum plastic strain and maximum principal stresses theory using a certain 2D FEM model with different delamination length “L_c.right”. Delaminations are easy to introduce more dangerous impact to the package, because the IC microstructures endure serious thermo-mechanical loading under aeronautical working conditions. The method can be used to find the dangerous designed structure schedules and will provide a basis for selecting passivation materials of aeronautical IC packages.

Thermal Stress Distribution in the Corner of IC Package Structure

Passivation cracking is one of the main failures of Integrated circuits (ICs). A major cause for these failures is due to the mismatch of Coefficients of Thermal Expansion (CTE), Young’s modulus, Poisson’s ratios of package materials. In this paper, in order to analysis the stress distribution around the passivation layer corner, the finite element simulations and simplified analytical solutions are both applied. Then the comparison of stress values is made between the FEM result and simplified analytical solution, which shows that there is a good agreement. Based on these analyses, a conclusion can be drawn out that the simplified analytical model can be used to analyze the maximum stress around the passivation layer corner fast when design a chip preliminarily.

Passivation cracking analysis of integrated-circuit microstructures under aeronautical conditions

Passivation cracking is one of the main failures of integrated circuits (ICs). A major cause for these failures is the mismatch of thermal expansion coefficients, Young's modulus, and Poisson's ratios of the package materials. Here, the finite element simulations and the maximum principal stress theory are applied to investigate the effects of aeronautical conditions, mainly temperature and load cycles, on the local stress distribution in the passivation layers of IC microstructures. Passivation cracks are easy to initiate and to propagate because the aeronautical IC microstructures endure serious thermo-mechanical loading. The method also can be used to provide a basis for selecting passivation materials for aeronautical IC packages.