Pass Transistor Logic Research Articles

The design of non‐stacked and symmetric XOR for high‐speed applications

AbstractThe paper proposes an advanced exclusive‐OR (XOR) design using a non‐stacked symmetric structure based on complementary pass transistor logic (CPL) for high‐speed applications. The proposed XOR adopts a non‐stacked structure where a cascade structure is used for pull‐up/down paths instead of a cascoded structure, allowing the increase of pull‐up/down strength and thus faster output transitions. The CPL provides a symmetric scheme that further improves the bandwidth by eliminating the deterministic jitter generated from various input patterns. Verified in a 28‐nm CMOS process, the proposed XOR shows 17.2 times smaller data‐dependent jitter compared to the conventional XOR at the data rate near the limit bandwidth of the process.

An efficient GNRFET-based circuit design of ternary half-adder

Attaining low energy consumption in digital circuits design is a main task for designers because emerging applications are based on batteries and face limited-energy. Designing digital circuits with application to multiple-valued logic (MVL) and graphene nanoribbon field-effect transistor (GNRFET) provides a huge improvement in energy consumption. In this regard, this paper presents a novel ternary Half-Adder (THA) implemented with metal-oxide semiconductor (MOS)-type GNRFET. In the proposed THA, the Sum circuit is based on a combination of 3:1 ternary multiplexer, unary operators, and two supply voltages (dual-VDD), and the Carry circuit is based on unary operators, pass-transistor logic, and dual-VDD. The proposed THA is simulated using the 32-nm MOS-type GNRFET technology node at 0.9 V supply voltage in the HSPICE simulator. The proposed THA reduces the transistors count by 5.71–26.67% compared to the previously published THA circuits available in the literature, which are similar to the proposed THA from the design approach point of view. It is concluded from the simulation results that the proposed THA improves the power and energy consumptions by 83.33–91.41% and 66.38–82.27%, respectively. Moreover, the proposed THA is also designed and simulated using the Stanford 32-nm carbon nanotube field-effect transistor (CNTFET) technology. The proposed MOS-type GNRFET-based THA reduces the power and energy consumptions by 84.79% and 68.03%, respectively, and increases the delay by 2.12 × compared to its CNTFET-based counterpart. Moreover, the proposed CNTFET-based THA offers the second-lowest delay and power and the third-lowest energy compared to other existing CNTFET-based THA circuits.

Low power 10T phase and frequency detector for high frequency phase locked loop

AbstractThe high‐frequency circuits used in communication systems significantly depend on the functioning of the Phase‐Locked Loop (PLL). The power consumption is traded with the performance in the high‐frequency PLL. The proposed robust Phase and Frequency Detector (PFD) has multiple benefits of low‐power and reliable functioning at high frequency. The PFD highly contributes to the stable performance of the PLL, and this work proposes a 10T PFD for low‐power. The proposed PFD employs Gate Diffusion Input (GDI) logic based D‐flip flop and the pass transistor logic in the reset path to reduce power consumption. The PFD uses only 10 transistors, enabling a faster reset path and consuming less power at high frequencies. The 10T PFD was designed using 90 nm CMOS PDKs and simulated using CADENCE Specter for functional verification and performance analysis. The 10T PFD achieved a reset time of 61.4 ps at 3 GHz alongside a power consumption of 189.2 nW. Also, the overall power consumption of PLL using the proposed PFD at 3 GHz was demonstrating the effectiveness of 10T PFD over other conventional PFDs.

Novel design of power-efficient quaternary logic gates using CNTFET

ABSTRACT This paper presents novel power-efficient designs of quaternary logic gates like Quaternary Minimum (QMIN) and Quaternary Maximum (QMAX), Standard Quaternary Inverter (SQI), Standard Quaternary NAND (SQNAND), Standard Quaternary NOR (SQNOR) and Standard Quaternary XOR (SQXOR) using Carbon Nanotube Field Effect Transistor (CNTFET). The designs are based on Pass Transistor Logic (PTL) and use only three types of Carbon Nanotube (CNT) diameters 0.626 nm, 1.018 nm, and 2.27 nm, which lead to lower fabrication costs and enhanced manufacturability when compared to the state-of-the-art designs. The designs are simulated in HSPICE with a 32 nm CNTFET model provided by Stanford University, and the average power and maximum propagation delay obtained from the simulation results are compared with other existing designs. It shows that the proposed designs require 75% to 90% less power and they achieve 73% to 91% less Power Delay Product (PDP) than the latest designs.

Optimized reverse converters with multibit soft error correction support at 7nm technology

Residue number system (RNS) speeds up digital signal processing systems involving dominant addition and multiplication. Addition and multiplication are accelerated further and performed with a balanced performance on one-hot coded (OHC) residue digits. However, the high complexity of the RNS reverse converter (RC) may kill the performance gain. This paper proposes a high-speed and scalable RNS-RC for both regular and one-hot RNS. For redundant RNS (RRNS), an RRNS-RC is proposed, which based on majority-voting between OHC residue digits, corrects multibit soft errors occurring in a single residue channel. With pass-transistor logic and low-power FinFETs, the proposed RCs are optimized. The simulated RRNS-RC corrected 98.5% of soft errors, while consuming 7, 6.2 and 0.4% of the system's area, leakage power and dynamic power, respectively. As compared to the leading lookup table RC in the literature, RNS-RC exhibited 10.3X, 4.4X and 1.8X savings in area, average power, and delay, respectively.

Design of Hybrid Full Adder using 6T-XOR-Cell for High Speed Processor Designs Applications

Hybrid-logic implementation is highly suitable in the design of a full adder circuit to attain high-speed low-power consumption, which helps to design n any high speed ALUs that can be used in varies processors and applicable for high speed IoT- Application. XOR/XNOR-cell, Hybrid Full Adder (HFA) are the fundamental building block to perform any arithmetic operation. In this paper, different types of high-speed, low-power 6T-XOR/XNOR-cell designs are being proposed and simulated results are presented. The proposed HFA is simulated using a cadence virtuoso environment in a 45nm technology with supply voltage as 0.8V at 1GHz. The proposed HFA consumes a power of 1.555uw, and the delay is 36.692ns. Layout designs are drawn for both 6T-XOR/XNOR-cell, and 1- bit HFA designs. XOR/XNOR-cells are designed based on the combination of normal CMOS-inverter and Pass Transistor Logic (PTL). Which is used in the design of high end device processors such as ALU that can be implemented for the IoT- design applications?

Fast Complete Ternary Addition with Novel 3:1 T-Multiplexer

Background: Complete Ternary Adder is the prime building block for Ternary Carry Save Adder (TCSA) and acts as a critical deciding factor to optimize the overall speed-power performance for many complex ternary computing like ternary multiplications. Objective: This work proposes a new idea for high-speed complete Ternary Adder design with reduced Power-Delay-Product (PDP) using PTL (Pass Transistor Logic) based novel 3:1 Ternary Multiplexer (T-MUX) for efficient ternary computing. Materials: No external materials have been used in the present work. Methods: In the proposed approach, a novel 3:1 T-MUX with conventional E-MOS (Enhancementtype Metal Oxide Semiconductor) transistor is designed first. The Novel Select Unit (SU) and Control Unit (CU) are the prime building blocks of the proposed T-MUX circuit, which are discussed in detail. The 3:1 T-MUX is exploited next to achieve the proposed high-speed, low-PDP Ternary Half and Full Adder operation. The complete adder circuit is designed and optimized based on BSIM4 device parameters using 32nm standard CMOS technology with 1.0V supply rail at 27°C temperature. Trit values “0”, “1” and “2” are represented with 0V, 0.5V and 1.0V respectively. Extensive T-Spice simulation with all possible test patterns using PWL (Piece Wise Linear) input source validates the proposed circuit. The evaluated speed-power result of the proposed TFA is then compared with the most recent competitive study to set a benchmark. Results: The proposed complete TFA offers 68.9% and 82.5% reduction in propagation delay along with 27.7% and 31.6% Power-Delay-Product (PDP) reduction compared to the most recent competitive complete TFA Design-1 and Design-2, respectively. Discussion: As per the study, the proposed idea can be a good selection to produce fast ternary addition along with reduced Power-Delay-Product (PDP). Conclusion: The proposed complete TFA can be utilized effectively as Ternary Carry Save Adder (TCSA) for fast, low-PDP ternary multiplication as well as for other computation-intensive applications.

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders.

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder's potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

Design and Implementation of Enhanced Edge Triggered Flip-Flop for Low Power Dissipation

Power consumption in integrated circuits is one of the prominent aspects of the design methodologies that affect cost and efficiency. It holds a prominent role in the design and fabrication of Integrated Circuits (ICs). Power consumption in ICs increases largely due to clock diffusion techniques and Flip-Flops (FFs) since they consume a huge amount of power to carry out internal transitions. Various researchers have proposed different flip-flop circuit designs for reducing power consumption in clocking systems. When integrated circuits are operating at high frequency, the clock functions are usually managed using clocked transistors. The increased number of clocked transistors increases power consumption which is a major challenge. This research aims to minimize the power consumption in flip-flops by lowering the number of clock transistors. This paper presents the design of an enhanced Dual Edge Triggered Flip-Flop (2EdTFF) based on ultra-low-power robust pass-transistor logic (PTL) for power consumption reduction. The proposed PTL-based 2EdTFF is implemented and simulated. The results of the simulation analysis show that the transistor count and layout area are reduced for minimizing power consumption. The average power utilization of the proposed approach is 3.69 μW for a power activity of 50%, 25%, and 12.5%. The power utilization of the proposed approach is reduced by 12.6% compared to TGFF, 5.5%, and 6.6% compared to S-TCRFF and TCRFF. Comparative analysis shows that the proposed approach achieves better power reduction with better D-to-Q delay and Power-Delay-Product (PDP) performance.

Layout Design of Row Decoder using Cadence

Abstract: Logic circuits, data transport circuits, and analogue to digital conversions all frequently employ decoders. For the line decoders, a mixed logic design approach incorporating transmission gate logic, pass transistor logic, and complementary metaloxide semiconductor (CMOS) technology is employed to achieve the desired performance and operation. A unique topology is proposed for the 2 to 4 decoders, which calls for a topology with fourteen transistors to reduce operating power and transistor count and a topology with fifteen transistors to achieve high power and low delay performance. For a total of four new designs, standard and inverting decoders are created for each situation. All of the suggested decoders have a low transistor count in comparison to their traditional CMOS architectures. Last but not least, a number of suggested solutions demonstrate a notable improvement in operating power and propagation latency, exceeding CMOS in virtually all instances

Image processing with high-speed and low-energy approximate arithmetic circuit

Nowadays there are plenty of compute-intensive algorithms that are carried out at the edge. Therefore, it is necessary to design low-energy and high-speed circuits. Approximate computing (AC) is an emerging paradigm that can be used in error-resilient applications such as multimedia processing. In this paper, a novel approximate full adder design is proposed with the aim of latency and energy consumption reduction at the cost of producing some errors at the output. The proposed design uses pass transistor and transmission gate logic styles to achieve these aims. The proposed cell and referenced circuits are applied in a vast range of simulation conditions including power supply, ambient temperature, and load variations. Moreover, the constancy of the proposed cell concerning the process variations of carbon nanotubes (CNTs) is studied. All circuits are implemented at the transistor level using carbon nanotube field-effect transistor (CNFET) technology. Experimental results based on HSPICE simulation indicate the superiority of the proposed cell in terms of latency, power-delay product (PDP), and energy-delay product (EDP) criteria against state-of-the-art designs. Moreover, at the application level, image blending is used to study the accuracy metrics such as peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) quantitative metrics. Finally, the PDP, PSNR, and SSIM metrics are simultaneously taken into account as a figure of merit (FOM) to trade-off between circuit and application-level metrics. Quantitative results confirm the better functionality of the proposed approximate full adder cell compared to its counterparts.

High-Performance and Energy-Area Efficient Approximate Full Adder for Error Tolerant Applications

In this paper, a novel approximate Full Adder cell is presented which is based on the combination of standard CMOS logic (S-CMOS) and pass transistor logic (PTL) styles. The carbon nanotube field-effect transistor (CNFET) technology is used to simulate and implement the proposed cell. Comprehensive simulations at various power supplies, output loads, and ambient temperatures are conducted using the HSPICE tool. According to simulation results, its delay, power-delay product (PDP), energy-delay product (EDP), and normalized energy-delay-area product (NEDAP) improve by 18%, 10%, 39%, and 15% compared with the best existing design. The effects of diameter variations of carbon nanotubes (CNTs) on the functionality of the circuits are studied by Monte Carlo (MC) transient analysis. Simulation results confirm that the proposed cell is resistant to the process variations. At the application level, all circuits are employed in image blending to assess their efficacy in terms of peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) index criteria using the MATLAB tool.

Implementation of 1-bit Full Adder Circuit Using Pass Transistor Logic

Abstract: In this work, we have implemented 1-bit Full Adder Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high-speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The 1-bit Full Adder Circuit has been performed and obtained I-V characteristics and power for sum and carry were calculated. The effect of scaling on the overall performance is also analysed through the performance evaluation of 1-bit full adder circuit. Simulation results have been performed on LT Spice tool simulator at 1.8v single ended supply voltage and simulations are carried out to indicate the functionality of the proposed full adder circuit compared with conventional design to verify the effectiveness and it shows the circuit has low power dissipation at high speeds.

Implementation of 2-bit Multiplier Circuit Using Pass Transistor Logic

Abstract: In this paper, we implemented 2-bit Multiplier Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The proposed Multiplier circuit is implemented in 2x2 bit multiplier to achieve high speed, low area and less power dissipation. VLSI schematic tool and the analysis is done by using the LT Spice simulator. This paper aims at an optimization of power area and voltages of multiplier to show the better performance. The design is implemented in 0.18um CMOS technology and its functional parameters are compared and the best result is incorporated. Simulation results have been performed on LT Spice tool simulator at 1.8v and 2v supply voltage and simulations are carried out indicate the functionality of the proposed multiplier circuit compared with conventional design to verify the effectiveness and it shows the circuit has low power dissipation at high speeds.

Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design.

A low-voltage and low-power true single-phase flip-flop that minimum the total transistor count by using the pass transistor logic circuit scheme is proposed in this paper. Optimization measures lead to a new flip-flop design with better various performances such as speed, power, energy, and layout area. Based on post-layout simulation results using the TSMC CMOS 180 nm and 90 nm technologies, the proposed design achieves the conventional transmission-gate-based flip-flop design with a 53.6% reduction in power consumption and a 63.2% reduction in energy, with 12.5% input data switching activity. In order to further the performance parameters of the proposed design, a shift-register design has been realized. Experimental measurements at 0.5 V/0.5 MHz show that this proposed design reduces power consumption by 47.3% while achieving a layout area reduction of 30.5% compared to the conventional design.

Pass-Transistor Logic Circuits Based on Wafer-Scale 2D Semiconductors.

2D semiconductors, such as molybdenum disulfide (MoS2 ), have attracted tremendous attention in constructing advanced monolithic integrated circuits (ICs) for future flexible and energy-efficient electronics. However, the development of large-scale ICs based on 2D materials is still in its early stage, mainly due to the non-uniformity of the individual devices and little investigation of device and circuit-level optimization. Herein, a 4-inch high-quality monolayer MoS2 film is successfully synthesized, which is then used to fabricate top-gated (TG) MoS2 field-effect transistors with wafer-scale uniformity. Some basic circuits such as static random access memory and ring oscillators are examined. A pass-transistor logic configuration based on pseudo-NMOS is then employed to design more complex MoS2 logic circuits, which are successfully fabricated with proper logic functions tested. These preliminary integration efforts show the promising potential of wafer-scale 2D semiconductors for application in complex ICs.

Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques

Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and other similar applications. With the rising limits on latency, the design of faster multiplications is becoming increasingly important. Many changes are being done to improve speed. Vedic multipliers based on Vedic Mathematics are among them. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. CMOS (Complementary metal-oxide-semiconductor) designs take up more space and use more energy. Power dissipation causes an IC to heat up, which has a direct impact on its reliability and performance. Gate Diffusion Input (GDI) technology reduces the size, propagation delay, and power consumption of digital circuits while also lowering logic complexity as compared to traditional CMOS and existing pass transistor logic approaches. We compared a 2x2 Vedic multiplier based on the GDI and mGDI (Modified GDI) techniques in this study. In comparison to the GDI approach, the mGDI technology employs much less transistors. The Vedic multiplier is implemented in the cadence virtuoso tool, on 180nm and 90nm technology.

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

A new 1-bit full adder (FA) cell illustrating low-power, high-speed, and a small area is presented by a combination of transmission gate (TG), pass transistor logic (PTL), and float techniques. Using the proposed cell, a 4:2 compressor is implemented and its performance is investigated under diverse circumstances of voltage, temperature, and driving. The process and corners are evaluated through the process-voltage-temperature (PVT) variations and the Monte Carlo method (MCM), respectively. The accuracy and reliability of the proposed 4:2 compressor are confirmed carefully. Utilising the proposed FA and the compressor, an efficient 8-bit subtractor is implemented for bioimage processing, in particular for difference detection of images. A new mechanism is presented to improve the detection performance of digital signal processors (DSPs) by the addition and subtraction of two images for their difference. The quality of the resulted image confirms the efficiency of the proposed circuits and the method. The high performance of the circuits makes them a promising candidate for the next generation of integrated circuits (ICs) applicable to medical image processing.

A Novel Design of Full Adder Cell for VLSI Applications

The state-of-the-art digital integrated circuits (ICs) are becoming increasingly complex due to the increasing functionality along with high–performance and ultra-low power dissipation requirement. To meet the aforementioned requirement, a new low power and high performance 1-bit full adder cell is implemented based on gate diffusion input (GDI) and pass transistor logic (PTL) techniques. The delay, power, power delay product (PDP) and energy delay product (EDP) are extracted and compared for proposed full adder cell with other seven widely used full adders. The area is compared at 0.18 µm and 0.090 µm CMOS technology. The average power dissipation of proposed adder is 1.063 µW, C-CMOS is next higher value 1.377 µW and the NMNFA exhibits highest value 3.217 µW at a supply voltage of 1.2 V. The proposed adder reveals lower PDP (0.265 fJ) than the other adders. At all supply voltages proposed adder deliver low EDP value (0.070 fJ*nS) and it is minimum at 1.8 V because the delay is low at the same point which is dominating parameter in EDP. At supply voltage 1.2 V, the proposed adder exhibits improved performance EDP of 69.07% over the other best reported adder MBFA in this paper.

Design of Frequency Divider (FD/2 and FD 2/3) Circuits for a Phase Locked Loop

This paper reports on three design of Frequency Divider (FD/2) and Frequency Divider (FD 2/3) circuits. Tanner EDA tool developed on 130nm CMOS technology with a voltage supply of 1.3 V is used to build, model, and compare all circuits. For the FD/2 circuit, E-TSPC Pass Transistor logic uses 1.77 µW, whereas TSPC logic consumes 5.57 µW for the FD 2/3 circuit. It implies that the TSPC logic is the best solution since it meets the speed and power consumption requirements.