Partially-depleted Silicon-on-insulator Devices Research Articles

An Analytical Model for Weak Avalanche Induced Kink Effect of PDSOI nMOSFETs

Silicon-on-insulator (SOI) devices and circuits are widely used in semiconductor industry for its superior natures on integration density, isolations degree. Inefficient body contact of partially-depleted SOI (PDSOI) devices cannot evacuate excess carriers which transported from the weak avalanche multiplication of pinch-off region at high drain voltage bias. These accumulated carriers elevate the internal body potential and trigger electrical effects namely the body bias effect of threshold voltage and the turn-on of parasitic bipolar junction transistor (BJT). A comprehensive analytical model which include all these mechanisms are proposed to describe this kink effect. This model is constructed by an equivalent circuit and five strong nonlinearly coupled equations to describe the electrical behaviors. To solve these equations, a C <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$++$</tex-math> </inline-formula> Qt-based graphical interface software is developed for the parameter extraction of the model. The fixed point iteration algorithm are adopted for the solution of equations. The effectiveness and accuracy of this model are verified by the T-gate shaped PDSOI nMOSFETs of 130 nm manufacturing process node. It can predict the electrical behaviors of kink effect. This is meaningful for the circuit simulation of PDSOI platform.

Investigation of the Combined Effect of Total Ionizing Dose and Time-Dependent Dielectric Breakdown on PDSOI Devices.

The combined effect of total ionization dose (TID) and time-dependent dielectric breakdown (TDDB) of partially depleted silicon-on-insulator (PDSOI) NMOSFET is investigated. First, the effect of TDDB on the parameter degradation of the devices was investigated by accelerated stress tests. It is found that TDDB stress leads to a decrease in off-state current, a positive drift in threshold voltage, and a reduction of maximum transconductance. Next, the degradation patterns of TID effect on the devices are obtained. The results show that the parameter degradation due to gamma radiation is opposite to the TDDB stress. Finally, the combined effect of TID and TDDB is investigated. It is found that the drift of the devices’ sensitive parameters due to TDDB stress decreases in a total dose of gamma radiation environment. The TDDB lifetime is shortened, but the pattern of gate current change remains unchanged. The failure mechanism of the gate oxide layer under TDDB stress is not changed after irradiation.

Bias dependence of TID induced single transistor latch for 0.13 μm partially depleted SOI input/output NMOSFETs

In this work, single transistor latch effects induced by total dose irradiation for 0.13μm partially depleted silicon-on-insulator (PDSOI) n-type metal-oxide-semiconductor field effect transistors (NMOSFETs) were investigated. The front gate transfer characteristics under different bias configurations with forward and reverse gate voltage sweep are characterized to evaluate the latch phenomenon. The results indicate that transmission–gate (TG) bias is the worst case bias for total dose induced latch, and the onset drain voltage required for latchup degrades as the irradiation level increased. Experiments and 2D simulations are performed to analyze the positive trapped charge in the buried oxide (BOX) and its impact on the latch effect. It is demonstrated that the irradiation can enhance the impact ionization and thereby make the device more sensitive to latchup, especially at negative gate voltage. Moreover, the radiation induced coupling effect between the front gate and back gate can make the PDSOI devices in our experiments behave like the fully depleted (FD) ones.

Low frequency noise and radiation response in the partially depleted SOI MOSFETs with ion implanted buried oxide**Project supported by the National Natural Science Foundation of China (Grant Nos. 61204112 and 61204116).

Low frequency noise behaviors of partially depleted silicon-on-insulator (PDSOI) n-channel metal-oxide semiconductors (MOS) transistors with and without ion implantation into the buried oxide are investigated in this paper. Owing to ion implantation-induced electron traps in the buried oxide and back interface states, back gate threshold voltage increases from 44.48 V to 51.47 V and sub-threshold swing increases from 2.47 V/dec to 3.37 V/dec, while electron field effect mobility decreases from 475.44 cm2/V·s to 363.65 cm2/V·s. In addition, the magnitude of normalized low frequency noise also greatly increases, which indicates that the intrinsic electronic performances are degenerated after ion implantation processing. According to carrier number fluctuation theory, the extracted flat-band voltage noise power spectral densities in the PDSOI devices with and without ion implantation are equal to 7×10−10 V2·Hz−1 and 2.7×10−8 V2·Hz−1, respectively, while the extracted average trap density in the buried oxide increases from 1.42×1017 cm−3·eV−1 to 6.16×1018 cm−3·eV−1. Based on carrier mobility fluctuation theory, the extracted average Hooge’s parameter in these devices increases from 3.92×10−5 to 1.34×10−2 after ion implantation processing. Finally, radiation responses in the PDSOI devices are investigated. Owing to radiation-induced positive buried oxide trapped charges, back gate threshold voltage decreases with the increase of the total dose. After radiation reaches up to a total dose of 1 M·rad(si), the shifts of back gate threshold voltage in the SOI devices with and without ion implantation are −10.82 V and −31.84 V, respectively. The low frequency noise behaviors in these devices before and after radiation are also compared and discussed.

Output-Conductance Transition-Free Method for Improving the Radio-Frequency Linearity of Silicon-on-Insulator MOSFET Circuits

In this paper, a novel concept is introduced to improve the radio-frequency (RF) linearity of partially depleted (PD) silicon-on-insulator (SOI) MOSFET circuits. The transition due to the nonzero body resistance ( R \(_{\rm Body}\) ) in output conductance of PD SOI devices leads to linearity degradation. A relation for R \(_{\rm Body}\) is defined to eliminate the transition and a method to obtain transition-free (TF) circuit is shown. 3-D numerical analysis of body-contacted devices is carried out to extract the TF body resistances. To identify the output conductance TF concept and its application to RF circuits, a 2.4-GHz low-noise amplifier (LNA) is further analyzed. Mixed-mode device-circuit analysis is carried out to simultaneously solve device carrier transport equations and circuit SPICE models. Fast Fourier transform calculations on the output signal are performed to compute harmonic distortion figures. Comparing the conventional body-contacted (CBC) and TF SOI LNAs, third harmonic distortion and total harmonic distortion (THD) are improved by 16% and 24%, respectively. Two-tone test is used to analyze third-order intermodulation distortions. Third-order output intercept point is improved in TF SOI LNA by 17% comparing with that of the CBC SOI LNA. The results demonstrate superior advantage in application of TF design concept to SOI MOSFET circuits.

A New Method for Extracting the Radiation Induced Trapped Charge Density Along the STI Sidewall in the PDSOI NMOSFETs

The effects of the radiation-induced trapped charge in shallow trench isolation (STI) and buried oxide (BOX) on total ionizing radiation response of 0.13 μm partially-depleted silicon-on-insulator (PDSOI) NMOS technology are analyzed respectively. The positive trapped charge in the STI oxide, but not in the BOX, is responsible for the off-state leakage increase after ON bias radiation. A new method is proposed to calculate the surface charge density along the STI sidewall. This method takes into account the influences of the non-uniform electric field and the variable oxide thickness in the STI region. Moreover, the calculated non-uniform charge density along the STI sidewall is verified by three dimensional simulations. Even though there is charge-accumulation in the BOX, it shows minimal impact on the front-gate characteristics of the PDSOI devices in this 0.13 μm technology, except for the device with low body doping concentration. The positive charge trapped in BOX can induce significant threshold voltage shift in the RVT (regular Vth) I/O NMOSFET through coupling effect.

The Enhanced Role of Shallow-Trench Isolation in Ionizing Radiation Damage of 65 nm RF-CMOS on SOI

The mechanism for ionizing radiation damage in multi-finger SOI CMOS devices is presented for the first time. We analyzed the effects of shallow-trench isolation on ionizing radiation response of 65 nm Silicon-On-Insulator (SOI) CMOS technology. The radiation response of the CMOS devices was investigated using 63 MeV protons and 10 keV X-rays. The implications of proton irradiation and X-ray irradiation on the dc and RF performance of these devices are presented. The cut-off frequency is degraded due to post-irradiation degradation of device transconductance. Even though there is charge-accumulation in the buried-oxide, there is minimal impact on the front-gate characteristics of the partially-depleted SOI devices in this 65 nm CMOS technology. The implications of parasitic conduction along the STI on device design constraints, particularly for varying device width and number of gate fingers, are discussed in the context of high performance RF CMOS technology. These results suggest that body-contacting schemes which eliminate sidewalls (e.g., H-body, T-body) will provide the necessary total-dose radiation tolerance for multi-finger analog and RF devices, without additional hardening techniques.

The Characteristics and Control of Body-to-Body Leakage Current in PD-SOI

Body-to-body leakage (BBL) current in a partially depleted silicon-on-insulator (PD-SOI) device is increased significantly as polyspacing (PS) is reduced in technology scaling. We found out that the BBL has a great impact to Vt variation. We have demonstrated that the BBL can be minimized drastically by implant optimization. The dependence of the BBL on silicon film thickness, e-SiGe structure, and dopant diffusivity is also discussed in this paper. The layout effect of the BBL current in PD-SOI devices has been characterized with different PSs, device widths, and polylengths. Finally, we have demonstrated that the BBL current can be reduced below junction leakage level.

Using Direct-Tunneling Mechanism to Suppress Hysteresis Effect in Floating-Body Partially Depleted SOI Devices

Considering the direct-tunneling mechanism, the hysteresis effect in ultrathin gate-oxide floating-body partially depleted (PD) silicon-on-insulator (SOI) devices is investigated. For H-gate PD SOI, owing to the converse poly-gate beside the body terminal, the influence of the direct-tunneling mechanism on the floating-body potential can no longer be overlooked. Based on the measured results, for ultrathin gate-oxide H-gate PD SOI devices, the floating-body potential is dominated by the direct-tunneling mechanism and appears highly gate voltage-dependent. As compared to the amount of the accumulation tunneling charges, the variation between the generation and recombination processes that causes the hysteresis behavior can be ignored. Therefore, the hysteresis effect is suppressed.

Metastability of SOI CMOS latches

An analysis of the metastability of silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) latches is presented, using partially-depleted SOI devices with various body-connection topologies and an unbuffered latch. The metastability window, resolution time and time interval between the clock edge and the time t meta are evaluated as functions of power supply and the type of body-connection topology. Simulations using SOISPICE show improved metastability behaviour for SOI specific body-connection topologies.