Abstract
Body-to-body leakage (BBL) current in a partially depleted silicon-on-insulator (PD-SOI) device is increased significantly as polyspacing (PS) is reduced in technology scaling. We found out that the BBL has a great impact to Vt variation. We have demonstrated that the BBL can be minimized drastically by implant optimization. The dependence of the BBL on silicon film thickness, e-SiGe structure, and dopant diffusivity is also discussed in this paper. The layout effect of the BBL current in PD-SOI devices has been characterized with different PSs, device widths, and polylengths. Finally, we have demonstrated that the BBL current can be reduced below junction leakage level.
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