Partial Reconfiguration Of FPGA Research Articles

Dynamic Partial Reconfiguration for Adaptive Sensor Integration in Highly Flexible Manufacturing Systems

As new production system concepts emerge to face an increasing demand for individualized production, sensor integration for Industry 4.0 functions is becoming a major challenge. Flexibility- and scalability-focused concepts rely on reconfigurable machines that automatically replace smart end effectors between production steps. To ensure adaptability to future demands, these smart components, comprising the main tool and sensors, are connected to the static part of the machine via a unified electro-mechanical interface. In robot-based concepts, these components are furthermore space- and weight-constrained and should be cost-optimized. With respect to sensor integration, this leads to the challenge of interfacing sensors using different communication protocols and electrical signal properties through a fixed, minimal set of signal lines. In this paper, an architecture for an adaptive sensor integration unit is presented, targeting highly flexible production systems. Leveraging dynamic partial FPGA reconfiguration to exchange communication logic and an extensible hardware module located in the static part of the machine, it efficiently supports alternating communication protocols over static signal lines. It thereby reduces the number of signal lines as well as the need for protocol conversion units in the exchangeable components. A prototype implementation using industrial bus protocols shows its suitability and is evaluated concerning relevant timing characteristics and resource usage.

Online Self-testable Multi-core System using Dynamic Partial Reconfiguration of FPGA

<span>This paper presents a novel and efficient method of designing an online self-testable multi-core system. Testing of a Core Under Test (CoUT) in a massively multi-core system can be carried out while the system is operational, by assigning the functionality of the CoUT to one of the non-functioning/idle and pre-tested core. The methodology presented in this paper has been implemented taking a test setup by demonstrating the Dynamic Partial Reconfiguration (DPR) feature of latest FPGAs on Zynq-7 XC702 evaluation board. The simulation results obtained from the experimental setup show that the utilization of a multi-core system can be significantly improved by effectively utilizing the idle core(s) to back up CoUT(s) for on-line test without a significant hardware overhead and test latency.</span>

Energy efficient processing of motion estimation for embedded multimedia systems

Visual sensor networks require low power compression techniques of large amount of video data in each camera node due to the energy-constrained and bandwidth-limited environments. In this paper, energy-efficient architecture for Variable Block Size Motion Estimation is proposed to fully utilize dynamic partial reconfiguration capability of programmable hardware fabric in distributed embedded vision processing nodes. Partial reconfiguration of FPGA is exploited to support run-time reconfiguration of the proposed modular hardware architecture for motion estimation. According to the required search range, hardware reconfiguration is performed adaptively to reduce the hardware resources and power consumption. A reconfigurable ME ranging from simple 1-D to a complex 2-D Sum of Absolute Differences (SAD) array to perform full search block matching is selected in order to support different search window size. The implemented scalable SAD array can provide different resolutions and frame rates for real time applications with multiple reconfigurable regions.

Definition of an Architecture to Configure Artificial Neural Networks Topologies Using Partial Reconfiguraton in FPGA

Artificial Neural Networks (ANNs) competence in generalization and reconfigurable hardware using provide a solid base to developing critical embedded systems, capable of efficiently adapt itself as requirements change. Different level adaptation, from physical level up to system level, can be combined to provide efficient solutions using FPGA. So, this work aims to define a novel architecture to configure ANNs topologies using partial FPGA reconfiguration. NEURON block has been described using fixed-point notation and applying partial reconfiguration to load partial bitstreams of sigmoid and hiperbolic tangent functions, as well as dynamically inserting and removing NEURON blocks on the net, this way it is possible to configure MultiLayer Perceptron (MLP) networks with different topologies, using partial bitstreams in reconfigurable areas. It is conceived that, using this kind of hardware facilitates embedding applications using different topologies, MLP ANNs, easily reconfigurable on the field.

RUN TIME DYNAMIC PARTIAL RECONFIGURATION USING MICROBLAZE SOFT CORE PROCESSOR FOR DSP APPLICATIONS

DSP Application requires a fast computations & flex ibility of the design. Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. In this paper we are using mi croblaze soft core processor & ICAP Port to reconfi gure the FPGA at runtime. ICAP is accessed through a light-weight custom IP w hich requires bit stream length, go, and done signa l to interface to a system that provides partial bit stream data. The partial bit s tream is provided by the processor system by readin g the partial bit files from the compact flash card. Our targeted DSP application is matrix multiplication; we are reconfiguring design by changing partial modules at run time. To change the partial bit stream we in terfaces a microblaze Soft processor & using a UART interface.ISE13.1 & PlanAhead is used for partial reconfiguration of FP GA .EDK is used for microblaze soft processor desig n & ICAP Interface .The simulation is done using Chip Scope Logic Analyzer & the complete hardware implementation is done on X ilinx VIRTEX -6 ML605 Platform.

Customizing virtual networks with partial FPGA reconfiguration

Recent FPGA-based implementations of network virtualization represent a significant step forward in network performance and scalability. Although these systems have been shown to provide orders of magnitude higher performance than solutions using software-based routers, straightforward reconfiguration of hardware-based virtual networks over time is a challenge. In this paper, we present the implementation of a reconfigurable network virtualization substrate that combines several partially-reconfigurable hardware virtual routers with software virtual routers. The update of hardware-based virtual networks in our system is supported via real-time partial FPGA reconfiguration. Hardware virtual networks can be dynamically reconfigured in a fraction of a second without affecting other virtual networks operating in the same FPGA. A heuristic has been developed to allocate virtual networks with diverse bandwidth requirements and network characteristics on this heterogeneous virtualization substrate. Experimental results show that the reconfigurable virtual routers can forward packets at line rate. Partial reconfiguration allows for 20x faster hardware reconfiguration than a previous approach which migrated hardware virtual networks to software.

Internal Dynamic Partial Reconfiguration for Real Time Signal Processing on FPGA

Few FPGAs support creation of partially reconfigurable systems when compared to traditional systems based on total reconfiguration. This allows dynamic change of the functionalities hosted on the device when needed and while the rest of the system continues its working. Runtime partial reconfiguration of FPGA is an attractive feature which offers countless benefits across multiple industries. Xilinx has supported partial reconfiguration for many generations of devices. This can be taken advantage of substituting inactive parts of hardware systems and to adapt the complete chip a different requirement of an application. This paper describes an innovative implementation for real time audio and video processing using run time internal partial reconfiguration. System is implemented on Virtex-4 FPGA. Internal reconfiguration is handled using internal configuration access port (ICAP) driven by soft processor core. The considerable savings in device resources, bit stream size and configuration time is observed and tabulated in this paper.

Internal dynamic partial reconfiguration for real time signal processing on FPGA

Few FPGAs support creation of partially reconfigurable systems when compared to traditional systems based on total reconfiguration. This allows dynamic change of the functionalities hosted on the device when needed and while the rest of the system continues its working. Runtime partial reconfiguration of FPGA is an attractive feature which offers countless benefits across multiple industries. Xilinx has supported partial reconfiguration for many generations of devices. This can be taken advantage of substituting inactive parts of hardware systems and to adapt the complete chip a different requirement of an application. This paper describes an innovative implementation for real time audio and video processing using run time internal partial reconfiguration. System is implemented on Virtex-4 FPGA. Internal reconfiguration is handled using internal configuration access port (ICAP) driven by soft processor core. The considerable savings in device resources, bit stream size and configuration time is observed and tabulated in this paper.