Parasitic Voltage Research Articles

Application of DC distributed bus bar power systems on ships

Operation of vessels sailing along the Northern Sea Route is associated with numerous risks that determine increased requirements for the reliability of the propulsion system. In this regard, it is important to use ship electrical networks based on the distribution of direct current (DC) electricity, the operation of which provides a number of advantages in comparison with AC distribution systems. Conducting technical control of imported ship equipment due to the lack of information received from foreign manufacturers is an urgent need. Using the example of a propulsion electric plant with Azipod-type equipment, methods for assessing the technical condition of the propulsion electric motor, protecting the shaft from parasitic voltages and currents that can accelerate the destruction of bearings have been described. Methods for troubleshooting semiconductor elements included in the frequency converter have been considered. Probable errors in the operation of the nacelle position monitoring system have been presented. The possibilities of remote assessment of the technical condition of the system have been determined. The aim of the work is to develop stages of technical control and evaluation of the obtained parameters for the development of expert decisions on the operational reliability and prospects for further operation of equipment and elements in Azipod-type propulsion electric systems relevant on numerous vessels.

Probing hidden conduction mechanisms in diced silicon solar cells by low frequency noise analysis

Electrical low frequency noise (LFN) measurements are utilized in this work, in order to identify parasitic low voltage transport mechanisms in diced aluminum back surface field (Al-BSF) photovoltaic (PV) cells, which cannot be identified by I–V characterization. A detailed method of LFN analysis is proposed, taking into account the co-existence of various transport mechanisms, that typically occur in parallel in such devices. A precise examination of the 1/f noise level dependency with both current and voltage, combined with static I–V characterizations at various temperatures, enabled the identification of two flicker noise sources appearing at different current regions: one attributed to local linear shunt mechanisms and a second one to a fluctuation in a nonlinear parasitic conductivity localized at the samples’ edges. The latter source exhibits noise signatures resembling either tunneling or Poole-Frenkel transport, while excluding Shockley-Read-Hall recombination processes. This hypothesis was further verified by measurements of thermal activation energies typical of tunnel and Poole-Frenkel conduction mechanisms.

Failure Scenario of Power Supply Due to Conducted Electric Pulse From E1 HEMP

This article presents the effects of a high amplitude conducted electromagnetic pulse on the electrical behavior of a flyback switch-mode power supply. The electromagnetic pulse is generated by a current injection platform that is able to reproduce differential or common mode parasitic currents and voltages induced by the coupling between E1 high-altitude nuclear electromagnetic pulse and a global electrical network. In this article, injections are performed in differential mode until the destruction of power supply. Current and voltage measurements have been performed around each destroyed component during the injection. Finally, these destruction tests, associated with spice simulations and component analyses, permit to build a power supply destruction scenario with the component's failures chronology modeling. This scenario is the first step in order to model the susceptibility of power supplies during an electrical pulse injection.

A New Modulation for Leakage Current Reduction of Modular Multilevel Converter

Leakage current is an important problem in non-isolated inverters, especially implemented in a medium- and high-voltage system. First, several analyses had carried out to reduce the high-frequency component of common-mode voltage (CMV) and the leakage current of a three-phase modular multilevel converter (MMC). Then, a new modulation method is proposed to keep CMV as the half of dc voltage and suppress the leakage current effectively. The peak value of leakage current can be suppressed under 5 mA, which complies with the VDE-0126-1-1 standard. Meanwhile, the parasitic capacitor voltage can be balanced automatically without the additional capacitor voltage control. Finally, the proposed scheme is verified in MATLAB/Simulink and tested on the hardware-in-loop platform. The effectiveness of the proposed scheme is verified by the experiment results.

A Comparative Study of High Temperature Tensile and Creep Testing Between Standard and Miniature Specimens: Applicability and Limits

This study concerns the quasi-static and time-dependent mechanical behavior obtained via the miniaturized electro-thermal mechanical testing (ETMT) approach for single crystal (SX) and conventional cast Mar-M-247 superalloy. The experimental outcome was benchmarked against standardized testing procedures. It is found that tensile yielding behavior can be captured accurately by the ETMT approach up to 1100 ^{circ }C, provided the appropriate type of thermocouple (T/C) is chosen. Furthermore, creep rupture behavior is underestimated by the miniaturized set-up. High repeatability of the rupture time was obtained for the SX case, whereas a significant scatter was observed for the conventional cast case. The discrepancies are assessed in detail; discussion centers around analytical and practical considerations, such as temperature uncertainty due to parasitic voltage and the choice of T/C, microstructural change as a result of the Joule heating, representative gauge volume, and strain rate non-linearity. Consequently, the applicability and limits of the miniaturized approach are examined critically, and improvements were suggested where appropriate.

RF Josephson Arbitrary Waveform Synthesizer With Integrated Superconducting Diplexers

We present the design and characterization of a broadband RF Josephson arbitrary waveform synthesizer (RF-JAWS) with a series array of 4500 Josephson junctions (JJs) and integrated low-pass/high-pass five-pole superconducting diplexers. The integrated diplexers enable broadband filtering of the feedthrough signal components in the drive-current pulses with decade-wide instantaneous bandwidth. The diplexers have at least 30 GHz passband with less than 0.8 dB insertion loss. The JJ array is driven with a delta-sigma pulse sequence that encodes 10 kHz and 1.005 GHz tones, and generates an open-circuit voltage of 22 mV rms (−26.18 dBm available power assuming a 50 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathrm{\Omega }$</tex-math></inline-formula> Thevenin equivalent source) at 1.005 GHz—a 25% increase compared to the state of the art. The drive current pulses undergo a three-step equalization to compensate for the linear distortion of the room-temperature electronics, the on-chip diplexers, and the remaining on- and off-chip components. The measured parasitic feedthrough voltages at 1.005 GHz are around −33 dBc, and their effect on the quantum locking ranges (QLRs) is quantified by measurements. The results demonstrated in this article show a significant step toward a broadband, integrated, quantum-based microwave voltage source with useful power above −30 dBm.

High-k field plate DeNMOS design for enhanced performance and electrothermal SOA in switching applications

This paper investigates high-k dielectric field plate (FP) application to optimize the capacitance and avalanche behavior of conventional drain extended NMOS (C_DeNMOS) for enhanced performance and electrothermal safe operating area (SOA) in transient switching applications. Two configurations of high-k dielectric DeNMOS have been investigated: 1) Planar and 2) Trench. Doping of FP is changed from N+ to P+ in Planar, while shallow trench isolation (STI) is placed below the N+ doped FP in the Trench structure to limit surface charge accumulation in comparison to C_DeNMOS. We demonstrate that efficient reduced-surface-field (RESURF) action of high-k dielectric improves the shielding against high lateral fields, enhancing electrical and electrothermal SOA. Furthermore, for electrothermal SOA analysis, unclamped inductive switching (UIS) simulations have been performed, and it is shown that high parasitic BJT trigger voltage (Vt1) and second breakdown current (It2) enable safe turn-off of the device under high current transient conditions.

A High-Efficiency Dynamic Inverter Dead-Time Adjustment Method Based on an Improved GaN HEMTs Switching Model

Benefited from the fast switching speed, Gallium nitride (GaN) high electron mobility transistors (HEMTs) have been widely used in high switching frequency converters. However, due to the significant correlation between the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> time and operating conditions (more than 20 times difference of the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> time between the high load current and small load current for GaN HEMTs), using a fixed dead time will introduce extra dead-time (DT) losses in inverters where the output voltage and current are constantly varying. Therefore, this article proposes a high-efficiency adaptive method to dynamically adjust the GaN-inverter DT with operating conditions. An improved transient model including the parasitic inductance and output voltage with bidirectional solution flow has been proposed for GaN HEMTs to increase the accuracy of DT adjustment. Based on this model, the dynamic DT adjustment can be realized without extra sensors for GaN-inverters. Using the dynamic DT adjustment, the experimental results show a peak efficiency of 98.25% in a 1200 W inverter with triangular current mode modulation. Compared with using the fixed DT, the dynamic DT method can reduce the power loss by 26.7% under full load and 49.14% under light load.

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

A novel level shifter (LS) circuit that uses a new low-power approach based on a parasitic capacitance voltage controlled current source is presented to minimize the propagation delay (PD) and maximize the voltage conversion range. This new scheme uses a simplified circuit including a dependent current source, a composite transistor made of three interconnected n-channel MOSFETs (TnM), one CMOS input inverter, and one CMOS output buffer to provide a fast response time. The circuit utilizes the combined action of the equivalent parasitic capacitance of the TnM, the value of which changes dynamically according to the transient value of the input voltage, and the dependent current source to shift the input signal level up from subthreshold voltage levels to +3.0 V, with minimal delay and power consumption. The LS circuit fabricated in 0.35 μm CMOS technology occupies a silicon area of only 25 μm×25 μm. The LS shows measured rising and falling PDs of, respectively, 4 and 11.2 ns. The measured results show that the presented circuit outperforms other solutions over a wide frequency range of 1 to 130 MHz. The fabricated circuit consumes a static power 31.5 pW and a dynamic power of 3.4 pJ per transition at 1 kHz, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDL</sub> =0.8 V, and a capacitive load of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> =0.1 pF.

Power Delivery Design, Signal Routing, and Performance of On-Chip Cobalt Interconnects in Advanced Technology Nodes

We assess the performance impact of cobalt interconnect metallization for both signal routing and power delivery in advanced logic technologies with a minimum metal pitch of 32 nm or less. While cobalt interconnects may enable lower line resistance in narrow signal lines than industry-standard copper interconnects below a threshold pitch, there is still a significant performance penalty associated with using cobalt in wide lines, including both signal and power. For wide signal lines at minimum-pitch metallization levels, we find a delay penalty as much as 60&#x0025;&#x2013;100&#x0025; depending on signal run length for Co interconnects. For wide power lines at minimum-pitch metallization levels, we find a parasitic voltage (IR) drop penalty as high as 50&#x0025; for Co interconnects. In light of these performance disadvantages, we discuss several design strategies to minimize the impact of Co metallization for both signal routing and power delivery. We also highlight critical differences between low-power and high-performance design points for power delivery.

Analysis and mitigation of parasitic resistance effects for analog in-memory neural network acceleration

To support the increasing demands for efficient deep neural network processing, accelerators based on analog in-memory computation of matrix multiplication have recently gained significant attention for reducing the energy of neural network inference. However, analog processing within memory arrays must contend with the issue of parasitic voltage drops across the metal interconnects, which distort the results of the computation and limit the array size. This work analyzes how parasitic resistance affects the end-to-end inference accuracy of state-of-the-art convolutional neural networks, and comprehensively studies how various design decisions at the device, circuit, architecture, and algorithm levels affect the system’s sensitivity to parasitic resistance effects. A set of guidelines are provided for how to design analog accelerator hardware that is intrinsically robust to parasitic resistance, without any explicit compensation or re-training of the network parameters.

Geometrical considerations to discern the transverse spin Nernst effect in an all-metallic permalloy/platinum bilayer system

Most spin caloritronics research utilizes thin films on substrates with an in-plane heat flow, where an unintended out-of-plane thermal gradient may develop by heat dissipation through the substrate. In systems exploiting metallic ferromagnets to generate or detect spin currents, such out-of-plane thermal gradients might confuse the signal via undesirable thermomagnetic effects, such as the anomalous Nernst effect. Here, we report direct measurement of the spin current created by the spin Nernst effect in platinum, using ferromagnetic metal contacts as spin accumulation detectors. By comparing the voltage measured transverse and longitudinal to the thermal gradient, we find that the device geometry is crucial in all-metallic systems. Exploiting the orthogonality in the angular dependence on the external magnetic field of the transversely measured voltage, we quantitatively separate the spin Nernst signal from the parasitic anomalous Nernst voltage, which are of the same order of magnitude. As a result, we estimate the spin Nernst angle of platinum to be comparable to the spin Hall angle in magnitude with an opposite sign.

Endurance-Aware Mapping of Spiking Neural Networks to Neuromorphic Hardware

Neuromorphic computing systems are embracing memristors to implement high density and low power synaptic storage as crossbar arrays in hardware. These systems are energy efficient in executing Spiking Neural Networks (SNNs). We observe that long bitlines and wordlines in a memristive crossbar are a major source of parasitic voltage drops, which create current asymmetry. Through circuit simulations, we show the significant endurance variation that results from this asymmetry. Therefore, if the critical memristors (ones with lower endurance) are overutilized, they may lead to a reduction of the crossbar's lifetime. We propose eSpine, a novel technique to improve lifetime by incorporating the endurance variation within each crossbar in mapping machine learning workloads, ensuring that synapses with higher activation are always implemented on memristors with higher endurance, and vice versa. eSpine works in two steps. First, it uses the Kernighan-Lin Graph Partitioning algorithm to partition a workload into clusters of neurons and synapses, where each cluster can fit in a crossbar. Second, it uses an instance of Particle Swarm Optimization (PSO) to map clusters to tiles, where the placement of synapses of a cluster to memristors of a crossbar is performed by analyzing their activation within the workload. We evaluate eSpine for a state-of-the-art neuromorphic hardware model with phase-change memory (PCM)-based memristors. Using 10 SNN workloads, we demonstrate a significant improvement in the effective lifetime.

Application of Perovskite Layer to Rotor for Enhanced Stator-Rotor Capacitance for PMSM Shaft Voltage Reduction

Adjustable speed drives use Pulse Width Modulation (PWM) to switch DC-bus voltage for the synthesis of three-phase voltages to provide power to the permanent magnet synchronous motor (PMSM). This switching action produces very short rise and fall times and Common Mode Voltage (CMV) in the motor winding, exciting the parasitic capacitances inherent to the motor geometry. These parasitic capacitances give rise to shaft voltage due to a voltage divider action. Therefore, in this paper, first, motor parasitic capacitances and voltage divider action is explained. Second, the Barium Titanate (BTO) layer is coated onto the rotor to enhance stator-to-rotor compound capacitance and a simulation is performed showing the dependence of the shaft voltage on the permittivity of the perovskite (BTO) layer. The rotor BTO layer reduces the bearing voltage ratio as well. Third, experimental results are presented showing effectiveness of the application of the BTO layer to rotor and reduction of shaft voltage of the motor in anticipation to mitigate the damaging electric discharge machining (EDM) bearing currents. Likewise, the experiment shows that the magnetic design of the motor is not affected by the BTO layer to rotor.

Crosstalk Analysis and Suppression of GaN Driving Circuit in Bridge Converter

Enhancement mode Gallium-Nitride power transistors (GaN HEMT) have emerged as promising devices for high frequency, high efficiency and high power density switch m ode power supplies. However, when GaN device works in high frequency, the dv/dt and di/dt slopes are increased due to stray inductances and parasitic capacitances, which leads to oscillations and overshoots in gate-source voltage and affect the stability of driving circuits. Especially in the phase-bridge circuit, the crosstalk between the upper and lower switch seriously limits the performance of the device. In order to solve the short circuit problem of bridge arms generated by oscillation and crosstalk, an improved design of gate driving circuit was proposed, which could eliminate the parasitic oscillation and voltage spikes, suppress crosstalk and higher harmonics effectively. In addition, A double pulse test prototype is built and the simulation and experimental results verify the effectiveness of this driving circuit.

Modeling of a Current Injection System for Susceptibility Study

This article deals with the model of a high current injection system associated with its electrical generation–transformation–distribution chain able to reproduce differential or common-mode parasitic currents and voltages induced by the coupling between a nuclear electromagnetic pulse radiation on a global electrical network. Due to the quite complexity of the current injection system, the chosen modeling approach was to use the well-known equivalent Thevenin generator. Because of several hundreds of amperes and volts of current and/or voltage generated and their relatively large spectral occupancy of some tens of megahertz, the measurement of currents and voltages needed to build the model, were carried out with adequate sensors and equipment. Once the model built, the generators have been integrated into Spice circuit simulation tool in order to predict the differential and the common- mode currents and voltages induced at the input of switch-mode power supplies and, for later studies, at some different nodes.

Investigation of the electrical limit conditions effects in piezoelectric transducer arrays utilized in medical imaging

Crosstalk is considered as an undesirable phenomenon disturbing the electromechanical behavior of the ultrasonic transducer arrays used in medical imaging applications. Indeed, when one element of a transducer array is excited, it generates parasitic voltages and/or displacement fields on the adjacent passive elements. Consequently, these interactions between elements decrease the array’s electroacoustic performance, which affects the obtained image quality. To overcome the crosstalk’s problem, several research works propose active cancellation techniques. In this case, the correction voltages are determined by considering the array’s elements grounded, contrary to the conventional crosstalk’s definition which considers the array elements in Open-Circuit. The novelty of this paper is in one hand the study of the electrical limit conditions’ effects on the physical behavior of a piezoelectric transducer array radiating in a fluid medium (water). On the other hand, a displacement method is proposed to evaluate the crosstalk level when the array elements are grounded. The limitations of the proposed method are also discussed. For this purpose, a piezoelectric transducer array is firstly modeled using a Two-dimensional Finite Elements Method (FEM), when the array elements are not grounded (open-circuit). Then, the results are compared to those obtained when the neighboring elements are grounded (as in the case of the crosstalk’s active cancellation techniques). Finally, measurements are realized on a fabricated transducer array vibrating in air medium and are successfully compared to the results predicted using FEM.

Ground Leakage Current Caused by Common-Mode Voltage of PWM inverter

In railway tractive vehicles, three-phase PWM (Pulse Width Modulation) inverters generate parasitic Differential-Mode Voltages (DMV) and Common-Mode Voltages (CMV). Parasitic voltages are a side effect of using the width modulation to shape the phase-to-phase inverter’s voltage. In this article, the authors present a mathematical description of the DM and CM voltages and carry out their spectral analysis. Based on the spectral harmonics analysis, the authors present a method for filtration of harmonics of DM and CM voltages aimed at limiting the capacitance parasitic currents: due to DM voltage – phase-to-phase parasitic current and CM voltage – ground parasitic currents. As the final result of the tests, almost complete elimination of leakage parasitic current form PE shock protection system was achieved.

An Improved Active Crosstalk Suppression Method for High-Speed SiC MOSFETs

Silicon carbide (SiC) power electronic devices feature the advantages of fast switching speed, low conduction loss, and reliable operation in high temperature environment, etc. Due to the differences of parasitic parameters and threshold voltage between SiC mosfet s and Si mosfet s, crosstalk problem is easy to be triggered when SiC mosfet s are applied to bridge topologies. In this paper, the crosstalk effect with different parasitic parameters of SiC mosfet s is firstly analyzed, and then an improved active crosstalk suppression method for high-speed SiC mosfet s is proposed. By using the proposed method, when the crosstalk occurs, the crosstalk voltage will be decreased by reducing the equivalent gate resistance and increasing the equivalent gate-source capacitance in an active way. Consequently, the crosstalk problem can be suppressed without affecting the switching speed. To verify the effectiveness of the proposed method, a prototype of a buck–boost converter is built and the proposed modified gate driver is applied to the half-bridge topology. Comparative experimental study is conducted and the crosstalk voltage is analyzed. The experimental results verify that effective crosstalk suppression is achieved.

Generalized DC loop current attack against the KLJN secure key exchange scheme

A new attack against the Kirchhoff Law Johnson Noise (KLJN) secure key distribution system is studied with unknown parasitic DC voltage sources at both Alices and Bobs ends. This paper is the generalization of our earlier investigation with a single end parasitic source. Under the assumption that Eve does not know the values of the parasitic sources, a new attack, utilizing the current generated by the parasitic dc voltage sources, is introduced. The attack is mathematically analyzed and demonstrated by computer simulations. Simple defense methods against the attack are shown. The earlier defense method based solely on the comparison of current/voltage data at Alice's and Bob's terminals is useless here since the wire currents and voltages are equal at both ends. However, the more expensive version of the earlier defense method, which is based on in situ system simulation and comparison with measurements, works efficiently.