Parasitic Components Research Articles

Inductive Coupler Analysis Based on Scattering Parameters With Nonstandard Terminal Impedance

A higher frequency helps to design a compact wireless power transfer system. Due to the parasitic effects and component nonlinearity, the increased frequency would depreciate the accuracy of the circuit model (CM). The scattering parameters (SPs) are powerful to avoid this issue and helpful to study the efficiency and voltage gain. However, the existing SP-based analysis would fail when the nonstandard terminal impedance is used. This article explores the limitation of the original SP-based analysis and, then, proposes a modified one with the help of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\bm{ABCD}$</tex-math></inline-formula> and impedance matrices. For a system with a clear model, the modified SP-based analysis can get exactly the same results as the CM-based one in terms of calculation. In the experiment, a 1-MHz inductive power transfer system is built to show the benefit of the SP-based analysis with increased model uncertainty. Compared to the CM-based one, the largest error reduction is 17% for the efficiency and 8% for the voltage gain.

Noise-Tolerant LLC Synchronous Rectification Using Volt-Second Product

Synchronous rectification (SR) technologies for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LLC$ </tex-math></inline-formula> resonant converters are essential to high-power, low-voltage battery chargers considering the excessive current stress on the rectifiers. Mainstream SR controllers employ an adaptive approach that measures the drain–source voltage during the SR turn-on phase ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$v_{\text {ds.on}}$ </tex-math></inline-formula> ). However, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$v_{\text {ds.on}}$ </tex-math></inline-formula> is low-magnitude and sensitive to the voltage across parasitic inductors and capacitors. The distortion of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$v_{\text {ds.on}}$ </tex-math></inline-formula> causes SR mistriggering, undermining the efficiency. This article proposes a noise-tolerant SR strategy based on the volt-second product (VSP) of SR drain–source voltage in the turn-off phase and rectifier current conduction time. The proposed method determines SR ON-time using high-magnitude voltage signals, which are tolerant of parasitic effects. In steady-state operation, the VSP method reduces the SR ON-time error caused by circuit parasitic components, whereas in transient operation, the algorithm dynamically adjusts SR ON-time to maintain a safe operation margin, preventing rectifier reverse current flow. Details of the implementation and timing sequence are provided to demonstrate the simplicity and effectiveness of the VSP SR algorithm. Experimental results show that compared with conventional adaptive SR, the proposed VSP SR decreases the ON-time error by 64% in the above-resonance operation and removes the reverse current in the below-resonance operation, which reduces the total loss by 3%.

Optimal Design of Solid State Transformer-Based Interlink Converter for Hybrid AC/DC Micro-Grid Applications

The conventional low-frequency transformer (LFT) in conjunction with power electronic converters is used as the conscientious device to provide galvanic isolation and voltage regulation for the hybrid micro-grid (HMG) applications. However, it may not be suitable for HMG applications where the high power density and active power flow control over a wide operating range are major concerns. This article presents the solid state transformer (SST)-based interlink converter (IC) used to provide high frequency (HF) galvanic isolation between the ac/dc micro-grid (MG) networks. The proposed structure of SST intends to meet out most of the aspects of HMG networks such as active control over the bidirectional power flow, high efficiency, high power density, and better voltage regulation. In SST, nonoptimal parasitic components of HF transformer (HFT) are used as a part of power transfer elements and are unable to assist soft-switching operation over the wide range of load variations that degrade its overall performance. In view of these concerns, the comprehensive design and analysis are carried out at different stages to decide the design constraints for the optimization of nonoptimal magnetizing components and their significant effect on the system performance. Furthermore, the influence of the system parameters is analyzed with analytical expression and graphical analysis. The proposed SST configuration is designed for minimum kVA rating and better voltage regulation at different buses by using the proposed dual degree control (DDC) scheme over the wide range of load variations. The 4-kW hardware prototype is built up in the laboratory which provides isolated dc dual-port output terminals. The design and testing are carried out under different loading conditions to validate the significant performance of the proposed SST structure.

A Load-Independent Output Current Method for Wireless Power Transfer Systems with Optimal Parameter Tuning

In current study, a method for achieving a load-independent output current with the ability to optimize the parameter tuning, which is applied to wireless power transfer (WPT) systems, is analyzed. The proposed technique is based on the immittance property in a passive resonant network (PRN) with the purpose of transforming a voltage/current resource into a current/voltage resource. This study determines an immittance conditions-qualified family of PRN, which is associated with a more appropriate topological description in WPT applications. Considering the resource and sink type, a comprehensive specification of the coupling coefficient-based design condition and operating point is carried out. Moreover, the parameters of each proposed topology are reconfigured by adjusting the proportion of active power to reactive power ratios as an index to optimize the topology size as well as a reduction of voltage/current stresses on their elements without changing the specified system-level parameters, such as the loosely coupled transformer operating frequency, and specified constant current outputs. The sample topology selection is also carried out with respect to the absorption of the parasitic components and achieving the inherent dc-blocked transformer. Zero-voltage-switching (ZVS) operation of the switches, minimum conduction losses of the rectifier diodes within an extensive variety of load variations, and capability of consistent generation of stable load-regulated current are also achieved. Analytical results show that the proposed compensation has the minimum output current fluctuation versus variations of the coupling coefficient and other parameters. Finally, the effectiveness of the proposed methodology is evaluated through simulations, and practical experiments, and compared with the conventional design method.

Parameter Extraction Technique for Evaluation of Inductive and Capacitive Elements of Three-Winding Coupled Inductor

Wide-bandgap devices have enabled miniaturization of magnetic components to enhance the power density of the converter. However, parasitic components become dominant at higher switching frequencies that actuate unwanted electromagnetic interference issues. Therefore, it is critical to model and evaluate them in compact magnetic structures. Since multiwinding coupled inductive structures are essential part of multiphase converters, this article introduces a measurement method to compute the parasitic elements of a three-winding coupled inductor. Results of the proposed method are verified by measuring the high-frequency emissions of the high-step-up converter with two inductor structures. Both inductors had similar inductances but different physical dimensions. With application of the proposed measurement methodology, parasitic capacitances of both inductors were computed. Results showed that one inductor structure has higher parasitic capacitance than the other. Since high-frequency emissions of the converter directly depend on the parasitic capacitance of the inductor structure, the emission profile of the converter showed that the converter indeed had lower noise peaks when the inductor with lower capacitance was employed. Hence, these results validate the capacitance trend as predicted by the proposed modeling technique. This method can be employed to any multiwinding coupled inductor to compute its parasitics to optimize the required electromagnetic interference filters.

Three-Phase Integrated-Optimized Power Electronic Transformer for Electric Vehicle Charging Infrastructure

This article proposes the high-frequency link three-phase integrated-optimized power electronic transformer (PET) for electric vehicle (EV) charging infrastructure in the distribution network. The structural elements and configuration of PET significantly affect its design and performance. However, the different topologies of PET available in the literature did not consider the influence of the circuit’s structural elements with their parasitic components. Consequently, it violates the value of control variables which fails to accomplish essential control characteristics required for EV charging infrastructure in the smart distribution network. Therefore, in this article, detailed modeling and analysis of the proposed PET are carried out at each stage by incorporating its structural effect to analyze the circuit behavior during different operating conditions. As a result, it provides the design and operating constraints for the proposed PET, employed in the design procedure and control algorithm. Furthermore, the dual-degree control (DDC) method is proposed to utilize the structural framework and dual control variables of the proposed PET to meet out significant aspects of EV charging infrastructure in the distribution network such as wide range of voltage regulation, active control over the power flow, and soft-switching operation. Finally, a 4-kW prototype of the proposed PET is built up, which has a bidirectional power flow feature and isolated dc dual-port output terminals. Hardware testing and experimental results verify the effectiveness of the proposed PET based on the DDC method.

Ultrafast Solid-State Circuit Breaker With a Modular Active Injection Circuit

This article proposes a new modular active injection circuit (AIC) for solid-state circuit breakers (SSCB). The modular AIC is used to achieve soft switching turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> during dc current interruption to mitigate the effects of the parasitic components in the main branch. The proposed AIC presents the following contributions: selectable resonant currents are achieved to obtain a reliable artificial zero-crossing point in dc currents; current rating scalability is provided; passive components of the AIC are optimized using particle swarm optimization (PSO) algorithm and new proposed objective functions; an external wireless charger is developed to charge the injection capacitor of the AIC to provide voltage isolation, compactness, and flexibility in choosing the precharge voltage value on the injection capacitor; the proposed AIC needs no discharge circuits, which simplifies the control and accelerates reclosing process. The proposed SSCB is simulated in a 6-kV system in power systems computer aided design/electromagnetic transients for dc (PSCAD/EMTDC) in interrupting currents of normal and different scenarios. The designed SSCB can interrupt the dc currents up to 200 A with the adaptive response time from 3.74 to 6.71 μs, faster response time in interrupting higher values of dc currents. The effectiveness of the proposed SSCB in practice is validated by experiments of a downsize 380 V/20 A prototype with only 2.8 μs response time and 99.91% efficiency.

Design and Development of Microstrip Antenna for Wireless Applications

The plan of microstrip Antenna with conservative size is recommended for remote correspondence. the microstrip recieving wire is a minimized variety of customary microstrip radio wire. The electromagnetically coupled feed from the lower layer is utilized to energize the proposed recieving wire. The full recurrence of the proposed recieving wire is lower than that of the customary microstrip recieving wire of same actual size. The addition of the recieving wire can be expanded by utilizing a parasitic component over the fundamental radiator and fixed with the spacer of ideal level. The reenactment investigation of different boundaries of the planned recieving wire is finished in Advance Design System electromagnetic EM test system.

Linear Response Modeling of High Luminous Flux Phosphor-Coated White LEDs for VLC

The widespread deployment of LEDs for illumination purposes has open the door to the use of these devices for visible light communications (VLC). Most lighting fixtures are mounted with phosphor-based white LEDs, and a driver connected to the LED is also required for VLC. This paper shows that the parasitic effects introduced by this setup change the frequency response of the intrinsic LED. A linear model to characterize the whole setup is proposed, as well as a methodology to extract its parameters. This methodology allows the designer to characterize the frequency response of LEDs without the additional difficulty of knowing the specific parasitic components introduced by the setup. The proposed model offers an accurate estimation of the slope of the LED frequency response in order to broaden the frequency range in which the model is useful to characterize and simulate VLC links. This was corroborated with the characterization of three commercial white LEDs whose measured and modeled frequency responses matched perfectly.

Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC

Power supply noise (PSN) in central processing unit (CPU) cores or any integrated circuit (IC) chips is a problem of power line voltage degradation impelled due to the parasitic components (viz., resistance, capacitance, and inductance) across the packaging. This lowers the operating frequency of the silicon chip during high volume manufacturing and thereby, affects the overall performance. After numerous attempts to minimize the parasitic impacts of power delivery networks (PDNs) in IC packages, researchers also started to look for circuital configurations that can curb down the coefficients of PSN (i.e., the instantaneous current <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$i(t)$ </tex-math></inline-formula> and the current ramp <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$[({di(t)})/{dt}]$ </tex-math></inline-formula> during OFF to ON switching of packaged CPU/IC). Though variable frequency clock (VFC) has emerged as a potential solution, its design is found to be complex and power hungry. Hence, a novel and simple configuration of VFC embedded with leakage control transistor-based clock gating (LCT-CG) is tendered in this article, where the pertaining circuits and integrated system have been designed using UMC 65 nm CMOS with a supply of 1.1 V. The performance of the design is tested on master-slave flip-flop (MSFF) and a few prominent benchmark circuits (viz., ISCAS’89 s27, s820, s832, s1196, s9234 and ITC’99 b02 and an IEEE 754 complaint single precision FPU) considering the PDN of existing CPU OLGA package. The system-level validation of our proposed IC on A-Z80 CPU chip offers the average power and PSN to be mitigated by 30.06% and 42.63% against the conventional clocking.

Design Methodology and Technological Flow of Screen-Printed Thick-Film Sensors

In this paper, the design considerations and basic equations related to thick-film screen-printed sensing devices are included. The geometry of the device and the patterns of the functional sensing film, or of the electrodes are taken into account for the determination of the operational frequency, noise voltage, quality factor and other key parameters, related to the proper work of the resistive, capacitive and surface acoustic wave based sensors. The determination of some parasitic components and possible errors is also provided. The focus is put on the most widely spread coating patterns related to this technology &#x2013; meander and comb-shaped. The technology flow chart of the screen-printing technology is given and the approaches for fine-tuning the resistance at the thick-film resistive sensors are discussed. Comparison of the typically used materials for substrates, resistive, conductive, and dielectric coatings is made. Criteria for the selection of the different pastes or inks for specific applications are mentioned.

Identification Method of Parasitic Components in a Power Loop on PCBs using a VNA Port Extension

Identification Method of Parasitic Components in a Power Loop on PCBs using a VNA Port Extension

Generation of cosecant squared pattern from linear array of active and parasitic dipole antennas

ABSTRACT This work uses the active and parasitic components in a linear antenna array composed of parallel dipoles to synthesize a cosecant squared pattern using the Quantum Particle Swarm Optimization approach. This pattern is obtained by the mechanical displacement of the parasitic array of the parallel dipole placed in front of an active dipole array. In addition to it, mutual coupling between the antenna elements is considered in this process. Two examples are presented to visualize the effect of this approach in the synthesis process. Moreover, obtained results from the simulation are also validated by the results produced from FEKO software.

A Novel GaN-Based Metal-2DEG-Metal Varactor With Cutoff Frequency of 3.13 THz

A novel metal-2DEG-metal (M-2DEG-M) varactor based on GaN high electron mobility transistor (HEMT) structures was designed and investigated. The novel varactor employed metal-2DEG direct contacts to form two back-to-back Schottky junctions, eliminating the threshold voltage and showing a strong nonlinear <i>CV</i> behavior at zero bias, which was more beneficial to terahertz (THz) multiplier circuits design compared with the conventional metal&#x2013;semiconductor&#x2013;metal (MSM) 2DEG varactors. The metal-2DEG direct contacts reduced the junction capacitance and the series resistance simultaneously. For the M-2DEG-M varactor with an electrode length of <inline-formula> <tex-math notation="LaTeX">$1 \mu \text{m}$ </tex-math></inline-formula>, the device capacitance at zero bias was determined to be 3.0 fF (without de-embedding the parasitic component), with the series resistance of <inline-formula> <tex-math notation="LaTeX">$25.4 \Omega $ </tex-math></inline-formula>, resulting in a record high cutoff frequency of 2.09 THz for GaN-based varactors. After de-embedding the parasitic pad-to-pad capacitance, the cutoff frequency and figure of merit (FOM) would be 3.13 and 7.14 THz, respectively. Additionally, the whole fabrication process of the novel varactor only needed two steps of ordinary UV lithography without elaborate nanoscale T-gates, totally compatible with GaN-based HEMT process.

A Bridgeless Isolated Half-Bridge Converter Based EV Charger With Power Factor Preregulation

Conventional full-bridge and half-bridge (HB) converters are quite popular for front-end power factor preregulation (PFP) in electric vehicle (EV) battery chargers. Discontinuous conduction mode (DCM) operation at high power causes increased oscillation in the circuit. These oscillations increase with parasitic components of circuit. During deep DCM operation, these oscillations are seen to be significant and contribute to harmonic content in the input current. Therefore, a PFP bridgeless isolated HB converter based EV charger with reduced <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> oscillation in DCM is presented in this article. To reduce <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> oscillation, two diodes are used in series with minimum number of magnetic components. The design of proposed charger in DCM is illustrated to facilitate uniform battery current during constant current/constant voltage charging. The inherent advantage of reduced conduction loss with bridgeless topology is achieved. The performance of this isolated HB converter based charger is shown for improved oscillation characteristics and power quality operation at steady state and over a range of varying input voltages.

Noise and Conversion Analyses for High-T c Superconducting Harmonic Mixers: Theoretical Modeling and Experimental Verification

High- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> superconducting (HTS) harmonic mixers are attractive frontends for terahertz wireless communication and sensing applications. However, the investigation of HTS harmonic mixers has long been hindered by the lack of effective theoretical method in device modeling. This article presents a modeling approach for analyzing the noise and conversion properties of HTS harmonic mixers. By quantitively analyzing the contribution of the parasitic components to frequency conversion, a parasitics-selection based equivalent circuit model is built with the architecture complexity reduced to a six-port network. Besides, a fast hybrid-solution method that combines the single-tone current excitation and perturbation-derivation processing techniques, is developed for efficiently calculating the conversion impedance matrix for harmonic mixing. Detailed derivations are then carried out to acquire the semianalytic expressions of noise temperature and conversion gain after solving the noise correlation matrix for harmonic mixing. The presented modeling method has been verified by the fourth harmonic mixing experiments for a dual-band antenna-coupled HTS Josephson-junction mixer module. The measured and simulated results are in good agreement in terms of the noise temperature and conversion gain as well as their dependance on dc biasing, local oscillator pumping, and operating temperatures. The results have validated the effectiveness of the presented modeling method for analyzing the properties of HTS Josephson junction mixers.

Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator

A nonvolatile lookup table (NV-LUT) circuit, which is a key component of a field-programmable gate array, is proposed for an energy-efficient yet high-performance binarized convolutional neural network (BCNN) accelerator. Since the active load is distributed to each configuration memory cell, the effect of the parasitic components is greatly reduced. Moreover, the use of a wired-OR logic-circuit style makes it possible to perform a high-speed logic operation. The proposed 6-input NV-LUT circuit using an active-load-localized single-ended circuit style is designed using a 45 nm CMOS technology and the delay is reduced by 30% with only 13% of hardware overhead compared to those of a conventional NV-LUT circuit. It is also demonstrated that the proposed NV-LUT circuit exhibits variation resilience against three process corners. The use of the proposed NV-LUT circuit also makes it possible to reduce 47% of the energy consumption of a BCNN accelerator for digit recognition compared to that of a conventional SRAM-LUT-based implementation.

A Parallel Resonant Converter Polynomial Model Implemented in a Digital Signal Controller

Due to their exceptional performance in coping with large variations in output voltage and current, parallel resonant converters (PRC) are commonly used in high-voltage applications. The incorporation of step-up transformer parasitic components as part of a power topology, on the right duty and a suitable switching frequency, determines the high efficiency and wide variety of applications with PRC. Switching losses are reduced in the same topology by tracking and running on the optimum mode for each power and voltage by a set frequency and duty. The PRC’s static model behaviors, under optimum operating circumstances, are illustrated. The equivalent polynomial model is used to quickly compute the switching frequency and duty cycle required to achieve the converter’s desired output voltage and power. The polynomial model is simple and easy to implement in any form of a digital signal controller (DSC). Normalized parameters are used to widen the operational range and generalize the model. This also offers the essential protection against current and voltage spikes. The work in progress depicts the specific procedures involved in developing a polynomial model. The normalized equations provide a graphical description of the static model, from which the graphical representation of the polynomial are derived. Hence, polynomial equations are obtained. This paper describes the PRC static model, how to convert it to a polynomial model, how to validate it with MATLAB-Simulink, how to program F28335 using Simulink, and how to use it in practice.

Maximum power extraction of hybrid photovoltaic ‐battery system with nonisolated single‐input and dual‐output DC‐DC converter: An efficient RFAMAO approach

The DC-DC converter is more significant for the integration of photovoltaic (PV) and battery. The design of the power converter is high complexity, because of the nonlinear characteristics, like supply voltage variations, switches, load current variations, and parasitic component fluctuation. This article proposes an efficient approach for increasing the maximum power of PV system and system efficiency. The proposed approach is the consolidation of Random Forest Algorithm (RFA) and Mexican Axolotl Optimization (MAO), hence it is called RFAMAO approach. The proposed approach utilized the single-input and dual-output boost converter to implement the maximum power point tracking of the system that improves the lesser voltage input power source, controllable higher voltage direct current bus and middle voltage output terminals. RFA is used to deal with the uncertainty caused by climate change. MAO is utilized to tune the control parameter of the system. The voltage-mode controlling strategy among the PV, battery, and standalone DC load depending on Digital Signal Processing and Control Engineering (DSPACE) is utilized for uninterruptible power flow management and constant DC load voltage maintenance. The proposed approach is implemented in MATLAB/Simulink, and its efficiency is compared with existing approaches. The oscillation around maximum power point (MPP) for case 1 of RFAMAO, modified shuffled frog leaping algorithm with fuzzy logic (MSFLA-FLC), fuzzy logic, and perturb and observe (P&O) is 2.69, 7.31, 20.54, and 29.12 W. The oscillation around MPP for case 2 of RFAMAO, MSFLA-FLC, fuzzy logic, and P&O is 2.57, 8.34, 18.56, and 27.65 W.

Design and Simulation of Normally Off High‐Electron‐Mobility Light‐Emitting Transistor

Herein, a built‐in normally off GaN‐based high‐electron‐mobility light‐emitting transistor is designed and simulated. The proposed structure can significantly minimize the device area, eliminate the parasitic component introduced by metal interconnectors, ensure a fail‐safe operation owing to its normally off operating condition, and it affords fabrication simplicity, a preferable quality for display applications. Using 2D computer‐aided design software (Silvaco's TCAD), the device's electrical and optical features are investigated, revealing good output power linearity and light intensity control by the gate voltage.