Parasitic Capacitive Coupling Research Articles

Parasitic Capacitive Couplings in Medium Voltage Power Electronic Systems: An Overview

Recent development within the field of medium voltage wide-bandgap semiconductor devices are drawing the attention from both researchers and industries, due to the demanding requirements for more efficient high-power energy conversion. The rapid development has entailed an increased awareness of the negative impact of increased rate of change in voltage, d vd t, and its derived issues caused by the inevitable parasitic capacitive couplings. This paper is dedicated to present an overview of the parasitic capacitive couplings in high-power medium voltage power electronic converter systems, using an example reference system enabled by medium voltage SiC MOSFETs. The definitions of capacitive couplings are presented and the impacts raised by parasitic capacitive couplings are reviewed. In addition, the similarities of different capacitive couplings introduced by components in practical medium voltage systems are presented and summarized. Lastly, the challenges and future work with respect to parasitic capacitive couplings in medium voltage power electronics converter systems are shared from the authors' perspective.

Brushless DC Motor Common-mode Voltage Analysis

Brushless DC motors (BLDCMs) with their own performance of obvious advantages: good speed regulation performance and high efficiency. BLDCMs have continuously replaced brushed DC and induction motors in many competitive fields and obtained more extensive applications. The common-mode voltage (CMV) in the motor parasitic capacitance coupling in the motor shaft induces the shaft voltage. It then triggers the shaft current, resulting in electrical corrosion of the bearing. It is necessary to conduct a systematic scientific analysis of its CMV. For different modulation methods, the phase voltages under three conditions without PWM modulation, HPWM_LPWM modulation, and HPWM_LON modulation are studied, FFT, and then the CMV is analyzed. Then, the correctness of the analysis is verified by simulation analysis.

In Depth Parasitic Capacitance Analysis on GaN-HEMTs with Recessed MIS Gate

In this study, parasitic coupling capacitance behavior on GaN devices with recessed MIS-gate is analysed in depth by combining experimental data, 2D-simulations, analytical calculations, and TEM imaging. This enabled to highlight the second channel formation. A new analytical model to determine the contribution of the active channel and the different coupling parasitic capacitances from a gate-to-channel capacitance Cgc curve of a GaN MIS-HEMT is proposed. This also enables the evaluation of the respective contribu-tions of all components such as the passivation layer and gate field plate capacitances in the parasitic ca-pacitance and effective gate length evaluation of GaN devices with recessed MIS gate, which could be useful for reliable parameter extraction, device modeling and optimization.

An Intra-Body Power Transfer System With 1-mW Power Delivered to the Load and 3.3-V DC Output at 160-cm of on-Body Distance.

This paper presents an intra-body power transfer (IBPT) system that can deliver power greater than 1 mW across an on-body distance of 160 cm. A system simulation model is built for the characterization of the channel and optimization of the power transfer. Our system analysis and experimental validation demonstrate that 1 MHz is an optimal carrier frequency for IBPT in terms of power delivered to the load (PDL) and power efficiency (PE). Prototype TX and RX boards were built, and an IC was fabricated in a 180-nm CMOS process for the RX. The proposed RX IC consists of a voltage doubler (VD) and a charge pump (CP) to obtain a sufficiently high voltage conversion ratio (VCR). Among various rectifier topologies, the VD is the optimal topology for the power receiver front-end because the parasitic ground coupling capacitances, which inevitably exist in the IBPT system, act as an inherent input-coupling capacitance for the VD. The implemented VD utilizes a dynamic VTH compensation (DVC) for its diode components. Compared to the conventional static VTH compensation (SVC), DVC in the VD reduces the reverse leakage current of the diode, thus maximizing the power conversion efficiency (PCE) and VCR. In addition, the PDL is enhanced by inserting an inductor on the TX board. It reduces the backward-path impedance without increasing the RX volume, boosting the PDL by up to 9.9 times compared to the PDL without the inductor insertion. The proposed IBPT system delivers up to 178.8 μW of power at 11.7% of maximum power efficiency with 3.3-V DC output voltage and even 1.385 mW of power with the inductor insertion, supporting various biomedical wearable sensors, such as ECG sensor modules.

Influence of external parameters on RF inductive discharge plasma characteristics

Systematic experimental studies of the electron density and temperature, the efficiency of RF power coupling to the RF inductive discharge plasma have been carried out in the pressure range of helium, neon, argon, and krypton 0.1–133 Pa, at an RF generator power of 100–500 W and frequencies of 2, 4 and 13.56 MHz. It is shown that the electron density reaches a maximum, and the temperature reaches a minimum in the pressure range 1.33–13.3 Pa. Taking into account the presence of a parasitic capacitive coupling between the inductor and the plasma, which forms the capacitive channel of RF power input, makes it possible to conclude that the maximum values of the electron density were observed at the pressure at which the power input through the inductive channel is maximal. At pressures of the order of 0.133 Pa and below, an increase in the electron temperature is observed in the peripheral part of the discharge. Numerical modeling by the PIC method shows that one of the reasons is the formation of a directed azimuthal motion of electrons in the region of the skin layer. As the pressure increases, a transition occurs from the nonlocal to the local electron kinetics, which is reflected in the ratio between the electron temperature in the peripheral and central parts of the discharge.

Choosing the Optimal Power Coils Using Open-Source k-Oriented Design Automation.

Wireless power coils have found important use in implantable medical devices for safe and reliable wireless power transfer. Designing coils for each specific application is a complex process with many interdependent design variables; determining the most optimal design parameters for each pair is challenging and time-consuming. In this paper, we develop an automated design method for planar square-spiral coils that generates the idealized design parameters for maximum power transfer efficiency according to the input design requirements. Computational complexity is first reduced by isolating the inductive coupling coefficient, k, from other design parameters. A simplified but accurate equivalent circuit model is then developed, where skin effect, proximity effect, and parasitic capacitive coupling are iteratively considered. The proposed method is implemented in an open-source software which accounts for the input fabrication limitations and application specific requirements. The accuracy of the estimated power transfer efficiency is validated via finite element method simulation. Using the presented approach, the coil design process is fully automated and can be done in few minutes.

Total Gain Recovery in Floating Gate Thin-Film Transistors for Neuromorphic and Edge Computing

We propose a floating-gate (FG) thin-film transistor architecture which alleviates a significant limitation present since the inception of FG field-effect transistors, namely the loss of gain due to parasitic capacitive coupling on the FG [1].The interest in large area electronics has grown beyond traditional applications, such as display and sensing arrays, with recent trends including neuromorphic and edge computing. However, the challenges of fabricating robust thin film transistor (TFT) circuits have remained despite the many significant achievements in material systems and process development. In order to realise the full benefit of low-cost, high-throughput manufacturing methods, device shortcomings need to be addressed [2]. In FG devices, specifically, one major limitation is the degradation of gain compared to conventional devices, as a result of capacitive coupling of the channel and drain potentials to the floating gate. The problem is far more severe in contact-controlled TFTs, such as the staggered-electrode, high-gain source-gated transistor (SGT) [3, 4], and crippling in conventional TFTs manufactured in materials such as InGaZnO [5].SGT operation differs from conventional field-effect TFTs, whereby the semiconductor is fully depleted at the source edge by an energy barrier (e.g. Schottky), which is reverse biased by the application of drain voltage. Charge injection is modulated via the gate/source overlap, producing very low saturation voltage and ultra-low output conductance gd [3]. This latter feature yields the distinctive and extremely high intrinsic gain observed in such devices. A large voltage drop occurs across the source depletion region, producing the notable early saturation and, consequently, the channel potential is maintained at a value close to the drain potential for operating conditions in which a conventional TFT would still be working in the linear region. As such, when a floating gate is used in a SGT, the FG couples strongly to both the drain and the channel. FG potential varies considerably with drain voltage, thus increasing charge injection along the source, ultimately raising gd . While gd is still orders of magnitude lower than that of a TFT or FG TFT (see Figure 1), many analog applications would benefit from a solution to this problem [1].Here, we present a staggered-electrode contact-controlled device, the multimodal transistor (MMT), which shares SGT charge injection principles, however the switching mechanism of its channel is controlled by a separate gate [6]. In a FG MMT, the source gate responsible for charge injection and channel switching gate are designed as FGs (FG1 and FG2, respectively) and a main control gate (CG) may overlap both FGs. FG MMTs have been fabricated in low T°C technology [6] with Ni source and drain contacts. ICP-CVD (Inductively Coupled Plasma Chemical Vapour Deposition) via the Corial 210D reactor was used to deposit µ-Si as active layer, as well as the insulators of the gate stack (Figure 1a). Temperature never exceeded 250°C in any of the processing steps.The MMT exhibits the same high-gain properties of the SGT and preserves it even in FG configuration. With the channel and drain potentials coupling to FG2, its potential is raised significantly higher than FG1 (see Figures 1b and 1c for TCAD simulation with Silvaco Atlas), which is effectively shielded. As charge injection is exclusively modulated by FG1, the low saturation and extremely low gd are maintained, in contrast to the FG SGT (see Figure 1c). Thus, extremely high gain can be obtained from the FG MMT structure, with a wide range of applicability to traditional analog applications such as displays and sensors, as well as emerging neuromorphic circuits.Figure. 1 a) Photomicrograph of a µ-Si floating gate MMT (FG MMT); b) FG2 potential is significantly raised, while FG1 is shielded from parasitic capacitive coupling from the channel and drain potential, keeping charge injection at the source constant with drain voltage. c) Output conductance gd comparison confirms FG MMT gd is significantly lower than that of the equivalent FG SGT.

The Completed Probabilistic Modelling of Nanometer MIFGMOSFET

A completed model of the probabilistic distribution of the drain current’s random variation of the nanometer multiple input floating gate MOSFET (MIFGMOSFET) is proposed in this work. The modelling process has taken the dominant physical level causes of the drain current’s variations into account. Unlike its predecessor, the proposed model considers both N-type and P-type nanometer MIFGMOSFET. Moreover, the formerly neglected parasitic coupling capacitances have also been taken into account. The obtained modelling results, which are based on the derived drain current’s equations of nanometer MIFGMOSFET, are very accurate. They can predict the probabilistic distributions of the candidate N-type and P-type nanometer MIFGMOSFETs obtained by using Monte-Carlo simulations with 99% confidence and higher accuracy than that of the previous work. We also perform a comparative robustness study of the nanometer MIFGMOSFET of both types and demonstrate various interesting applications of our modelling results

Microwave engineering for semiconductor quantum dots in a cQED architecture

We develop an engineered microwave environment for coupling high Q superconducting resonators to quantum dots using a multilayer fabrication stack for dot control wiring. Analytical and numerical models are presented, which show that high resonator quality factors can be attained by either minimizing the parasitic coupling capacitance to the leads or creating a low effective environmental impedance at the cavity frequency. We implement the later approach by fabricating low characteristic impedance (Zg≈10 Ω) microstrips on-chip for the dot bias wiring and show resonator quality factors of 8140 that can be attained without the addition of explicit filtering. Using this approach, we demonstrate single electron occupation in double and triple dots detected via dipole or quadrupole coupling to a superconducting resonator. Additionally, by using multilayer fabrication, we are able to improve ground plane integrity and keep microwave crosstalk below −20 dB out to 18 GHz while maintaining high wire density, which will be necessary for future circuit quantum electrodynamics quantum dot processors.

High-Precision Incremental Capacitive Angle Encoder Developed by Micro Fabrication Technology

This article proposes a high-precision incremental capacitive angle encoder based on microfabrication technology. Compared to traditional printed circuit board technology, the encoder manufactured by microfabrication technology has higher processing accuracy and better temperature characteristics. Further, the microfabrication technology makes the encoder obtain larger sensitive capacitances and achieve more electrical cycle divisions within a smaller volume. To overcome the effect of the parasitic parameters led by microfabrication technology, electric models were established and analyzed, and the solution was proposed. First, to reduce the parasitic capacitance coupling to the ground, the process materials and fabrication steps are improved and optimized. Then, a differential structure on excitation voltage wires is adopted to minimize the nonlinear error on the measurement results. In addition, the collection electrode interconnection model is optimized to reduce parasitic parameters on the collection and enhance the signal to noise ratio. Both analytical calculation and finite-element analysis results verified the feasibility of the improvement and optimization. Finally, the optimized prototype is fabricated and measured, and the result shows that the prototype can achieve 0.0002° measurement resolution and 0.0012° measurement accuracy within a 58 mm diameter.

Parasitic Capacitances, Inductive Coupling, and High-Frequency Behavior of AMR Sensors

Anisotropic Magneto-Resistive (AMR) sensors are popular in sensitive applications, especially in planar on-chip integrated form which implies the presence of several on-chip capacitive and inductive parasitic elements. However, there is a lack of equivalent circuit models capturing these parasitics and allowing the modeling of sensors' behavior at higher frequencies or in stability-sensitive closed-loop operation. This work fills this gap in the literature by introducing a high-frequency equivalent circuit model, for planar on-chip AMR sensors with integrated offset and Set/Reset coils, capturing the main capacitive and inductive parasitic elements. A general methodology for estimating the values of the parasitic elements via a set of measurements is presented and it is applied to a particular commercial AMR sensor. Using the introduced circuit model, the transfer function from the offset coil voltage to the output voltage of the sensor, via the parasitic capacitive coupling path, is derived. The transfer function from the S/R coil voltage to the offset coil voltage is also derived. Both are used to create a system-level model of the AMR sensor which can be used in system-level analysis to help the designer predict and optimize the open or the closed-loop sensor circuit system behavior. The introduced high-frequency equivalent circuit model and the two related transfer functions have been verified experimentally using the component values derived from the examined commercial AMR sensor.

Common-Mode Stability Test and Design Guidelines for a Transformer-Based Push-Pull Power Amplifier

We report design guidelines for a transformer-based push-pull power amplifier (PA) with a systematic stability test carried out in the complex frequency domain. By detecting the right half-plane zeros of the impedance matrix's determinant, the common-mode (CM) instability in a differential PA were accurately estimated with the established frequencies from the analysis. In the stability test, the parasitic series coupling capacitance of the input transformer and the parasitic inductance from the gate (base) biasing line were identified as the two primary mechanisms of the CM instability in a transformer-based PA contingent on stability. Based on the analysis of the instability mechanisms, useful stabilization methods were proposed and discussed for a robust push-pull PA design with a well-balanced performance. An onboard transformer-based push-pull PA was implemented for the verification purpose, and the effects of parasitic inductance on the stability had been investigated. The simulated and measured results corresponded well with the proposed analysis.

Investigate and Reduce Capacitive Couplings in a Flyback Adapter With a DC-Bus Filter to Reduce EMI

In consumer electronics, high power density power adapters are designed to minimize the adapter size. As a result, the components are getting very close and the near-field coupling issue tends to be severe. This compromises the performance of electromagnetic interference filters, especially at high frequencies. This article investigates near-field capacitive couplings and the reduction techniques in a high power-density power adapter with a dc-bus filter. The parasitic capacitive coupling theory is developed and parasitic coupling capacitances are experimentally extracted. The common-mode (CM) noise model with parasitic capacitive couplings is developed and the techniques to reduce the CM noise due to parasitic capacitive couplings are explored. Simulation and experiments were conducted to verify the analysis and the proposed techniques.

Neighbor-A-Posteriori Information Assisted Cell-State Adaptive Detector for NAND Flash Memory

Cell-to-Cell interferences (CCIs), which arise from adjacent cells through parasitic coupling-capacitance, severely degrade the performance of threshold voltage detection. Pre-processing and post-processing methods have been proposed to mitigate the effect of CCIs on threshold voltage variation. The performance of the aforementioned methods heavily depends on the accuracy of the threshold voltages adjacent to the victim cells. However, to obtain high accuracy, these methods requires multi-sensing operations, thus significantly resulting in high detection latency. In this letter, a novel non-uniform detection scheme based on the threshold voltage of cell states, which is referred to as the cell-state adaptive detection (CSAD), is proposed to adapt the shifts of the threshold voltages. Then, the neighbor-a-posteriori information is exploited to mitigate the overcompensation phenomenon and further improve the performance of the CSAD under the block read mode scenario. Simulation results show that the proposed CSAD scheme and its improved version not only achieve better bit-error-rate performance but also keep lower detection latency compared with the existing detection schemes.

Plasma parameters in a twin-chamber RF inductive plasma source, placed in a weak external magnetic field

Experimental study of the plasma parameters in an RF inductive plasma source consisting of gas-discharge chamber and process chamber (GDC and PC) located in the magnetic field with inductance less than 70 Gs was carried out. The magnetic field was close to uniform in the PC and divergent in the GDC. The metal or dielectric flange was used as a separating element between GDC and PC. Experiments showed that an increase in the magnetic field at the pressures when the electron mean free path exceeds the longitudinal size of the plasma source and utilization of the operating frequencies of more than 2 MHz led to the formation of radially limited plasma column, which ended at the bottom grounded flange of PC. In this case, the plasma density in the PC became higher than in the GDC. In the area of the metal separation flange, there was a local minimum of the electron density as well as plasma potential, associated with the parasitic capacitive coupling between the antenna and the separating flange. The growth of the magnetic field led to the equalization of the axial potential distribution.At the operating frequency of 2 MHz, at the pressures at which the electron mean free path is less than the longitudinal size of the plasma source, the electron density as well as the space potential reaches a maximum in the GDC and, as a rule, decreases monotonously toward the PC.

Effect of TLP rise time on ESD failure modes of collector-base junction of SiGe heterojunction bipolar transistors

Electrostatic discharge behavior of integrated SiGe heterojunction bipolar transistors is investigated by transmission line pulse (TLP) and transient interferometric mapping techniques. When stressing collector - base junction in reverse direction, two distinct non-thermal failure modes, depending on TLP pulse rise time (RT), have been found: For RT ≥ 10 ns the observed failure at a critical voltage is attributed to base corner breakdown as supported by failure analysis. For RT ≤ 5 ns the failure occurs due to parasitic capacitance coupling which virtually short-circuits the base-emitter junction at the pulse beginning and thus induces a parasitic bipolar action.

Lab-On-A-Chip Device for Yeast Cell Characterization in Low-Conductivity Media Combining Cytometry and Bio-Impedance.

This paper proposes a simple approach to optimize the operating frequency band of a lab-on-a-chip based on bio-impedance cytometry for a single cell. It mainly concerns applications in low-conductivity media. Bio-impedance allows for the characterization of low cell concentration or single cells by providing an electrical signature. Thus, it may be necessary to perform impedance measurements up to several tens of megahertz in order to extract the internal cell signature. In the case of single cells, characterization is performed in a very small volume down to 1 pL. At the same time, measured impedances increase from tens of kilo-ohms for physiological liquids up to several mega-ohms for low conductivity media. This is, for example, the case for water analysis. At frequencies above hundreds of kilohertz, parasitic effects, such as coupling capacitances, can prevail over the impedance of the sample and completely short-circuit measurements. To optimize the sensor under these conditions, a complete model of a cytometry device was developed, including parasitic coupling capacitances of the sensor to take into account all the impedances. It appears that it is possible to increase the pass band by optimizing track geometries and placement without changing the sensing area. This assumption was obtained by measuring and comparing electrical properties of yeast cells in a low-conductivity medium (tap water). Decreased coupling capacitance by a factor higher than 10 was obtained compared with a previous non-optimized sensor, which allowed for the impedance measurement of all electrical properties of cells as small as yeast cells in a low-conductivity medium.

Extending accurate spectral induced polarization measurements into the kHz range: modelling and removal of errors from interactions between the parasitic capacitive coupling and the sample holder

SUMMARY Spectral induced polarization (SIP), describing the measurement of the frequency domain electrical impedance magnitude and phase of porous materials, has been widely used to characterize subsurface hydrological/biogeochemical properties and processes. SIP data collected at frequencies higher than 100 Hz are expected to describe the polarization of small particles providing insights into the physicochemical properties of clays, nanoparticles and microorganisms. However, the phase measurements at these high frequencies are often contaminated by errors due to the parasitic capacitive coupling of the SIP instrument, especially for lower conductivity samples. We developed a model showing the measured phase is the sum of the true sample phase and an error term ωCinZx, where ω is the angular frequency; Cin is the instrument input capacitance and Zx is a measurable impedance function related to the sample holder properties and the reference resistor. Based on this model, a new phase correction method is proposed that results in highly accurate SIP data up to 20 kHz as well as the determination of Cin. We tested the correction method using electric circuits, NaCl fluids and three unconsolidated samples (sand, sand-clay and sand-pyrite mixtures). The corrected phase for the circuit and NaCl fluid experiments showed excellent agreement with the theoretical phase response across the studied frequency range (errors <1 mrad). For unconsolidated samples, removal of errors results in phase spectra more consistent with expected polarization mechanisms, as based on phase peaks recorded for small pyrite and clay particles at high frequencies. These phase peaks could not be identified in the uncorrected data. Our approach can substantially enhance the value of the SIP method for the characterization of fine-grained sediments and rocks.

A Behavioral Compact Model for Static Characteristics of 3D NAND Flash Memory

We present a behavioral compact model for static characteristics of 3D NAND flash memory for integrated circuits and system-level applications utilizing BSIM-CMG 110.0.0. This model is easy to implement, computationally efficient, fast, accurate, and effectively accounts for the different parasitic capacitance coupling effects applicable to the 3D geometry of the vertical channel Macaroni body charge-trap flash memory. The model parameter extraction methodology is simple and can be extended to reproduce the electrical behavior of different 3D NAND flash memory architectures (with different page size, dimension, or a number of stacked layers). We believe that the developed compact model would equip the circuit designers and system architects with an effective tool for design-exploration of 3D NAND flash memory devices for diverse unconventional analog applications.

Shaft-to-Frame Voltage Mitigation Method by Changing Winding-to-Rotor Parasitic Capacitance of IPMSM

Common-mode voltage by switching pattern of space vector pulsewidth modulation excites parasitic capacitance coupling in interior permanent magnet synchronous motors, and it finally causes a shaft-to-frame voltage. Among all parasitic capacitances, winding-to-rotor parasitic capacitance has the greatest effect on the shaft-to-frame voltage, which means the winding-to-rotor parasitic capacitance must be suppressed for noticeable mitigation of the shaft-to-frame voltage. This paper proposes two suppression methods by changing the stator winding-to-rotor and end winding-to-rotor capacitances. First, the modified winding shape is utilized for the suppression of stator winding-to-rotor capacitance. Second, a copper shield is applied to suppress the end winding-to-rotor parasitic capacitance. Finally, both the methods are applied together to mitigate the effect of the stator winding-to-rotor and end winding-to-rotor capacitances on the shaft-to-frame voltage.