Parasitic Capacitance Research Articles

Precisely Patterned Channels in a Vertical Organic Electrochemical Transistor with a Diazirine Photo‐Crosslinker

AbstractOrganic electrochemical transistors (OECTs) rely on both efficient ionic doping/de‐doping process and carrier transport in the mixed ionic‐electronic channel under the modulation of gate bias. Moreover, channels that hold photopatterning capability are highly desired to minimize parasitic capacitance and simplify the fabrication process/cost. However, yielding photo‐patternable channels with both precise/robust patterning capability and controllable ionic‐electronic coupling is still challenging. Herein, double‐end trifluoromethyl diazirines (DtFDA) with different chain lengths are introduced in the OECT channel to act as both photo‐crosslinker and medium to regulate ionic‐electronic transport. Specifically, high‐resolution patterns with a minimum line width/gap of 2 μm are realized in p(g2T‐T) or Homo‐gDPP based channels by introducing DtFDA. Maximum transconductances of 68.6 mS and 81.6 mS, current on/off ratio of 106 and 107 (under a drain voltage of only ±0.1 V), are achieved in p‐ and n‐type vertical OECTs (vOECTs), respectively, along with current densities exceeding 1 kA cm−2 and good cycling stability of more than 100,000 cycles (2000 seconds). This work provides a new and facile strategy for the fabrication of vOECT channels with high resolution and high performance via the introduction of a simple and efficient crosslinker.

Precisely Patterned Channels in a Vertical Organic Electrochemical Transistor with a Diazirine Photo-Crosslinker.

Organic electrochemical transistors (OECTs) rely on both efficient ionic doping/de-doping process and carrier transport in the mixed ionic-electronic channel under the modulation of gate bias. Moreover, channels that hold photopatterning capability are highly desired to minimize parasitic capacitance and simplify the fabrication process/cost. However, yielding photo-patternable channels with both precise/robust patterning capability and controllable ionic-electronic coupling is still challenging. Herein, double-end trifluoromethyl diazirines (DtFDA) with different chain lengths are introduced in the OECT channel to act as both photo-crosslinker and medium to regulate ionic-electronic transport. Specifically, high-resolution patterns with a minimum line width/gap of 2 μm are realized in p(g2T-T) or Homo-gDPP based channels by introducing DtFDA. Maximum transconductances of 68.6 mS and 81.6 mS, current on/off ratio of 106 and 107 (under a drain voltage of only ±0.1 V), are achieved in p- and n-type vertical OECTs (vOECTs), respectively, along with current densities exceeding 1 kA cm-2 and good cycling stability of more than 100,000 cycles (2000 seconds). This work provides a new and facile strategy for the fabrication of vOECT channels with high resolution and high performance via the introduction of a simple and efficient crosslinker.

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.

Reduced OFF-state current and suppressed ambipolarity in a dopingless vertical TFET with dual-drain for high-frequency circuit applications

In this article, a dopingless TFET with dual-drain and reversed T-shaped channel (DLVIT-TFET) is investigated to offer improvement in ON-state current (IOn) along with the reduction in OFF-state leakage current (IOff) and in ambipolarity. The investigated device has a dual channel region which helps in improving the on-state parameters like IOn and subthreshold swing (SS) due to the extended tunneling area. The inverted T-shaped channel minimizes the charge carriers to tunnel during the off-state, thereby reducing the magnitude of IOff. The results obtained from 2D TCAD simulation show that the investigated device provides ∼1 order of improvement in IOn and ∼3 orders of improvement in IOff. Furthermore, DLVIT-TFET offers an ∼3 orders of improvement in ambipolar current (IAmb) due to a reduction in peak electric field at channel-drain interface caused by splitting of drain potential at ambipolar state. Moreover, various analog/RF parameters such as transconductance (gm), gate parasitic capacitance (Cgd, and Cgs), cut-off frequency (fTmax), gain-bandwidth product (GBP), transconductance-frequency product (TFP) and transit time (τ) are found to be improved in DLVIT-TFET compared to the conventional DL-TFET. In addition, the transient analysis of DLVIT-TFET based inverter is analyzed, which shows improvement in the parameters like propagation delay and voltage swing. Finally, reliability of the investigated device is discussed by considering the effect of interface trap charges (ITCs) and variation in ambient temperature and it is observed that DLVIT-TFET is more immune to such defects and environmental factors than the conventional one.

Improving RF characteristic and suppress gate leakage in normally-off GaN-HEMTs using negative polarization effect and floating gate for millimeter-wave systems

This article demonstrates the effect of reverse gradient barrier layer and floating gate structure on DC and RF performance of GaN-based HEMTs. In terms of power characteristics, using reverse gradient barrier and floating gate, the GaN-HEMTs with Lg of 240 nm and S-D spacing of 8.4 μm demonstrated the maximum drain current and peak transconductance are increased by 70 % and 15 % respectively, and the linearity of GaN based HEMT is greatly improved. Meanwhile, using the reverse gradient barrier layer, the gate leakage current is significantly reduced by nearly 1 to 5 orders of magnitude, and it is proved that the negative polarization effect has a certain effect on increasing the threshold voltage and breakdown voltage. In terms of RF characteristics, due to the existence of the floating gate, the parasitic capacitance is reduced and the frequency performance is improved. In addition, for both conventional and proposed HEMTs, this article proposes two equivalent capacitance models to optimize RF performance. As a result, the optimal structure offers approximately 10 and 7 times improvement in the current gain cutoff frequency (ft) and unilateral power gain cutoff frequency (fmax) (from 5.3 and 9.8 to 52 and 73.8 GHz, respectively). Additionally, the optimal structure exhibits outstanding scaling factors of 12.48 GHz·μm.

Analysis of the behavior of TCAD and SPICE diode models in ESD protection circuits

To protect the interfaces of high-speed ICs from ESD, it is necessary to develop and optimize specialized protection circuit designs to minimize parasitic capacitance. The classic widely used designs based on ggMOS and SCR have too large parasitic capacitance, which degrades the parameters of the interface pins of the ICs. It is necessary to develop and optimize other ESD protection designs. One of the possible promising options is optimized diode protection. In this paper, an analysis of the effect of the design of a diode protection on its electrical characteristics is carried out. An analysis of the possibility of modeling protection using SPICE models was also performed and an assessment of the need to use TCAD simulation was carried out. Based on a comparison of the results of SPICE and TCAD simulations, it is shown that widely used SPICE diode models not optimal for designing and optimizing diode ESD protection. For this task, it is necessary to use TCAD simulation, taking into account the self-heating of the structure and the dynamics of the propagation of the thermal front. The results of this work are used for the development of ESD protection for interfaces of high–speed microcontrollers, DACs/ADCs, and transceivers.

Realization of a composite ferroelectric characterization test system using a modified constant current method and a modified virtual ground method.

A composite ferroelectric characterization test system constructed using a modified constant current method (CCM) and a modified virtual ground method (VGM) has been successfully designed and implemented. By sending instructions to the microcontroller through software, the system's test mode can be easily changed by arranging the switching status of six switching elements. When validating the system, a dual-channel precision source/measure unit B2912B was used to verify this design. There is also parasitic capacitance that cannot be ignored in this commercial machine. This parasitic capacitance affects the appearance of the entire hysteresis curve. However, the parasitic capacitance values also differ in various test current ranges. In addition, to confirm the data credibility of this composite ferroelectric test system, Keysight B1530A and Radiant Premier II were used to conduct cross-verification between different systems. The results obtained between different systems show good consistency. Furthermore, reproducible and recoverable imprint phenomena were found in this composite system during interactive validation using VGM and CCM methods. After designing different voltage profiles for verification, it was found that the root cause of this imprint phenomenon was the difference between the final polarization state of the previous test and the pre-initialized polarization state. This imprint phenomenon exists in traditional Pb(Zr, Ti)O3(PZT) ferroelectric capacitors and Hf0.5Zr0.5O2-based ferroelectric capacitors. Fortunately, this imprint phenomenon is reversible. Moreover, this imprint phenomenon disappears through the design of the time-varying voltage profile on the ferroelectric capacitor of the CCM method.

Homogenized Finite Element Analysis for Multi-Turn Coils Considering Parasitic Capacitances

Homogenized Finite Element Analysis for Multi-Turn Coils Considering Parasitic Capacitances

WITHDRAWN: An 81MV/s SR, ±12.5V Swing Operational Amplifier with 2.15nV/√Hz Noise floor

—This brief introduces a high-voltage, high-speed and low-noise operational amplifier designed with a standard BCD process. High noise performance is achieved by using the bipolar transistors as input stage. However, the significant parasitic capacitance of the bipolar transistors leads to slew rate (SR) deterioration bandwidth deterioration. To overcome these problems, an improved folded-cascode structure with bipolar-based source degeneration current mirror (BSD-CM), the mirror pole control technique and the fast response output stage is proposed. The simulation results show that the BSD-CM improves the bandwidth by 35dB compared to the traditional bipolar current mirror. The mirror pole control improves the bandwidth of amplifier by 9dB. The fast response output stage improves the SR by 2 times. The proposed amplifier is fabricated with a standard 0.18 μm BCD process. The chip area is 3.75 mm2. The measurement results show that this amplifier consumes 4.5 mA with a ±15 V voltage supply. The SR is 81MV/s, the GBW is 158MHz and the input referred noise is 2.15 nV/√Hz.

A Systematic Methodology for Parasitic Capacitance Estimation and Validation of Multichip Modules

This paper proposes a method for extracting parasitic capacitances from die terminals to baseplate in a multi-chip-module (MCM). The parasitic capacitors constitute the common mode (CM) equivalent circuit model enabling filter design. While traditionally simple open module die area measurements are used to calculate capacitance from concerned nodes to baseplate, such methods result in breaking the module or contamination, rendering the module useless. This is especially concerning for high voltage (HV) rated modules (> 10 kV) where cost can be a deciding factor. Hence, a non-intrusive double pulse test method is developed to extract the parasitic capacitance from specific nodes to ground without physical damage to the module. Consequently, the proposed method is verified using a series of tests and open module measurements. The distributed capacitors can be transformed into lumped capacitors for electromagnetic compatibility (EMC) simulations and filter design. The proposed method is analyzed on a Three-Level Neutral Point Clamped (3L-NPC) phase leg module and compared against traditional method. Finally, the impact of estimation errors on the proposed method are discussed.

Nonisolated Three-Phase Current DC-Link Buck–Boost EV Charger With Virtual Output Midpoint Grounding and Ground Current Control

Non-isolated three-phase AC/DC converter concepts facilitate more compact and more efficient realizations of future EV chargers. However, without the galvanic isolation and/or high common-mode (CM) impedance provided by an isolation transformer, non-isolated chargers must employ other means to suppress CM leakage currents to ground sufficiently and to prevent nuisance tripping of mandatory residual current devices (RCDs). Typically, the required EMI filters reduce high-frequency (HF) CM leakage currents to uncritical values. However, low-frequency CM voltages, e.g., generated by third-harmonic injection, may drive significant LF CM currents through the parasitic capacitances of the DC output (including the battery pack) to protective earth (PE). Therefore, considering a non-isolated three-phase buck-boost current DC-link PFC rectifier system that consists of a buck-type current-source rectifier (CSR) stage and a three-level boost-type DC/DC-stage, this paper first proposes a virtual grounding control (VGC) of the DC output voltage midpoint. VGC employs the DC/DC-stage to compensate the LF (third-harmonic) CM voltage inherently generated by the CSR-stage, and thus controls the LF CM voltage between the DC output midpoint and PE to zero. This enables further a direct connection of the DC output midpoint to PE, where an additionally proposed ground current control (GCC) ensures near-zero LF CM leakage current. The proposed concepts are verified with a 10kW hardware demonstrator (power density of 6.4 kW/dm3 or 107.5 W/in3, full-load peak efficiency of 98.5%) considering TT (Terra-Terra) and TN (Terra-Neutral) grounding systems. With a direct connection of the DC output midpoint to PE, GCC limits the LF CM leakage current to < 6mA RMS, i.e., significantly below typical RCD trip levels, and, using the human-body impedance model according to UL 2202, achieves a test voltage of 110mV that is clearly below the most stringent limit (250 mV) of the standard.

Fabrication of the low-k films with tunable k value as spacers in advanced CMOS technology

In advanced CMOS technology, a suitable spacer scheme is crucial to alleviate the effects of increasing parasitic resistance and capacitance on device performance as the critical dimensions shrinking. Low dielectric constant (low-k) films, possessing a tunable k value ranging from 3.5 to 6.5, were fabricated using plasma-enhanced atomic layer deposition in a single chamber. The fabrication process involved the deposition of the SiN film via SiH2I2 with N2 plasma, as well as the deposition of the SiOX, SiOCN, and SiON films using diisopropylamino silane with O2, Ar/O2, and N2/O2 plasmas, respectively. The introduction of groups containing carbon (C) tended to loosen the film structure, due to its weak bond strength with Si, thus made distinctions in structural and electrical stability. We developed such a process which can adjust the C-group concentration and O, N content to tune the film k value. The SiOx, SiOCN, SiON, and SiN films had high breakdown strength of 9.04, 7.23, 9.41, and over 11 MV cm−1, and meanwhile low leakage current density of 2.42 × 10−9, 4.78 × 10−8, 1.29 × 10−9, and 9.26 × 10−10 A cm−2, respectively. The films exhibited remarkable thermal stability, enhanced breakdown strength, and suppressed leakage with annealing treatment, which could be attributed to the desorption of —CHX groups. Moreover, the low-k materials demonstrated excellent step coverage both in the inner-spacer cavity and on sidewalls, exploring the potential application as spacers in advanced CMOS structure.

Analysis and Compensation of Phase Current Measuring Error Caused by Sensing Resistor in PMSM Application.

Field Oriented Control (FOC) effectively realizes independent control of flux linkage and torque, and is widely used in application of Permanent Magnet Synchronous Motor (PMSM). However, it is necessary to detect the phase current information of the motor to realize the current closed-loop control. The phase current detection method based on a sampling resistor will cause a measurement error due to the influence of parasitic parameters of the sampling resistor, which will lead to the decrease in PMSM control performance. This paper reveals the formation mechanism of the current sampling error caused by parasitic inductance and capacitance of the sampling resistor, and further confirms that the above error will lead to the fluctuation of the electromagnetic torque output by simulation. Moreover, we propose an approach for online observation and compensation of the current sampling error based on PI-type observer to suppresses the torque pulsation of PMSM. The phase current sampling error is estimated by the proportional and integral (PI) observer, and the deviation value of current sampling is obtained by low-pass filter (LPF). The above deviation value is further injected into the phase current close-loop for error compensation. The PI observer continues to work to keep the current sampling error close to zero. The simulation platform of Matlab/Simulink (Version: R2021b) is established to verify the effectiveness of online error observation and compensation. Further experiments also prove that the proposed method can effectively improve the torque fluctuation of the PMSM and enhance its control accuracy performance of rotation speed.

Effect of Metal Oxide Semiconductor Field-Effect Transistor Output Parasitic Capacitance on Efficiency in Full-Bridge LLC DC/DC Converters.

This study analyzed the efficiency impact of a MOSFET output parasitic capacitance (Coss) on a full-bridge LLC DC/DC converter. The core of the converter was the control chip for a half-bridge LLC DC/DC converter, and the output signal of the chip controlled the first-arm power transistors of the primary side of the converter. The coupling transformer reversed the output signal to control the primary side of the second arm of the power transistor. The full-bridge converter comprises a half-bridge control chip that converts the high-voltage DC power supply to a low-voltage DC power supply, which is then synchronously rectified and supplied to the load. The primary side of the power transistor achieves a zero-voltage switching (ZVS) state through the resonance of the LLC converter. This design gives the converter high power density and a simple structure. Furthermore, to determine the appropriate output parasitic capacitance for improving converter efficiency, this study analyzed the effect of the output parasitic capacitance on the switching loss and conduction loss of the power transistor on the basis of the output parasitic capacitance of the primary-side power transistor. A 1200 W converter prototype was fabricated in this study, and when the output was 300 W, efficiency increased from 92.603% to 93.462%, a 0.859% increase. The empirical results verified the feasibility of the proposed theory.

Enhanced gate biasing resilience in asymmetric and double trench SiC MOSFETs towards generalized highly reliable power electronics

The gate oxide quality in SiC MOSFETs presents a significant challenge, particularly at temperatures exceeding 175 °C. This predicament arises from the gate oxide interface's propensity to trap or release charge carriers, compromising device ruggedness. In mainstream SiC MOSFETs, the gate oxide in the trench corner confronts the demanding task of enduring higher electric field strengths, thereby posing a substantial risk to overall device reliability. As a result, research entities are proactively involved in improving the SiC/oxide interfaces to enhance the devices' resilience against elevated E-field. This endeavor aims to maintain the favorable characteristics of the trench SiC MOSFETs, including low on-state resistance, minimal parasitic capacitance, and exceptional switching performance. Thus, the implementation of a streamlined process becomes crucial to fortify the trench corner, ultimately yielding boosted E-field immunity. In this report, our research focuses on enhancing the reliability of trench corner in SiC MOSFET devices. Specifically, we employ spacer etch technology to selectively shield the trench corner with high-K heterolayers, thereby enhancing the device's ability to withstand higher E-field strengths (59.2 % reinforcement) while mitigating the risk of hidden defects. Importantly, compared to the structure without protection, at high-K shielded layer contact angles ranging from 90 to 150°, the E-field decreases, correlated the enhanced reinforcement at larger angles. Furthermore, such technology enables higher E-fields and greater circuit capacity at the bottom of trench gate, leading to enhanced device reliability. Our studies confirm that the developed device structure exhibits simplicity, reliability, maturity, and controllability, rendering it suitable for large-scale integration applications.

A Low-Power, 65 nm 24.6-to-30.1 GHz Trusted LC Voltage-Controlled Oscillator Achieving 191.7 dBc/Hz FoM at 1 MHz

This work presents a novel trusted LC voltage-controlled oscillator (VCO) with an embedded compact analog Physically Unclonable Function (PUF) used for authentication. The trusted VCO is implemented in a 1P9M 65 nm standard CMOS process and consumes 1.75 mW. It exhibits a measured phase noise (PN) of −104.8 dBc/Hz @ 1 MHz and −132.2 dBc/Hz @ 10 MHz offset, resulting in Figures of Merit (FoMs) of 191.7 dBc/Hz and 199.1 dBc/Hz, respectively. With the measured frequency tuning range (TR) of ~5.5 GHz, the FoM with tuning (FoMT) reaches 197.6 dBc/Hz and 205.0 dBc/Hz at 1 MHz and 10 MHz offset, respectively. The analog PUF consists of CMOS cross-coupled pairs in the main VCO to change analog characteristics. Benefiting from the impedance change and parasitic capacitance of the cross-coupled pairs, the AC and DC responses of the VCO are utilized for multiple responses for each input. The PUF consumes 0.83 pJ/bit when operating at 1.5 Gbps. The proposed PUF exhibits a measured Inter-Hamming Distance (HD) of 0.5058b and 0.4978b, with Intra-HD reaching 0.0055b and 0.0053b for the current consumption and fosc, respectively. The autocorrelation function (ACF) of 0.0111 and 0.0110 is obtained for the current consumption and fosc, respectively, at a 95% confidence level.

The parasitic capacitance considerations of metal interconnects in sub 10 nm era

With the development of the integrated circuit industry and semiconductor technology, we have entered the sub-10 nanometers era, which means the distance between adjacent components in a device is less than 10 nm. This is a situation where the parasitic capacitance of metal interconnects must be considered. Parasitic capacitance can act as a significant influence in different ways on disparate devices. Fin field-effect transistors and microelectromechanical systems are typical devices and deserve further detailed explanation on their parasitic capacitance. There are many ways to reduce parasitic capacitance and its attendant effects, including using materials with low dielectric constants and optimizing the structure of the layout. Some others are newly brought out in recent years due to advanced industrial technology and new materials, including carbon nanotubes, oxide-free spacer layers, and tunneling hybrid technology. All these methods are of great significance and practicability to producing and applying semiconductor devices and structures. Knowing more about this expertise about parasitic capacitance can help us better understand its nature and specialties.

Full ZVS Achievement for DCM Grid-Tied Inverter With Improved Average Current Model and Considering Nonlinear Parasitic Capacitance

Full ZVS Achievement for DCM Grid-Tied Inverter With Improved Average Current Model and Considering Nonlinear Parasitic Capacitance

A Multidisciplinary Approach toward CMOS Capacitive Sensor Array for Droplet Analysis.

This paper introduces an innovative method for the analysis of alcohol-water droplets on a CMOS capacitive sensor, leveraging the controlled thermal behavior of the droplets. Using this sensing method, the capacitive sensor measures the total time of evaporation (ToE), which can be influenced by the droplet volume, temperature, and chemical composition. We explored this sensing method by introducing binary mixtures of water and ethanol or methanol across a range of concentrations (0-100%, with 10% increments). The experimental results indicate that while the capacitive sensor is effective in measuring both the total ToE and dielectric properties, a higher dynamic range and resolution are observed in the former. Additionally, an array of sensing electrodes successfully monitors the droplet-sensor surface interaction. However practical considerations such as the creation of parasitic capacitance due to mismatch, arise from the large sensing area in the proposed capacitive sensors and other similar devices. In this paper, we discuss this non-ideality and propose a solution. Also, this paper showcases the benefits of utilizing a CMOS capacitive sensing method for accurately measuring ToE.

Electrical characterization and imaging of discharge morphology in a small-scale packed bed dielectric barrier discharge

Packed bed dielectric barrier discharges (DBDs) exhibit an improved energy efficiency and selectivity in nonthermal plasma based gas conversion. They enable the direct interaction between plasma and catalyst. In this contribution a compact coaxial DBD reactor enabling the end-on imaging of the discharge with and without packed beds is studied. The discharge morphology is correlated with electrical measurements such as voltage-charge (V-Q) plots. The studies are performed for different packed bed materials, binary gas compositions of argon and carbon dioxide, voltage amplitudes, average powers, and pressures. The analysis points outs the role of parasitic capacitances and parasitic discharges as often overlooked aspects. The introduction of the packed bed material into the coaxial barrier discharge arrangement increases the total capacitance, but the barrier of the outer glass tube mostly determines the maximum effective dielectric capacitance. The choice of the packed bed material determines the voltage threshold and the average discharge power. The investigations leads to a revision of the equivalent circuit for packed bed barrier discharge reactors, which also accounts the properties of different filling materials.