Abstract
—This brief introduces a high-voltage, high-speed and low-noise operational amplifier designed with a standard BCD process. High noise performance is achieved by using the bipolar transistors as input stage. However, the significant parasitic capacitance of the bipolar transistors leads to slew rate (SR) deterioration bandwidth deterioration. To overcome these problems, an improved folded-cascode structure with bipolar-based source degeneration current mirror (BSD-CM), the mirror pole control technique and the fast response output stage is proposed. The simulation results show that the BSD-CM improves the bandwidth by 35dB compared to the traditional bipolar current mirror. The mirror pole control improves the bandwidth of amplifier by 9dB. The fast response output stage improves the SR by 2 times. The proposed amplifier is fabricated with a standard 0.18 μm BCD process. The chip area is 3.75 mm2. The measurement results show that this amplifier consumes 4.5 mA with a ±15 V voltage supply. The SR is 81MV/s, the GBW is 158MHz and the input referred noise is 2.15 nV/√Hz.
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