Parasitic Bipolar Effect Research Articles

Floating-body effects in partially depleted SOI CMOS circuits

This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.

A study on high temperature CMOS circuits for sensor applications with SDB-SOI wafer.

High temperature CMOS circuits for sensor applications have been fabricated using Silicon-Direct-Bonding (SDB) SOI wafers. A novel SOI-MOSFET structure was fabricated on silicon film of 800nm in thickness above a buried oxide layer of 1μm in thickness. The MOSFET was designed in order to remove Kink-effect and parasitic bipolar transistor effect, and the fabrication process was optimized by process simulator(SUPREM III). The signal conditioning circuits (Operational amplifier and C-F converter) for sensor applications were designed and fabricated with the MOSFET. These MOSFET and signal conditioning circuits were operated up to 300°C. The temperature dependence of the MOSFET and the characteristic of the circuits were evaluated from room temperature to 300°C.

Scaling constraints imposed by self-heating in submicron SOI MOSFET's

The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Suppression of parasitic bipolar effects and off-state leakage in fully-depleted SOI n-MOSFET's using Ge-implantation

This work demonstrates a well-controlled technique of channel defect engineering, by implanting germanium into the channel of a Silicon-On-Insulator (SOI) MOSFET to generate subgap energy states. These subgap states act as minority-carrier lifetime killers to spoil the parasitic bipolar gain, and thus improve the source-to-drain breakdown voltage and reduce the front-channel gate-induced-drain-leakage (GIDL). The Ge-implant also serves the dual purpose of positioning most of the subgap states in the back interface region which reduce back-channel off-state leakage.

Improvement of radiation hardness in fully-depleted SOI n-MOSFETs using Ge-implantation

This work demonstrates a well-controlled technique of channel defect engineering by implanting germanium into the channel of a silicon-on-insulator (SOI) MOSFET to generate subgap energy states. These subgap states act as minority-carrier lifetime killers to reduce parasitic bipolar effects. The Ge-implant also serves the dual purpose of positioning most of the subgap states in the back interface region which retard the total dose responses of off-state leakage and front-channel threshold voltage.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Twin-MOSFET structure for suppression of kink and parasitic bipolar effects in SOI MOSFETs at room and liquid helium temperatures

A twin-MOSFET structure is proposed for suppression of the kink and parasitic bipolar effects in SOI MOS transistors. It is also an attractive candidate to provide satisfactory linear device operation at liquid He temperature. The device consists of two transistors in series with a common gate but it operates as a single transistor. Kink effect can be confined to the one “slave” transistor while the other “master” transistor can be kept free from the kink effect. If the gate length of the master transistor is larger than that of the slave one, the kink-free master transistor dominates the overall output characteristics of the device. As a consequence, the kink effect is suppressed in the overall output characteristics of the device. Furthermore, the parasitic bipolar effect in SOI MOSFETs is also significantly reduced and the saturation drain output impedance as well as the output breakdown characteristics are drastically improved. Kink-free and very flat output characteristics are obtained at both room and liquid He (4.2 K) temperatures.

Suppression of parasitic bipolar effects in thin-film SOI transistors

In order to correctly estimate the bipolar holding voltage of thin-film SOI transistors with submicrometer gate lengths, it is necessary to obtain the correct balance between the bipolar current gain and impact ionization. The bipolar current gain was found to be strongly dependent upon bandgap narrowing in the heavily doped source, while impact ionization may be most accurately modeled with a nonlocal ballistic model employing a composite electron mean-free path of 9.2 nm. Simulation with the improved models suggests that a reduction in the lateral electric field of the n/sup -/ drain region, and hence an increased bipolar holding voltage, may be achieved by using ultrathin highly doped SOI films. For a 0.5- mu m gate length, a maximum holding voltage in excess of 6 V has been simulated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Body tie placement in CMOS/SOI digital circuits for transient radiation environments

The authors present criteria for the use of body ties to reduce or eliminate parasitic bipolar effects important in the transient radiation response of SOI/CMOS devices. A theoretically derived body tie spacing rule is verified using both TRIGSPICE and PISCES II with photocurrent injection capabilities. The tie spacing rule, which is independent of feature size within bounds, provides a simple guideline for design/layout for CMOS/SOI digital circuits for harsh transient radiation environment. >

Experimental and simulation study of the effects of cosmic particles on CMOS/SOS RAMs

The existence of a charge multiplication effect in CMOS/SOS RAM circuits, as reported by J. Rollins (1987), is confirmed. Shorter channel lengths and higher power supply voltages caused the ratio, M, of upset charge to deposited charge to increase. As a result of this multiplication factor, actual devices are more likely to upset than expected from an analysis of only the collected charge. A mixed-mode simulator was used to model the charge collection process. The results showed that the M factor is a very fluid number which is dependent on minority carrier lifetime, drain voltage, and the switching dynamics of the cell in addition to the dependence on mobility ratio and channel length reported by Rollins. Parasitic bipolar gain at high injection levels appears to be the primary mechanism allowing collected charge to be greater than deposited charge. The simulator and experimental data show that, as floating body static memory transistors are down scaled, the particle energy needed to upset the cell is reduced because of the enhanced parasitic bipolar gain effect as well as a reduction in the node capacitance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Unusually abrupt switching in submicrometer thin-film transistors using a polysilicon film with enhanced grain size

Unusually abrupt drain current change observed in polysilicon thin-film transistors (TFTs) with a channel length and width of 1 mu m or smaller is discussed. The polysilicon used to fabricate the devices was deposited by low-pressure chemical vapor deposition (LPCVD) and the grain size of the film was enhanced by silicon ion implantation followed by a low-temperature anneal. The TFTs exhibited an abrupt drain current change of more than five orders of magnitude for a corresponding gate voltage change of less than 40 mV. A self-limiting positive feedback loop due to impact ionization currents and/or a parasitic bipolar effect are suggested as possible explanations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Parasitic bipolar effects in submicrometer GaAs MESFET's

We report the observation for the first time of parasitic bipolar action in GaAs MESFET's. It manifests itself in the form of increased transconductance at higher drain voltage, abrupt change in output conductance (kink effect) around 4-V drain-source voltage, and a gate-voltage-dependent substrate current. These effects are explained by electron-hole pair generation in the high-field region at the drain. The holes generated are injected into the substrate where they form the base region of a parasitic lateral bipolar transistor. The effect also explains a new breakdown mechanism for short-channel enhancement-mode MESFET's.

N- and P-well optimization for high-speed N-epitaxy CMOS circuits

A double-well n-epi CMOS process was used to investigate the influence of technological parameters relevant to high-speed performance. Dopant concentrations, well depths, channel lengths, and epi-layer thickness have been varied with regard to low propagation delay times measured by three-input NOR/NAND ring oscillators. Parasitic bipolar effects like latchup have been taken into consideration. Ring oscillator circuits designed in general with 3.5-µm design rules and with geometrical gate lengths ≤2 µm exhibited gate delays ≤0.9 ns. The influence of low temperature processing on short-channel and field oxide transistors is discussed.

On the theory of the thermionic emission transistor II. TET as an element of logic circuits

The theory of the Thermionic Emission Transistor proposed by us earlier is further developed. It is shown that the structure can be significantly simplified with only a marginal loss in its performance. The simplification consists in eliminating the need for a built-in planar doped triangular potential barrier. The current-voltage characteristics, the voltage gain, and the transconductance are calculated for exemplary TET structures. The proposed simplification makes it feasible to incorporate devices of complementary carrier type on a single chip thus forming the basis for CMOS-like logic. An important advantage of the TET in this application is the low required level of the supply voltage, viz. approx. 0.5 V, which virtually eliminates all the parasitic bipolar effects. The transfer characteristic is calculated for a basic inverter gate. For a numerical example of an inverter pair of total area 10 μm × 10 μm and period 0.6 μm of the surface electrode pattern the estimated inverter delay is 5 ps for fan out of 1.