On the theory of the thermionic emission transistor II. TET as an element of logic circuits

Abstract

The theory of the Thermionic Emission Transistor proposed by us earlier is further developed. It is shown that the structure can be significantly simplified with only a marginal loss in its performance. The simplification consists in eliminating the need for a built-in planar doped triangular potential barrier. The current-voltage characteristics, the voltage gain, and the transconductance are calculated for exemplary TET structures. The proposed simplification makes it feasible to incorporate devices of complementary carrier type on a single chip thus forming the basis for CMOS-like logic. An important advantage of the TET in this application is the low required level of the supply voltage, viz. approx. 0.5 V, which virtually eliminates all the parasitic bipolar effects. The transfer characteristic is calculated for a basic inverter gate. For a numerical example of an inverter pair of total area 10 μm × 10 μm and period 0.6 μm of the surface electrode pattern the estimated inverter delay is 5 ps for fan out of 1.