Transistor Parameters Research Articles

Development of the Ge-MDST instrument structure with an induced p-type channel

The conditions for the growth of n-type Ge conduction layers by the HW CVD method with the parameters required to create a Ge-TIR transistor with an induced p-type channel are determined. The conditions of deposition by electron beam deposition and subsequent annealing of layers of a high-k dielectric ZrO2:Y2O3 are optimized, allowing to achieve a leakage current of 5 × 10–6 A/cm2. For the developed instrument structure, some parameters of the Ge-TIR transistor were calculated, such as the channel length, the maximum voltage between the drain and the source, and the breakdown voltage.

Improving bias stability of IGZO field-effect transistors through CF4 plasma treatment of Al2O3 dielectrics

In this study, the effects of the CF4 plasma treatment on the amorphous indium gallium zinc oxide (IGZO) material were explored. The electrical characteristics of the IGZO-based field-effect transistor (FET) were also thoroughly examined to analyze the influence of the plasma treatment. Excellent adhesion of the sol-gel-based IGZO semiconducting film was achieved owing to the strong dipole moment of the AlOxFy layer created by the surface treatment. In particular, X-ray photoelectron spectroscopy depth profiles and transmission electron microscopy electron energy loss spectroscopy analyses provided clear evidence that fluorine atoms diffused into the Al2O3 surface via the CF4 plasma treatment. The formation of an AlOxFy layer at the IGZO/Al2O3 interface is expected to be advantageous for reducing the interface trap density, thereby enhancing the critical transistor parameters. Additionally, the plasma-treated IGZO transistor demonstrated strong electrical bias stability under continuous gate bias stress conditions. Therefore, surface modification via CF4 plasma treatment is proposed to boost the stability and performance of the device, offering a straightforward approach for integrated thin-film transistor circuitry in advanced display applications.

Trade-off analysis between gm/ID and fT of GNR-FETs with single-gate and double-gate device structure

This study examines the operational parameters of field-effect transistors (FETs) using single-gate (SG) and double-gate (DG) graphene nanoribbons (GNRs) within the analog/RF domain. A detailed exploration is conducted through an atomistic pz orbital model, derived from the Hamiltonian of graphene nanoribbons, employing the nonequilibrium Green’s function formalism (NEGF) for analysis. The atomic characteristics of the GNRFETs channel are accurately described by utilizing a tight-binding Hamiltonian with an atomistic pz orbital basis set. The primary focus of the analysis revolves around essential analog/RF parameters such as transconductance, transconductance generation factor (TGF), output resistance, early voltage, intrinsic gain, gate capacitance, cut-off frequency, and transit time. Furthermore, the study assesses the gain frequency product (GFP), transfer frequency product (TFP), and gain transfer frequency product (GTFP) to evaluate the balance between transistor efficiency, gain, and cut-off frequency. The research outcomes indicate that double-gate GNRFETs exhibit superior analog/RF performance in comparison to their single-gate counterparts. However, both types of devices demonstrate cut-off frequencies in the gigahertz range. The extensive data presented in this study provides valuable insights into the characteristics of SG and DG GNRFETs, particularly in terms of the figure-of-merit (FoM) for analog/RF performance, offering a comprehensive analysis of the trade-offs in analog applications. In addition, the analysis has been extended be performing a high-performance hybrid 6T static random-access memory (SRAM) to get the impact in their circuit level variation as well as improvement in their circuit performance.

Improving the performance parameters of organic field-effect transistors via alkyl chain length of boronic acid self-assembled monolayers

Interface modification is a promising technique for enhancing electrical parameters of Organic Field Effect Transistor (OFETs). In OFETs, self-assembled monolayer molecules are widely used for treatment dielectric/semiconductor interface layer. Modification of dielectric/semiconductor layer with SAM molecules ensures a variety of potential applications. Boronic acids with four different alkyl chain lengths (Cn-BA; n = 8, 10, 12, 14) molecules were used in this study to treat the Al2O3 dielectric surface in dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) based OFETs. Treated with SAMs improve the mobility of Al2O3 surfaces for linear and saturation regime and threshold voltages shifted from positive direction. The morphological and electrical characterizations were performed for fabricated OFET. The results show that alkyl-boronic acids SAM molecules open a new perspective for further optoelectronic applications due to its application for oxide surfaces and controllability.

A broadband low‐loss SPDT RF switch using a new off‐chip compensation technology

SummaryAn off‐chip compensation technology for low‐loss and broadband characteristics of radio frequency (RF) switches is proposed based on mathematical analysis of series shunt single pole double throws switches in this letter. This compensation technology can absorb the parasitic parameters of the switch Field Effect Transistor, improving the insertion loss and return loss of the switch as well as supporting higher bandwidth. To verify the design principle, a RF switch, using the SANAN GaAs 0.15 um pseudomorphic High Electron Mobility Transistors (pHEMT) process, and an off‐chip compensation network were designed and implemented. Specifically, after using an off‐chip compensation network, the measured bandwidth of switch has been expanded from 1.1–8.8 to 0.8–11 GHz, while the input and output return loss have also improved significantly.

ПРОЕКТИРОВАНИЕ ПЕЧАТНОЙ ПЛАТЫ C КОНТАКТНЫМ УСТРОЙСТВОМ ДЛЯ КОНТРОЛЯ ПАРАМЕТРОВ СЕРИЙНО-ВЫПУСКАЕМЫХ ТРАНЗИСТОРОВ

The article discusses the design of a printed circuit board of a contact device designed to control the electrical parameters of serial produced transistors. This contact device is a double-sided printed circuit board. The developed electrical circuit diagram of this device is given, the components included in it are listed. The process of designing a printed circuit board, which includes several stages, is described. The topology of a double-sided printed circuit board made using the Altium Designer program is shown. The criteria for the design of this topology are highlighted. The used circuit board layers are described. Next, based on the created Gerber files, using the high-quality production technology of a printed circuit board layout was made. In the future, a printed circuit board made in this way can be used to test the electrical parameters of transistors.

Accurate Multi-segment Probability Density Estimation Through Moment Matching

The impact of process variations continues to grow as transistor feature size shrinks. Such variations in transistor parameters lead to variations and unpredictability in circuit output and may ultimately cause them to violate specifications leading to circuit failure. In fact, timely failures in critical circuits may lead to catastrophic failures in the entire chip. As such, statistical modeling of circuit behavior is becoming increasingly important. However, existing statistical circuit simulation approaches fail to accurately and efficiently analyze the high sigma behavior of probabilistic circuit output. To this end, we propose PDM (Piecewise Distribution Model) - a piecewise distribution modeling approach via moment matching using maximum entropy to model the high sigma behavior of analog/mixed-signal (AMS) circuit probability distributions. PDM is independent of the number of input dimensions and matches region specific probabilistic moments which allows for significantly greater accuracy compared to other moment matching approaches. PDM also utilizes Spearman’s rank correlation coefficient to select the optimal approximation for the tail of the distribution. Experiments on a known mathematical distribution and various circuits obtain accurate results up to 4.8 sigma with 2-3 orders of speedup relative to Monte Carlo. PDM also demonstrates better accuracy while compared against other state-of-the-art statistical modeling approaches, such as maximum entropy, importance sampling, and subset simulation.

Reliability analysis and comparison of ring-PUF based on probabilistic models

—To address the issue of maladaptive reliability theory models in delay-based physical unclonable functions (PUF) of ring classes, this paper begins by analyzing the relationship between four key transistor parameters (channel length, channel width, threshold voltage, and gate oxide thickness) and delay sensitivity. Then establishes reliability quantification formulas for various PUF types, including ring oscillator PUF, k-out-of-1 PUF, Loop PUF, transient effect ring oscillator PUF, and duty cycle PUF. This analysis and comparison are conducted using the inverter delay model and probabilistic statistical methods to ensure fairness at the theoretical level. Finally, the proposed model is validated through simulation experiments, along with further analysis and comparison of ring-PUF. The results demonstrate that delay sensitivity can be utilized to assess the extent of delay impact when process parameters fluctuate. In terms of reliability, the ring-PUF can be ranked as follows: k-out-of-1 PUF, Loop PUF, ring oscillator PUF, transient effect ring oscillator PUF, and duty cycle PUF. This paper offers extensive technical guidance and theoretical support for ring PUF designers.

Determining the Electron Scattering from Interfacial Coulomb Scatterers in Two-Dimensional Transistors.

Two-dimensional (2D) transistors are promising for potential applications in next-generation semiconductor chips. Owing to the atomically thin thickness of 2D materials, the carrier scattering from interfacial Coulomb scatterers greatly suppresses the carrier mobility and hampers transistor performance. However, a feasible method to quantitatively determine relevant Coulomb scattering parameters from interfacial long-range scatterers is largely lacking. Here, we demonstrate a method to determine the Coulomb scattering strength and the density of Coulomb scattering centers in InSe transistors by comprehensively analyzing the low-frequency noise and transport characteristics. Moreover, the relative contributions from long-range and short-range scattering in the InSe transistors can be distinguished. This method is employed to make InSe transistors consisting of various interfaces a model system, revealing the profound effects of different scattering sources on transport characteristics and low-frequency noise. Quantitatively accessing the scattering parameters of 2D transistors provides valuable insight into engineering the interfaces of a wide spectrum of ultrathin-body transistors for high-performance electronics.

An Ameliorated Small-Signal Model Parameter Extraction Method for GaN HEMTs up to 110 GHz with Short-Test Structure

An improved method of extracting small-signal equivalent circuit model parameters for gallium nitride high electron mobility transistors (GaN HEMTs) is presented. This paper intends to present a method to extract the parasitic inductance and resistance of transistors based on the short-test structure without the open-circuit test structure. The parasitic capacitance of transistors is extracted by the method based on the size scalable model. Compared with the traditional COLD-FET method, the extraction procedure is simpler and more convenient. After removing the influence of parasitic elements, the intrinsic parameters of the model can be extracted by the S-parameters measured at different bias points. The experimental results show that the simulation results have good agreement with the measured results in the range of 0.5∼110 GHz.

The Modeling of GaN-FET Power Devices in SPICE

This paper focuses on the problem of the modeling of FET power transistors made of gallium nitride offered by GaN Systems, Transphorm, and Nexperia. The considered devices have been available on the market since 2014. GaN-FETs are built as a cascade connection of a normally on gallium nitride HEMT and a normally off MOSFET made of silicon. On the manufacturer’s sites, one can find models of these devices for like-SPICE tools in the text form. The main goal of this paper is to evaluate the model’s accuracy by comparing calculation results obtained by the use of the considered models with the authors’ measurement results and datasheet. It has been demonstrated that the GaN Systems model built on controlled sources described by a set of arbitrarily selected mathematical functions more accurately reproduces the basic characteristics of a transistor. On the other hand, the models from Transphorm and Nexperia, which are constructed based on built-in semiconductor device models, more precisely calculate the values of selected functional transistor parameters.

Design of Fully Differential Amplification Circuit and Analysis of Related Parameters Based on Feedback Mechanism

In this paper, a new feedback-based mismatch reduction method is proposed for CMOS process-based differential circuit design. The method combines an active feedback circuit and a differential amplifier circuit to reduce the error caused by device mismatch by utilizing the feedback signal, which is calculated to achieve higher circuit performance and accuracy. Meanwhile, based on the actual circuit simulation in Candence, it is concluded that under the conditions of input voltage of 5V, operating current of 100mA, and the same transistor parameters, the circuit with the introduction of the feedback mechanism is able to achieve a maximum gain of about 10dB and a lower common mode rejection ratio at the same frequency compared with the circuit without feedback.

Electrical Characterization of InGaZnO-Based Thin Film Transistor fabricated by Three-mask Process

Indium Gallium Zinc Oxide (InGaZnO) has gained increasing attention as a replacement for amorphous silicon in thin-film transistors (TFTs) owing to its excellent electrical and optoelectronic properties, chemical stability, and potential for low-temperature processing.
 However, efforts are being made to optimize the design to improve the performance and reduce costs.
 In this study, a top-contact top-gate (TCTG) structure of InGaZnO TFTs was fabricated using three lithography steps. The electrical current–voltage characteristics of the device were measured and used to extract the device parameters.
 The result shows transistor parameters with threshold voltage of –9 V, ON-OFF ratio of in the range of 103, maximum mobility of 1.15 cm2V-1 s-1, subthreshold slope of in the range of 103 mV/dec, and maximum interface trap density of 1.53x103 (cm-2eV-1) at maximum applied voltage of 5 V.

Heterostructure transistor for an energy-efficient low-noise radiothermograph amplifier based on monolithic integrated circuits

Currently, there is a growing interest in medical practice in such a method of diagnostic human internal organs as microwave radiothermometry. However, a number of strict requirements are imposed on the parameters of radiometric receivers, which are the main elements of a radiothermograph, including the amplification path. The problem lies in the fact that the amplifying path of the radiothermograph consumes, with transistors available on the market, an unacceptably large amount of energy, which leads to an increase in heat generation and, as a result, to the introduction of additional errors in measurements. Therefore, in order to increase the reliability of the radiothermograph, it is necessary to develop a basic transistor for MIC amplifier with reduced power consumption. Using numerical modeling methods, the parameters of an energy-efficient transistor on the proposed heterostructure were researched. As a result of optimizing the transistor design based on the presented strict requirements for the parameters, a calculated steepness characteristic was obtained, clearly showing the increased amplifying properties of the proposed transistor in the low-current region, which directly leads to the possibility of a significant reduction in current consumption of the entire chip. A significant increase in transconductance of the proposed transistor design indicates the possibility of using this promising element base as part of microwave radiometers, which will allow combining the principles of multi-channel, multi-frequency and miniaturization in one radiometric complex and will lead to an expansion of its functionality and a significant reduction in size. The research was carried out with the financial support of the Russian science Foundation in the framework of agreement No. 19-19-00349-П in the theme: “A method and a multichannel multifrequency microwave radiothermography on the basis of monolithic integrated circuits for finding the 3D distribution and dynamics of brightness temperature in the depths of the human body”.

Novel extraction method for contact resistance and effective mobility in carbon nanotube field-effect transistors using S-parameter measurements

In this paper, a novel method is presented for the accurate extraction of key parameters of carbon nanotube field-effect transistors (CNTFETs) using S-parameter measurements. An equivalent circuit model, which utilizes lumped components based on the physical characteristics of the device, is employed to model the AC behavior (S-parameters) of the CNTFETs. The proposed method extracts the bias-dependent contact resistance, channel resistance, and gate-channel capacitance from the model at each gate voltage, thereby facilitating the extraction of the effective mobility of the CNT channel. At the last part of this paper, this method is used to quantitatively investigate the impact of electrostatic doping on CNTFETs. This new methodology offers an effective approach for characterizing CNTFETs, which is an important indicator for device optimization. Additionally, the proposed method can be easily applied to other types of FETs.

Highly Effective and Efficient Self-Assembled Multilayer-Based Electrode Passivation for Operationally Stable and Reproducible Electrolyte-Gated Transistor Biosensors.

To ensure the operational stability of transistor-based biosensors in aqueous electrolytes during multiple measurements, effective electrode passivation is crucially important for reliable and reproducible device performances. This paper presents a highly effective and efficient electrode passivation method using a facile solution-processed self-assembled multilayer (SAML) with excellent insulation property to achieve operational stability and reproducibility of electrolyte-gated transistor (EGT) biosensors. The SAML is created by the consecutive self-assembly of three different molecular layers of 1,10-decanedithiol, vinyl-polyhedral oligomeric silsesquioxane, and 1-octadecanethiol. This passivation enables EGT to operate stably in phosphate-buffered saline (PBS) during repeated measurements over multiple cycles without short-circuiting. The SAML-passivated EGT biosensor is fabricated with a solution-processed In2O3 thin film as an amorphous oxide semiconductor working both as a semiconducting channel in the transistor and as a functionalizable biological interface for a bioreceptor. The SAML-passivated EGT including In2O3 thin film is demonstrated for the detection of Tau protein as a biomarker of Alzheimer's disease while employing a Tau-specific DNA aptamer as a bioreceptor and a PBS solution with a low ionic strength to diminish the charge-screening (Debye length) effect. The SAML-passivated EGT biosensor functionalized with the Tau-specific DNA aptamer exhibits ultrasensitive, quantitative, and reliable detection of Tau protein from 1 × 10-15 to 1 × 10-10 M, covering a much larger range than clinical needs, via changes in different transistor parameters. Therefore, the SAML-based passivation method can be effectively and efficiently utilized for operationally stable and reproducible transistor-based biosensors. Furthermore, this presented strategy can be extensively adapted for advanced biomedical devices and bioelectronics in aqueous or physiological environments.

Improving the Performance of CNN Accelerator Architecture under the Impact of Process Variations

Convolutional neural network (CNN) accelerators are popular specialized platforms for efficient CNN processing. As semiconductor manufacturing technology scales down to nano scale, process variation dramatically affects the chip’s quality. Process variation causes delay variation within the chip due to transistor parameter differences. CNN accelerators adopt a large number of processing elements (PEs) for parallel computing, which are highly susceptible to process variation effects. Fast CNN processing desires consistent performance among PEs; otherwise the processing speed is limited by the slowest PE within the chip. In this work, we first quantitatively model and analyze the impact of process variation on CNN accelerators’ operating frequency. We further analyze the utilization of CNN accelerators and the characteristics of CNN models. We then leverage the PE underutilization to propose a sub-matrix reformation mechanism and leverage the pixel similarity of images to propose a weight transfer technique. Both techniques are able to tolerate the low-frequency PEs and achieve performance improvement at chip level. Furthermore, a novel resilience-aware mapping technique that exploits the diversity in the importance of weights is also proposed to improve the performance. Evaluation results show that our techniques are able to achieve significant processing speed improvement with negligible accuracy loss.

Data-driven voltage/var optimization control for active distribution network considering PV inverter reliability

Fully exploiting the reactive power support capability of the distributed photovoltaic power supply is helpful to solve the problems of voltage fluctuation, voltage overlimit and new energy consumption in the distribution network. However, the reactive power output of the photovoltaic power supply will seriously threaten the reliable operation of the photovoltaic inverter. Therefore, this paper proposes a data-driven voltage-reactive optimization control strategy considering the reliability of the photovoltaic inverter. Firstly, the data-driven model is used to calculate the insulated gate bipolar transistor junction temperature, which improves the calculation efficiency of the insulated gate bipolar transistor junction temperature and reduces the dependence of the evaluation accuracy on the insulated gate bipolar transistor parameters. Then, the voltage-reactive optimization control model of the distribution network considering the reliability of the photovoltaic inverter is established, and the average junction temperature and junction temperature fluctuation of the insulated gate bipolar transistor are introduced into the model optimization goal. The optimization model is transformed into the reinforcement learning task, and then the deep deterministic policy gradient algorithm is used to realize voltage-reactive control. According to the simulation of IEEE 33 node distribution system, the proposed strategy can increase the minimum and average insulated gate bipolar transistor lifetime of all nodes by 6 years and 4 years. At the same time, it can reduce the minimum and average levelized cost of energy of all nodes by 0.1095 $/W and 0.0318 $/W.

EFFECTS OF SCALING OF JUNCTIONLESS TRANSISTOR PARAMETERS WITH SILICON DIOXIDE (SIO2) AND SILICON NITRATE (SI3N4) GATE OXIDES ON THE ELECTRICAL CHARACTERISTICS OF THE DEVICES

This research investigated the effects of scaling of parameters of junctionless transistors (JLT) with SiO2 gate oxide and Si3N4 gate oxide on the electrical characteristics of the two devices. It also compared the electrical performance of the two devices as a way of replacing the conventional SiO2 gate oxide with high-k dielectric such as Si3N4 gate oxide. Different JLT were designed and simulated using a technology computer aided device software, sentaurus and extracted the electrical characteristics such as Threshold voltage, subthreshold slope, drain induced barrier lowering, on-state current etc. It was observed that leakage current, DIBL, SS as well as on-state current were significantly improved using Si3N4 as gate oxide in JLT. As a result, on-state to off-state current ratio was greatly increased, hence the speed of the device. The performance was significantly increased to approximately 109 using Si3N4 material for gate length of 10nm and nanowire diameter of 10nm. All these were achieved because of the high dielectric constant, k of the Si3N4 which is higher than that of SiO2. Similarly, Si3N4 has also has high energy band gap which considerably help in reducing the leakage current and other short channel effects (SCEs).

Improving the accuracy for amplitude and frequency of analytical equation of single-ended ring oscillators based on circuit and transistor parameters

PurposeThis paper aims to find a closed-form expression for the frequency and amplitude of single-ended ring oscillators when transistors experience all regions.Design/methodology/approachIn this paper, the analytical relationships presented for ring oscillator amplitude and frequency are approximately derived due to the nonlinear nature of this oscillator, taking into account the differential equation that governs the ring oscillator and its output waveform.FindingsIn the case where the transistors experience the cut-off region, the relationships presented so far have no connection between the frequency and the dimensions of the transistor, which is not valid in practice. The relationship is presented for the frequency, including the dimensions of the transistor. Also, a simple and approximately accurate relationship for the oscillator amplitude is provided in this case.Originality/valueThe validity of these relationships has been investigated by analyzing and simulating a single-ended oscillator in 0.18 µm technology.