Transistor Parameters Research Articles

Effect of Gamma Radiation on Characteristic of bipolar junction Transistors (BJTs )

This paper describes the effects of 60Cogamma radiation hardness of characteristic and parameters of Bipolar Junction Transistors in order to analyze the performance changes of the individual devices used in nuclear field. Bipolar Junction Transistor (BJT) of the type (BC-301) (npn) silicon, Transistor was irradiated by gamma radiation using 60Cosource at different doses (1, 2, 3, 4, and 5) KGy. The characteristics and parameter of Bipolar Junction Transistor was studied before and after irradiated by using Transistor Characteristics Apparatus with regulated power supplies. Obtained result showed that, the saturation voltage VCE(sat) of Bipolar Junction Transistor decreased because of the gain degradation of the transistor and increased silicon resistivity, Another parameter of a bipolar junction transistor affected by ionizing radiation is a collector-base leakage current, a strong increase of the current is caused by the build-up charge near the junction.

Analysis of the Electrical Parameters of SOI Junctionless Nanowire Transistors at High Temperatures

This work studies the effects of the temperature variation, from 300K to 500K, on the electrical parameters of SOI n-type and p-type junctionless nanowire transistors. The temperature influence on the threshold voltage, subthreshold slope, and the effective carrier mobility were analyzed. The mobility scattering mechanisms were analyzed and show that nanowire devices have the phonon scattering as their major component, although there is a significant component of the ionized impurity scattering that can be identified as well. These electrical parameters were also analyzed for short channel devices with a channel length of 40nm. P-type devices showed higher degradation with the temperature as the doping concentration is higher than n-type devices.

Bandwidth Analysis of a Broadband Amplifier with Two-Stage Matching System Using the Smith Chart

This paper describes a novel trace structure for the analysis and design of two-stage Broadband Frequency Low Noise Amplifiers based on standard Smith chart procedures and program algorithm realization. The method allows to put the transistor's S-parameters and details of the source and load networks and to interactively explore the effects of these quantities on design variables such as gain, noise figure and stability. It also facilitates the design of two-element matching networks to transform the source and load impedances to optimum values to achieve the desired gain and noise performance. The extended Smith chart concept is proposed to enable the advanced graphical interpretation of devices containing complex properties. This methodology is based on the Smith chart concept, and makes it easy to deal with devices containing signal sources, nonlinearity, very high Q factors and negative resistances. The concept of explaining the use of the Smith chart in combination with using modern tools as MATLAB scripts is exemplified in graphical forms. Phyton-based program contains the algorithm for parameters calculation. It explains the procedure that must be used to solve the two-stage impedance-matching problem. The point of this proposal is using of Smith chart plane for the graphical processing for its application to oscillator analysis. To demonstrate the effective usage of this methodology an interpretation and analysis of the oscillator, especially in terms of gain, noise and stability, are provided. The practical relevance concludes results of multistage design using impedance matching LC networks for the intersection level. The values of the parameters of the integrated microcircuit confirm the possibility of using the calculation methodology considered in the paper. The proposed solution is validated with extensive RF measurements at 3.5 GHz and is benchmarked against several frequency ranges for noise, stability and gain values. The methodology shown in the paper can be used in the development and design of modern microwave amplifiers, as well as for research and analysis of the efficiency of existing devices.

МЕТОД КОНТРОЛЯ ТЕМПЕРАТУРЫ IGBT КРИСТАЛЛА В РЕЖИМЕ РЕАЛЬНОГО ВРЕМЕНИ

The work is devoted to the study of temperature–sensitive parameters of power IGBT transistors. A method for measuring IGBT temperature based on temperature–sensitive parameters is considered. An experimental estimate of the temperature dependence of the temperature–sensitive parameter Rgint.

Characteristics Modeling of GaN Class-AB Dual-Band PA Under Different Temperature and Humidity Conditions

As the technology scales down, besides the CAD tools and design guidelines, understanding circuit performance degradation as a consequence of transistor degradation becomes essential for designers. Due to several adverse environmental conditions, the study of performance degradation in the power amplifier (PA) is very demanding research. In this paper, an RF PA is experimentally studied to observe various characteristic degradations in a broad range of operating temperature and humidity conditions. Based on a few key measurement points, a measurement-based modeling method is proposed to help designers make intelligent decisions to minimize the performance degradation effects. This method uses four two-dimensional interpolation models, and the results show that the prediction results of the four planar interpolation models are in good agreement with the measurement results. The results presented in this article help select design models for the RF power amplifier that can analyze the performance degradation of the transistor parameters in advance. Cubic and spline interpolation has the highest model accuracy among the four two-dimensional models, while the nearest interpolation offers the shortest training time.

Aging in CMOS RF Linear Power Amplifiers: An Experimental Study

An extensive experimental analysis of the hot carrier injection (HCI) and bias temperature instability (BTI) aging effects on RF linear power amplifiers (PAs) is presented in this article. Two different 2.45-GHz PA topologies have been implemented in a CMOS 65-nm technology: one based on a classical common-source (CS) and choke inductor and another one based on a complementary current-reuse (CR) circuit, both of them producing similar gain and output 1-dB compression point (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1dB</sub> ). These circuits have been stressed to produce accelerated aging degradation, by applying increasing supply (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) voltages or increasing RF input powers (PIN). The degradation on the transistor parameters (threshold voltage and mobility), dc bias point (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> current), and RF performance (gain, matching, and compression point) has been simultaneously measured. This has allowed us to observe how the reduced transistor degradation in CR PA results in higher robustness in its RF parameters compared with the CS PA circuit. The equivalent root-mean-square (rms) voltages have been proposed as an observable metric to assess the combined dc + RF stress in a PA circuit. This has been applied to a semianalytical model, providing comprehension of the link between the conditions under which a circuit is operated, the degradation of the transistor parameters, and the effects on the dc current and RF performance.

Development of a robust fabrication process for single silicon nanowire-based omega gate transistors on polyamide substrate

Single silicon nanowire (SiNW) omega-gate field-effect transistors have been fabricated using a standard photolithography method on a Kapton flexible polyamide thin film attached to a sacrificial silicon substrate. SiNWs have been grown by the chemical vapor deposition method using a vapor–liquid–solid mechanism and gold as the catalyst. A key step for proper SiNW integration, Kapton surface flattening, was performed via an innovative method based on soap. Contrary to a previously reported integration process on flexible substrates, this flexible/rigid hybrid substrate is compatible with temperature as high as , allowing the formation of low-resistive nickel silicide at the source/drain contacts. As a consequence, our devices can exhibit excellent electrical properties such as hole mobility, 105 ratio and subthreshold slope of about . These parameters can compete with those of organic transistors or in some aspects even exceeding electrical parameters of similar single SiNW transistors fabricated onto flexible substrates. In addition, after separation from the rigid silicon substrate, devices on Kapton experience a significant improvement in their performance, such as two orders of magnitude for ratio and halving the subthreshold slope. This flexible/rigid hybrid substrate, offering high chemical and thermal stability, as well as preserving good electrical features and even improving them, after detaching and transfering the polyamide layer to a plastic substrate, which opens up a new route for the integration of further nanostructures.

Design and Implementation of a pH Sensor for Micro Solution Based on Nanostructured Ion-Sensitive Field-Effect Transistor.

pH sensors based on a nanostructured ion-sensitive field-effect transistor have characteristics such as fast response, high sensitivity and miniaturization, and they have been widely used in biomedicine, food detection and disease monitoring. However, their performance is affected by many factors, such as gate dielectric material, channel material and channel thickness. In order to obtain a pH sensor with high sensitivity and fast response, it is necessary to determine the appropriate equipment parameters, which have high processing cost and long production time. In this study, a nanostructured ion-sensitive field-effect transistor was developed based on the SILVACO technology computer-aided design (TCAD) simulator. Through experiments, we analyzed the effects of the gate dielectric material, channel material and channel thickness on the electrical characteristics of the nanostructured field-effect transistor. Based on simulation results, silicon nitride was selected as the gate dielectric layer, while indium oxide was chosen as the channel layer. The structure and parameters of the dual channel ion-sensitive field-effect transistor were determined and discussed in detail. Finally, according to the simulation results, a pH sensor based on the nanostructured ion-sensitive field-effect transistor was fabricated. The accuracy of simulation results was verified by measuring the output, transfer and pH characteristics of the device. The fabricated pH sensor had a subthreshold swing as low as 143.19 mV/dec and obtained an actual sensitivity of 88.125 mV/pH. In addition, we also tested the oxidation reaction of hydrogen peroxide catalyzed by horseradish peroxidase, and the sensitivity was up to 144.26 pA mol−1 L−1, verifying that the ion-sensitive field-effect transistor (ISFET) can be used to detect the pH of micro solution, and then combine the enzyme-linked assay to detect the concentration of protein, DNA, biochemical substances, biomarkers, etc.

New Approach for Designing and Optimally Selecting the Parameters of Graphene nano-ribbon Transistors in the Presence of Process Variation

GNRFET Graphene Nano-Ribbon Field-Effect Transistor is sensitive to geometric parameters. Therefore, changing parameters circuit characteristics can be improved or degraded. In this study, we propose a new approach to optimizing the GNRFETs. The effect of geometric and process parameters such as chirality, channel length, width, line edge roughness, oxide thickness, and doping on characteristics of an inverter gate is investigated based on GNRFET. Analysis of power consumption, delay, PDP, and SNM results indicate that GNRFETs adjustable parameters can significantly affect circuit performance. It is shown that SNM increases by changing channel length and width. Moreover, by reducing the channel length from 20 nm to 10 nm, delay for chirality (6,0) decreases by 50%, and delay for chirality (10,0) decreases by 53%. By increasing the Line Edge Roughness by 20%, power consumption for chirality (10,0) and chirality (6,0) increases by 18% and exponentially, respectively. Also, by decreasing the oxide thickness, SNM and power consumption are increased; however, the delay behaves differently with chiralities (6,0) and (10,0). This research demonstrates the importance of accurately determining the GNRFET adjustable parameters according to the design aims. A set of recommendations is provided for optimal parameters needed by digital circuit designers to use GNRFET in their design optimally.

Impact of channel length and width for charge transportation of graphene field effect transistor

The effect of channel length and width on the large and small-signal parameters of the graphene field effect transistor have been explored using an analytical approach. In the case of faster saturation as well as extremely high transit frequency, the graphene field effect transistor shows outstanding performance. From the transfer curve, it is observed that there is a positive shift of Dirac point from the voltage of 0.15 V to 0.35 V because of reducing channel length from 440 nm to 20 nm and this curve depicts that graphene shows ambipolar behavior. Besides, it is found that because of widening channel the drain current increases and the maximum current is found approximately 2.4 mA and 6 mA for channel width 2 µm and 5 µm respectively. Furthermore, an approximate symmetrical capacitance-voltage (C-V) characteristic of the graphene field effect transistor is obtained and the capacitance reduces when the channel length decreases but the capacitance can be increased by raising the channel width. In addition, a high transconductance, that demands high-speed radio frequency (RF) applications, of 6.4 mS at channel length 20 nm and 4.45 mS at channel width 5 µm along with a high transit frequency of 3.95 THz have been found that demands high-speed radio frequency applications.

Effect of Gaussian Disorder on Power-Law Contact Resistance and Mobility in Organic Field-Effect Transistors

We study the effect of Gaussian energetic disorder on the organic field-effect transistors (OFETs) with surprisingly high field-effect mobility and the low contact resistance. The numerical device simulation assumes the thermally assisted hopping transport and injection in disordered semiconductors. The results are analyzed with the power-law field-effect mobility and the asymptotic power-law contact resistance model. Transistor parameters extracted by the models reveal that a higher Gaussian disorder, which leads to a lower injection barrier and a larger mobility enhancement, is the origin of the high field-effect mobility and the low contact resistance.

DEVELOPMENT OF A METHOD FOR DETERMINING THE MAXIMUM ACHIEVABLE GAIN (TRANSMISSION) KmS

Increasing the level of semiconductor devices, improving their characteristics significantly affects the potential stability in a wide range of frequencies. Classical methods and standard measuring equipment are not designed to measure the parameters of potentially unstable transistors. Measuring systems are excited uncontrollably, which increases the measurement error. Therefore, today there is an urgent task of measuring the parameters of both transistors in particular and quadrupoles in general, in the frequency range of potential instability. The clock frequency at which modern computer equipment works is close to the microwave range (ultrahigh frequencies), which makes the problem of measuring and calculating the various functional units of the computer quite relevant. The development of new methods and means of measuring the parameters of potentially unstable quadrupoles in the microwave range is an important scientific field that can significantly improve the accuracy of their measurement on standard equipment. The conducted researches and the developed technique allow to increase accuracy of measurement of parameters of four-poles and to provide stability of experimental installation at measurement of parameters of any four-pole. The proposed methods are more efficient and solve the problem of measuring the S-parameters of potentially unstable quadrupoles in the microwave range. The parameters of the quadrupole have the dimensions of the elements of standard W-parameters, their measurements are performed in the microwave range with an error of less than 5%, and to a lesser extent depends on the coefficient of stability of the measuring path than when measuring S-parameters. When measuring the parameters of the quadrupole, there is no need to use the modes of short circuit and XX or make measurements with a coordinated measuring path, which allows to increase the measurement accuracy and ensure stability when measuring potentially unstable quadrupoles with Ks&gt; 0.

Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction in Junction FETs

In this brief, extraction methods are proposed for determining the essential parameters of double gate junction field-effect transistors (FETs). First, a novel method for determining free carrier effective mobility, similar to a recently proposed method for MOSFETs, is developed. The same method is then extended to cover also the case when series resistance is present, while series resistance itself may be determined from the measurement from two FETs with different channel lengths. The key technological and design parameter is the threshold voltage, which may be unambiguously determined from the transconductance-to-current ratio with a constant-current method. The new methods are shown to be effective over a wide range of technical parameters, using technology computer-aided design simulations.

Random offset minimization in low frequency front-end amplifiers using swarm intelligence based techniques

Random offset in amplifiers arises mainly due to random variations i.e. inherent mismatch in transistor parameters and greatly impacts its overall design specifications, especially in case of low frequency application. It must be minimized for high precision in the amplifier’s performance. A new approach for minimization of random offset voltage in amplifiers has been proposed through the use of swarm intelligence based optimization algorithms due to their derivative free nature and easy search mechanism. The approach involves firstly, modelling the random offset voltage due to mismatch between transistors parameters based on Pelgrom’s model and then minimizing the formulated model subjected to design constraints using swarm intelligence based algorithms. Two case studies are considered, firstly, a high swing Folded Cascode Operational Transconductance Amplifier (OTA) and secondly, a Recycling Folded Cascode (RFC) OTA. Comparative analysis have been performed by recording best, worst and mean data for 2500 function evaluations and also using statistical analysis such as Friedmann’s test and Mann–Whitney’s U test. The results indicate that the Hybrid Whale Particle Swarm Optimization (HWPSO) algorithm outperforms the other state of the art algorithms by giving a minimum random offset voltage of 7.2 mV and 1.452 mV with a mean rank of 1.55 and 1.75 for the 1st and 2nd case studies respectively. Validation of HWPSO results have been done by performing simulations and Monte Carlo Analysis for the two amplifiers in Cadence Virtuoso, which are found to be in close agreement with the algorithmic results.

INCREASING RADIATION RESISTANCE OF MEMORY DEVICES BASED ON AMORPHOUS SEMICONDUCTORS

A memory cell structure is proposed that uses a Schottky barrier thin film transistor based on an amorphous semiconductor as a junction element, and a chalcogenide glassy semiconductor film as a switching element. A physical storage cell model has been developed. The dependence of the transistor and memory cell parameters on the dose of neutron flux and γ - quanta was investigated. It is shown that when the dose of neutron irradiation is changed, the steepness of the drain-gate characteristic (DGC) decreases by 10% at a dose of the order of 1015 n/s, at the same time, the transfer coefficient of the bipolar n-p-n transistor decreases by 20% already at doses of 1013 n/s, indicating a significant increase in the radiation resistance of the proposed memory cell. In the case of irradiation with γ - quanta in the range up to 2.6 MRad, the steepness of the DGC of the proposed structure changes by only 10%. When used as an isolation element, a field-effect transistor with an insulated gate, the slope of the DGC is reduced by 50%. It is shown that the current of recording information of the proposed structure when changing the dose of γ - quantum flux to 2.6 MRad changes by about 10%, at the same time, in the case of using a field-effect transistor with an isolated cover, the information recording current changes by 50%. The study of the dependence of the gate current on the dose of γ – quanta is showed. When the radiation dose changes from 0 to 2.6 MRad, the gate current changes only by 10%, which indicates the high resistance of the proposed structure to the action of permeable radiation. Also, studies of the dependence of the conductivity of single-crystal semiconductors on the radiation dose ɣ by quanta and neutron flux show that a significant increase in the specific resistivity of AS occurs at doses 2-3 orders of magnitude larger than in the case of single-crystal n-type conductivity semiconductors.

Wafer-scale carbon nanotube network transistors

Highly purified, preseparated semiconducting carbon nanotubes (CNTs) hold great potential for high-performance CNT network transistors due to their high electrical conductivity, high mechanical strength, and room-temperature processing compatibility. In this paper, we report our recent progress on CNT network transistors integrated on an 8-inch wafer. We observe that the key device performance parameters of CNT network transistors at various locations on an 8-inch wafer are highly uniform and that the device yield is impressive. Therefore, this work validates a promising path toward mass production and will make a significant contribution to the future field of wafer-scale CNT electronics.

CALCULATION OF NON-STANDARD W-PARAMETERS OF FOUR-POLE ON BIPOLAR TRANSISTORS

Improving the performance of microwave devices can be achieved both through the use of a fundamentally new element base, and through the use of new circuit designs. In this respect, the direction of use of the reactive properties of transistors as well as transistor structures with negative resistance for the construction of information-measuring systems and operating and computing devices of the microwave range is promising in this respect. In order to confirm the proposed methods, it is necessary to compare the results of the experimental studies using the proposed methods and means of measuring the W-parameters of real potentially unstable four-poles. As such four-poles it is proposed to use bipolar and transistors with a wide range of frequencies of potential instability. The paper develops mathematical models of W-parameters of such structures and evaluates their parameters in the frequency range. The active four-pole is a transistor model. Its W parameters can be determined either experimentally - for specific conditions or calculated - by using a physical transistor replacement circuit. In most cases, the calculation path is more acceptable because it allows to obtain analytical expressions for the four-pole, it is important in the analysis of the influence of various factors on the characteristics of the scheme under study. The inertial properties of the transistor are already manifested at relatively low frequencies and must be taken into account in practically the entire operating range of the transistor. The theoretical model holds up to frequencies f  2fт (where ft is the limit frequency) [1,3]. At higher frequencies, it is necessary to consider the parasitic reactive parameters of real transistors, first of all, the inductance of the terminals. A physically T-equivalent equivalent transistor replacement scheme was proposed by Pritchard in a simplified version [4]. It has several varieties, differing in the configuration of the circuit consisting of the resistance of the base material and the capacity of the collector junction. If we carefully consider and compare the T and U-shaped circuits of the transistor substitution, it can be noticed that they differ only in the configuration of their inne r part - the theoretical model. At high frequencies P and T, such circuits are not exact mutual equivalents. This is due to the approximation used in the transition from one circuit to another. However, the frequency characteristics of the circuits are very close. Each of them models the processes in the transistor with approximately the same accuracy, and in this sense they are equivalent.

Analysis of MIS-HEMT Device Edge Behavior for GaN Technology Using New Differential Method

A new differential method for accurate extraction of electrical parameters of high-electron mobility transistor (HEMT) devices for gallium nitride (GaN) technology is proposed. This method, presented here for the first time, is used to study the mobility degradation with gate length, allowing an analysis of the contribution of the gate edge region to the total metal-insulator semiconductor (MIS)-HEMT device conductance. First, an analytical model is proposed to account for the relative conduction of the edges and the main flat part of the channel HEMTs. Second, the differential method allows the split-CV mobility extraction of each part, allowing a precise analysis of the resistive contribution of each region of the HEMT devices. This study has been performed over a large range of channel lengths for two normally OFF HEMT GaN wafers having different recess depths.

High yield manufacturing of fully screen-printed organic electrochemical transistors

The potential of the screen printing method for large-scale production of organic electrochemical transistors (OECTs), combining high production yield with low cost, is here demonstrated. Fully screen-printed OECTs of 1 mm2 area, based on poly(3,4-ethylenedioxythiophene) doped with poly(styrensulfonate) (PEDOT:PSS), have been manufactured on flexible polyethylene terephthalate (PET) substrates. The goal of this project effort has been to explore and develop the printing processing to enable high yield and stable transistor parameters, targeting miniaturized digital OECT circuits for large-scale integration (LSI). Of the 760 OECTs manufactured in one batch on a PET sheet, only two devices were found malfunctioning, thus achieving an overall manufacturing yield of 99.7%. A drain current ON/OFF ratio at least equal to 400 was applied as the strict exclusion principle for the yield, motivated by proper operation in LSI circuits. This consistent performance of low-footprint OECTs allows for the integration of PEDOT:PSS-based OECTs into complex logic circuits operating at high stability and accuracy.

Systematic method for studying single-electron transistors

We present a thorough classification of the electronic transport patterns of single-electron transistors (SETs) using a two-letter notation, based on the symmetry properties of SETs and a nondimensionalization procedure. We find five unique symmetry types of SETs: one symmetric and four asymmetric. For these types and the corresponding dimensionless transistor parameter sets, denoted by the two-letter scheme, we calculate and compare current–voltage curves, modulation curves, charge stability diagrams, and the average and standard deviation of the number of excess electrons on the transistor island. The simulation is performed using the mean of the recurrent solution method for the system of kinetic equations for the charge probability distribution function. On the basis of the simulation results, we analyze the properties of asymmetric SETs. We also consider the effect of asymmetry in the transistor bias voltage and show that this effect can be compensated by renormalization of the left and right junction capacitances. In addition, we propose a measurement technique that can be used to determine the voltage bias asymmetry ratio in real experiments. Finally, using the Bardeen approximation for the tunnel matrix element and the parallel-plate capacitor approximation, we estimate the geometric features of the tunnel junctions.