Parallel Pipelined Architecture Research Articles

Genetic neural network based background calibration method for pipeline ADC

This article presents a pipeline analog-to-digital converter (ADC) background calibration method that combines genetic algorithm (GA) and neural network (NN) algorithm. The proposed method uses ADC outputs or individual stage sub-ADC outputs for NN training, employs GA for global optimization of the NN's initial setup to avoid local optima traps, and utilizes a parallel pipeline architecture to create a high-throughput calibration circuit with optimized multiply-accumulator (MAC) to minimize resource consumption. Through simulation on a 6-stage 14-bit pipelined ADC model, the proposed method demonstrated superiority over traditional calibration techniques and other NN-based calibration strategies. Specifically, after calibration, the signal-to-noise ratio (SNDR), spurious-free dynamic range (SFDR), and effective number of bits (ENOB) are significantly improved from 57.72 dB, 59.77 dB, and 8.79 bits to 104.61 dB, 152.64 dB, and 17.08 bits, respectively.

A Compact Hardware Architecture for Bilateral Filter With the Combination of Approximate Computing and Look-Up Table

Bilateral filter (BF) is a widely applied method for image denoising due to the characteristic of edge-preserving. This brief presents a super-compact hardware architecture for the BF by a piecewise approximate computing algorithm. The contributions are summarized as follows: 1) The architecture significantly reduces the storage and the arithmetic logic for the piecewise approximated filter weights and can attain comparable smoothy and edge-preserving performance to the standard BF. 2) The BF is accelerated by the parallel pixel-level pipeline architecture and the LUT-based divider for normalization. 3) The synthesized result shows that this architecture, even on a low-cost XINILX Zynq-7000 FPGA, can reach real-time denoising at more than 30 frames/second for 8M-pixel ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3268 \times 2448$ </tex-math></inline-formula> ) videos at the maximum working frequency of 278 MHz with the power dissipation of only 168 mW.

Parallel Pipelined Architecture and Algorithm for Matrix Transposition Using Registers

Parallel Pipelined Architecture and Algorithm for Matrix Transposition Using Registers

Time-Division-Multiplexed Online Gauss-Newton-Based Multi-Echo Decomposition Method for Real-Time In-Situ Laser Ranging

In forestry and agriculture investigations, the laser spot of FW-LiDAR may simultaneously illuminate multiple targets, which reflect multiple echoes. To realize the real-time in-situ laser ranging of multiple targets, a time-division-multiplexed online Gauss-Newton-based multi-echo decomposition method (GMOT) is proposed for decomposing the multi-echo in an online manner. In waveform preprocessing, a local-region linear analysis method was employed in GMOT to recognize the echo components of multi-target. Gauss-Newton method was then used to decompose the multi-echo by fitting the waveform. In the waveform fitting, a sparse Jacobi matrix was employed to improve the target extraction ratio. Due to the ability of the parallel computation, a Kintex-7 FPGA was employed as the hardware platform. GMOT was implemented on the embedded FPGA with the parallel-pipeline architecture and time-division multiplexing method to improve the measurement rate for decomposing the multi-echo in real-time. Simulations proved that GMOT achieves a measurement rate of 238.1 kHz, approximately 3.5 times as fast as online Gauss-Newton-based multi-echo decomposition method. An FPGA-based in-situ ranging system was built to evaluate the ranging performance of GMOT by experiments. The results revealed that GMOT increases the target extraction ratio by 11.4%, compared with the Gauss-Newton-based multi-echo post-processing decomposition method (GMP). The ranging error of GMOT is on the same scale of GMP. The proposed method will be used for the real-time multi-target ranging in the forestry survey and intelligent driving.

Real-Time In-Situ Laser Ranging via Back Propagation Neural Network on FPGA

To increase the measurement rate and reduce the ranging error of real-time in-situ laser ranging in full-waveform light detection and ranging (LiDAR), a back propagation (BP) neural network-based online ranging method (BPO) implemented on FPGA is proposed. In BPO, a three-layer BP neural network model is trained and implemented on a Virtex-6 FPGA to estimate the parameters of laser pulses for ranging in real time. The training dataset is generated using the multi-pulse coherent average method combined with the B-spline interpolation method. In the implementation of BPO, the parallel-pipeline architecture is employed to accelerate the computational process. Simulations proved that BPO decreased the time consumption of a single measurement to $2.95~\mu \text{s}$ . The measurement rate was increased to 339 kHz by BPO, which was approximately as 1.2 times as the measurement rate of Gauss-Newton-based online ranging method (GNO). Experiments were conducted by an FPGA-based in-situ ranging system to evaluate the ranging error of BPO. The results revealed that the mean and standard deviation of ranging errors of BPO were 0.8 mm and 1.4 cm for a laser pulse with an SNR of 36.4 dB, respectively. For a laser pulse with an SNR of 21.8 dB, the mean and standard deviation of ranging errors of BPO were 1.7 cm and 5.5 cm, which decreased 0.8 cm and 1.7 cm from those of GNO, implying that the proposed method is capable of mapping the trailing laser pulse and reducing the ranging error caused by the trailing distortion.

Design of Optimized Radix-4 FFT Processor with Multiplier Sharing Method

To implement the parallel pipelined FFT architecture in OFDM applications. The OFDM has developed in wide band Digital communication. The radix4 algorithm can achieve to reduce the half computational steps compare than the radix2 algorithm and R4MDC is reduces the slices and power consumption than the single path delay feedback. It can be converted into real and imaginary values. To reduce the twiddle factor complexity by using the bit parallel multiplier. It can be exploits the constant twiddle factor when the twiddle factor multiplicatier relocate the twiddle factor multiplications in timing process. The changes can be appeared in multiplications so have to perform the TF at clock signals in two ways data path.

Online Gauss–Newton-Based Parallel-Pipeline Method for Real-Time In-Situ Laser Ranging

To increase the measurement rate of real-time in-situ laser ranging, an online Gauss-Newton-based parallel-pipeline method (GNPPo) is proposed to extract waveform parameters. The proposed method includes waveform pre-processing for initial estimation, variable substitution for fast computation, and Gauss-Newton method for optimization. In waveform pre-processing, parallel-pipeline architecture was used to obtain initial values of waveform parameters as input for Gauss-Newton method. In the variable substitution, the initial values were transformed to reduce the number of divisions and accelerate Jacobi matrix calculation. To obtain the optimized waveform parameters, adjoint matrix method was used to calculate the iteration vector in Gauss-Newton method. The optimized waveform parameters required inverse transformation by variable substitution for accurately calculating the distance. The proposed method employed parallel-pipeline architecture, implemented on Kintex-7 FPGA. Simulations first proved that the proposed method decreased time cost and increased the occupied computational resource. Extensive experiments were conducted using a lab-built full-waveform ranging system. In comparison with the online Gauss-Newton-based pipeline method (GNPo) and the Gauss-Newton-based post-processing method (GNp), experimental results revealed that the proposed method realizes a range measurement rate of 285.7 kHz, approximately 2.5 times and 49 times as fast as GNPo and GNp, respectively. The mean range error and range standard deviation of GNPPo are 0.6 cm and 1.7 cm, at a distance of 21 m with an SNR of 36.6 dB, roughly the same scale of GNp, and a millimeter-scale increase of GNPo. The proposed method will be used for LiDAR application on autonomous vehicles with real-time centimeter accuracy.

PARALLEL PIPELINED MULTI RADIX VARIABLE LENGTH FAST FOURIER TRANSFORM ARCHITECTURE

There is an enormous demand for high speed data communication or high speed internet using Long Term Evolution (LTE) or LTE-Advanced communication methods. To achieve the high speed data rate in the receiver side, it is necessary to achieve high throughput in the Fast Fourier transform (FFT) architecture. Hence there is demand to improve the throughput of the FFT architectures used for high speed data communication. The FFT architecture is designed and optimized for LTE-A applications. However, the high throughput has been achieved by sacrificing hardware resources of the Field Programmable Gate Array (FPGA). Many fixed and variable length FFT processors are proposed by the researchers with improved performance focusing either on algorithmic modifications, novel architectural optimizations or radix selection. Among these FFT processors, the goal and main objectives of this paper are: 1. To design and implement a pipelined FFT architecture to give high throughput for LTE-A MIMO applications 2. To develop an intellectual property (IP) core for FFT computation with variable FFT size 3. To propose a parallel implementation to increase the performance of LTE-A baseband processing system. In an Orthogonal Frequency Division Multiplexing (OFDM) baseband communication system, FFT operation is one of the highest computationally serious tasks which directly influence the communication system performance factor. The baseband hardware has to be capable as well as efficient enough to calculate FFT in specific timing restrictions. Thus, the parallel pipelined multi radix Variable Length FFT architectures for LTE-A Multiple-Input-Multiple-Output (MIMO) applications have been designed. The proposed FFT architecture delivers a throughput of 550 MSPS at the maximum clock rate of 550 MHz. The proposed FFT support the FFT length of 64, 128, 256, 512, 1024 and 2048 for LTE-Advanced MIMO standard. The proposed FFT architecture has been implemented in Xilinx Artix-7 FPGA device and the performance metrics have been analysed. Even though the proposed FFT architecture consumes additional Block-RAMs (BRAM) and quite an amount of Xilinx-Xtreme Digital Signal Processor (DSP)/ DSP48 resources, the Power Delay Product (PDP) of the proposed FFT is excellent compared to the existing FFT architectures. The proposed multi radix mixed 2/3/5 parallel pipelined 2048 point FFT architectures exhibits very less latency of 11.382 µs at 550 MHz clock frequency compared to the existing system with the latency of 56.88 µs at 200 MHz clock frequency. Moreover, the designed FFT architecture utilizes 96 Xilinx Xtreme DSP blocks 25040 clock cycles to complete the FFT operation with an excellent throughput of 2200 MSPS with FFT computation time of 45.528 µs at the clock frequency of 550 MHz for the 4x4 MIMO- OFDM architecture. Therefore, the designed FFT provides high throughput rate in order to meet the modern wireless standard specifications. The proposed FFT architecture outperforms well in terms high throughput, low latency and better PDP with extra hardware as trade-off for both for Single FFT and for MIMO technology.

Analysis of 32 × 32-Bit Parallel Pipeline Multiplier Using In-Built Register Transfer Level Testing Approach

This paper presents a design and implementation of Fixed Point Ultra High Throughput Multiplier (UHTM) using parallel pipeline architecture for both signed and unsigned numbers to improve the throughput of the VLSI SoC design. Here backend issues are addressed in the front end RTL design itself hence this reduces the testing time by detecting all possible defects. In this paper RTL coding style is realized with respect to FPGA design. In an FPGA design inbuilt DSP blocks is used for arithmetic (multiplication) operations which will achieve the higher frequency of operation. In addition power and timing optimization techniques are also addressed to reduce dynamic power. The multiplier hardware design of 32×32 bit UHTM is synthesized in FPGA and compared with the previous works. As a result of this, 32×32 multiplier achieves the throughput of 15552 Mbps at 243 MHz, 64 bits per clock cycle output in FPGA and 32 Gbps at 1.2 GHz, 64 bits per clock cycle in ASIC, obtains the best hardware efficiency in terms of area in the FPGA area utilization of 1264 ALUTs, 2811 FFs in the Cyclone V5CSXFC6D6F3117 device with First in First out latency of ten clock cycles at the rate of 243 MHz clock frequency. The Structural realization and analysis pertaining to timing, area and power are implemented in Cyclone V 5CSXFC6D6F3117 FPGA and ASIC 28 nm technology.

A New Automatic Real-Time Crop Row Recognition Based on SoC-FPGA

With the development of artificial intelligence technology, agricultural robot plays a significantly important role for agricultural intelligence. Crop row line detection is a critical and fundamental step for agricultural robot navigation. Although there are some crop row lines detection methods, few of them can meet the real-time requirement for agricultural robot under complex fields conditions. In view of this, a real-time crop detection system implemented on a SoC FPGA (System-on-a-Chip Field Programmable Gate Array) is first proposed in this paper, which contains crop segmentation and crop row detection, where we design parallel pipeline architecture to enhance real-time performance by using line buffer and sliding windows technologies. At the same time, the fixed point representation is used to reduce the memory resource in this system. The proposed system is evaluated and implemented on Xilinx Zynq UltraScale+ MPSoC ZCU102 SoC-FPGA. The experimental results show that the proposed system can process an image with 1920×1080 resolution only within 210 ms with the average accuracy of 89.7%, which satisfies the real-time requirements of the crop rows recognition.

FPGA Implementation of Predictive Cascaded Speed and Current Control of PMSM Drives With Two-Time-Scale Optimization

This paper proposes a field programmable gate array (FPGA) implementation of predictive speed and current control of permanent magnet synchronous motor (PMSM) with two-time-scale optimization. Considering the time-scale characteristics of speed loop and current loop, different sampling times are assigned to the subsystems. The predictions of both slow and fast models consuming great computation resource for all the prediction instants are analyzed in two-time-scale system. In order to achieve a fast and accurate predictive control, the proposed method is implemented on an FPGA. Parallel unrolling and maximized parallel pipeline architecture are designed specifically to optimize the computational time of the proposed method. Experimental results validated in PMSM drives illustrate that proposed implementation achieves a high performance with balanced resource consumption.

System-on-a-chip (SoC) FPGA-based Hardware Acceleration for Green Crop Segmentation

With the development of artificial intelligence technology, agricultural robot plays a significantly important role for agricultural intelligence. Crop segmentation is a critical and fundamental pre-processing step for agricultural robot navigation and crop growth monitoring. Although there are several crop segmentation methods, they cannot meet the online real-time requirement for agricultural robot. In view of this, a real-time crop segmentation system implemented on a SoC-FPGA is first proposed in this paper, which contains image loading module, segmentation algorithm module and image display module. As a core module, segmentation algorithm module consists of greenness identification, thresholding operation and morphological operation. Its hardware implementation adopted a parallel pipeline architecture to enhance real-time performance. The proposed system is implemented on a Xilinx Zynq-7000 FPGA and the experimental results showed that it can achieve a frame rate of 60 frames per second for the image resolution of 1920×1080 with the average accuracy of 91%.

Reinforcement design of radar pulse compression algorithm in space‐borne environment

Realising radar high-speed real-time signal processing under the space-borne environment is a worldwide research difficult point. Commercial Quartus devices required for high-speed processing are hardened and consolidated in high radiation environments. This study realises high-speed real-time radar signal processing in space-borne environment for doing the reinforced design of commercial Quartus chip for pulse compression algorithm. The article first analysed the failure modes of high-performance FPGAs in a space-borne environment in China: a highly efficient parallel pipeline architecture with 8-8 K points is designed; control registers, state machine registers, on-chip RAM, and other easy-to-flip positions have been fully reinforced for the pulse compression algorithm. The system realises 200 M real-time processing capability after integration. Single-event fault injection tests were performed on key signals such as system control, and the test results verified the effectiveness of the reinforcement. The fault tolerance of the system has been significantly improved to ensure the normal operation of the FPGA.

LiveCap

We present the first real-time human performance capture approach that reconstructs dense, space-time coherent deforming geometry of entire humans in general everyday clothing from just a single RGB video. We propose a novel two-stage analysis-by-synthesis optimization whose formulation and implementation are designed for high performance. In the first stage, a skinned template model is jointly fitted to background subtracted input video, 2D and 3D skeleton joint positions found using a deep neural network, and a set of sparse facial landmark detections. In the second stage, dense non-rigid 3D deformations of skin and even loose apparel are captured based on a novel real-time capable algorithm for non-rigid tracking using dense photometric and silhouette constraints. Our novel energy formulation leverages automatically identified material regions on the template to model the differing non-rigid deformation behavior of skin and apparel. The two resulting non-linear optimization problems per frame are solved with specially tailored data-parallel Gauss-Newton solvers. To achieve real-time performance of over 25Hz, we design a pipelined parallel architecture using the CPU and two commodity GPUs. Our method is the first real-time monocular approach for full-body performance capture. Our method yields comparable accuracy with off-line performance capture techniques while being orders of magnitude faster.

Self adaptable high throughput reconfigurable bilateral filter architectures for real-time image de-noising

A bilateral filter is a local, non-iterative and non-linear technique which aids in removing the noise while preserving edges and details. This work proposes novel highly parallel-pipelined low complex bilateral filter architectures to achieve high throughput, high efficiency, self adaptability and reconfigurability in a real-time noisy environment. The design implements true bilateral filter by adaptively varying the filter parameters to achieve error tolerance less than \(4\%\). The proposed architecture can denoise up to 4K UHD (2160 p @ 53 fps) video stream at real-time. The design improves the throughput by \(88\%\), reduces resource utilization and latency by 30 and \(60\%\) respectively than the state of the art architectures. The proposed fixed and floating point implementation achieves a power efficiency of 318 GOPS/W and 37 GFLOPS/W respectively. The dynamic reconfigurability of the design allows to switch from high efficiency to high throughput mode in less than 4.2 ms. The evaluation of a real time denoising system on FullHD (1080 p) video stream is performed on Virtex-7 FPGA. A comparison with Virtex-5 FPGA implementation shows the robust performance of the architecture across different FPGA families.

VLSI Implementation of Low Power and High Speed Architecture of DWT-IDWT using Lifting based Algorithm

Objective: The purpose of this study is to optimize DWT1-IDWT2 architecture for different Image Compression techniques using lifting based algorithms. Statistical Analysis: The data in form of image and video are transmitted as signal. Because of limited channel bandwidth the data has to be compressed and this reduces the quality of the image. An algorithmic concept of encoding information is given by wavelets in a manner that is layered according to level of detail. The analysis of this implementation includes speed optimization, accuracy, and power reduction. This study uses pipelined architecture of 1D-DWT architecture and is combined with another 1D-DWT module in parallel to obtain 2D-DWT architecture to analyze the speed. Findings: The study was done using VLSI cad tools and coding was done using Verilog, by implementing the proposed algorithm with pipelined-parallel architecture for image compression using DWT, we analyzed the timing wrt* clock speed and we analyzed PSNR and SNR for different video and image compression techniques. Improvements: Our study shows higher speed can be achieved by using DWT for image compression and by using VLSI architecture, the study can be optimized to any further extent.

REFRESH: REDEFINE for Face Recognition Using SURE Homogeneous Cores

In this paper we present design and analysis of a scalable real-time Face Recognition (FR) module to perform 450 recognitions per second. We introduce an algorithm for FR, which is a combination of Weighted Modular Principle Component Analysis and Radial Basis Function Neural Networks. This algorithm offers better recognition accuracy in various practical conditions than algorithms used in existing architectures for real-time FR. To meet real-time requirements, a Scalable Parallel Pipelined Architecture (SPPA) is developed by realizing the above FR algorithm as independent parallel streams and sub-streams of computations. SPPA is capable of supporting large databases maintained in external (DDR) memory. By casting the computations in a stream into hardware, we present the design of a Scalable Unit for Region Evaluation (SURE) core. Using SURE cores as computer elements in a massively parallel CGRA, like REDFINE, we provide a FR system on REDEFINE called REFRESH. We report FPGA and ASIC synthesis results for SPPA and REFRESH. Through analysis using these results, we show that excellent scalability and added programmability in REFRESH makes it a flexible and favorable solution for real-time FR.

Real-time star identification using synthetic radial pattern and its hardware implementation

Star identification algorithm has always been the core strategy of star sensors. For the time being, the identification speed is becoming the bottleneck of satisfying real-time requirements (e.g. high-speed maneuvering applications, power breakdown and so on) on the premise of the robustness. To solve this problem, this paper proposes a novel lost-in-space star identification algorithm based on the synthetic radial pattern, which is dedicated to the pipelined parallel architecture of FPGAs (Field Programmable Gate Arrays). The synthetic radial pattern consists of two single radial patterns connected by their two respective polestars. In the algorithm, the polestar-pair is firstly matched and optimum identification results can be obtained after the follow-up radial pattern filtering. Then, the number of spurious matches can be reduced to a much less level and a mathematical model is also developed to demonstrate the efficiency compared with conventional radial algorithms. Simulations show that the approach is very robust towards various noise conditions and the quantified identification time is less than 1ms at a low resource cost when it is implemented on FPGA platforms.

English

English

FFT Architectures for Real Valued Signals based Different Radices Algorithm

Objectives: The objective of this work is to design efficient FFT architectures for real valued signals. For higher value of N, the design of FFT architecture has many butterflies in the same column. A considerable amount of power is needed for such architecture. The hardware complexity also increases. Methods: The throughput depends on the number of input data paths available, which also increases hardware complexity for higher values of N. This work aims at overcoming these shortcomings by employing one of the effective techniques such as parallel pipelined architectures. One butterfly structure is introduced in one column. For handling the complex data paths, different butterfly structures have been introduced using parallel processing and Folding methodology. The design is simulated in Xilinxs14.3, and synthesized in Cadence RTL compiler. Findings: The hardware complexity is reduced by introducing one butterfly structure in one column. Comparison is made between the different radix algorithms and pipelined architectures and Radix-2 multi path delay commutator (R2MDC) in terms of the required number of adders, delay elements, multiplier units, throughput and control complexity. Although the parallel architecture consumes more power, it occupies less area when compared to the R2MDC architecture. Parallel architecture is more area efficient than R2MDC, whereas the radix-2 multi-path delay commutator is simple to implement, since feedback is not needed in the design. Conclusion: This work can be extended to higher order N-values of DIF and DIT-FFT flow graphs.