A Compact Hardware Architecture for Bilateral Filter With the Combination of Approximate Computing and Look-Up Table

Abstract

Bilateral filter (BF) is a widely applied method for image denoising due to the characteristic of edge-preserving. This brief presents a super-compact hardware architecture for the BF by a piecewise approximate computing algorithm. The contributions are summarized as follows: 1) The architecture significantly reduces the storage and the arithmetic logic for the piecewise approximated filter weights and can attain comparable smoothy and edge-preserving performance to the standard BF. 2) The BF is accelerated by the parallel pixel-level pipeline architecture and the LUT-based divider for normalization. 3) The synthesized result shows that this architecture, even on a low-cost XINILX Zynq-7000 FPGA, can reach real-time denoising at more than 30 frames/second for 8M-pixel ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3268 \times 2448$ </tex-math></inline-formula> ) videos at the maximum working frequency of 278 MHz with the power dissipation of only 168 mW.