Parallel Implementation Scheme Research Articles

Widely Distributed Radar Imaging: Unmediated ADMM Based Approach

This paper presents a novel approach to reconstruct a unique image of an observed scene via synthetic apertures (SA) generated by employing widely distributed radar sensors. The problem is posed as a constrained optimization problem in which the global image which represents the aggregate view of the sensors is a decision variable. While the problem is designed to promote a sparse solution for the global image, it is constrained such that a relationship with local images that can be reconstructed using the measurements at each sensor is respected. Two problem formulations are introduced by stipulating two different establishments of that relationship. The proposed formulations are designed according to consensus ADMM (CADMM) and sharing ADMM (SADMM), and their solutions are provided accordingly as iterative algorithms. We drive the explicit variable updates for each algorithm in addition to the recommended scheme for hybrid parallel implementation on the distributed sensors and a central processing unit. Our algorithms are validated and their performance is evaluated by exploiting the Civilian Vehicles Dome dataset to realize different scenarios of practical relevance. Experimental results show the effectiveness of the proposed algorithms, especially in cases with limited measurements.

Hyper-parallel nonlocal Toffoli gates assisted by quantum dots inside a double-side optical microcavity

<p indent="0mm">Implementing three-qubit Toffoli gates nonlocally plays an important role in quantum communication networks and distributed quantum computation. Most of previous protocols for implementing quantum Toffolis gate consider only implementing Toffoli gates with one degree of freedom. In this paper, we present a scheme for parallel implementation of nonlocal Toffoli gates in polarization and spatial-mode degrees of freedom assisted by quantum dots inside a double-side optical microcavity. Alice and Bob let photons traverse the double-side optical microcavity sequentially and perform single-particle measurements on electron spin in quantum dots and the entangled photons. Charlie performs single-particle measurements and applies the corresponding unitary operation in polarization and spatial-mode degrees of freedom according to Alice and Bob’s measurement results. Alice and Bob can implement hyper-parallel nonlocal Toffoli gates by performing unitary operations according to Charlie’s measurement result. This protocol has the advantage of having high channel capacity by the hyperentangled state as the quantum channel.

Natural convection flow on a bent wavy vertical enclosure filled with power-law nanofluid simulated by Element Free Galerkin method

The present paper contains a study of heat transfer and flow of a power-law nanofluid in bent vertical wavy walls enclosure. The system of governing equations has been solved by mesh free method (EFGM) with a parallel scheme. The results are found in terms of heat transfer rate at the hot wall, isotherms and streamlines under the influence of Aspect ratio, Rayleigh number, Prandtl number, power-law index and wave amplitude. It is observed that the average Nusselt number improves with enhancing the Prandtl number, Rayleigh number and aspect ratio but it decrements with enhancing the power-law index and surface waviness. A parallel implementation scheme gives better efficiency as compared to the sequential scheme. Such problems have direct application in electronic devices, food processing industries, and biomedical applications.

A GPU parallel scheme for accelerating 2D and 3D peridynamics models

Peridynamics (PD) is prevailing in the numerical simulations of damage evolution, but with the cost of far more required computations than traditional methods. This paper proposes a massively parallel implementation scheme for PD simulations with a single-card Graphics Processing Unit (GPU) to reduce the computational cost. The GPU parallel scheme includes two-level parallel modes of particle-mapping and bond-mapping, realizing high parallelism. By reasonably setting the data structure and using the CUDA memory model, realize the efficient utilization of GPU memory resources. Three numerical experiments involving quasi-static and transient problems, 2D and 3D problems, and impact problems are performed. The results show that the proposed parallel scheme can greatly improve the computational efficiency of various PD models while ensuring accuracy. The bond-mapping unrolls the inner loop of the particle-mapping and makes full use of registers and shared memory resources for stronger performance. To further explore the fatigue behavior of rails with hole defects using the GPU parallel scheme, which is difficult to perform using the serial and OpenMP scheme. The results show that the proposed GPU parallel scheme can explore more complex structural fracture problems by greatly reducing the computational cost.

Parallel Cleaning Algorithm for Similar Duplicate Chinese Data Based on BERT

Data is an important source of knowledge discovery, but the existence of similar duplicate data not only increases the redundancy of the database but also affects the subsequent data mining work. Cleaning similar duplicate data is helpful to improve work efficiency. Based on the complexity of the Chinese language and the bottleneck of the single machine system to large-scale data computing performance, this paper proposes a Chinese data cleaning method that combines the BERT model and a k-means clustering algorithm and gives a parallel implementation scheme of the algorithm. In the process of text to vector, the position vector is introduced to obtain the context features of words, and the vector is dynamically adjusted according to the semantics so that the polysemous words can obtain different vector representations in different contexts. At the same time, the parallel implementation of the process is designed based on Hadoop. After that, k-means clustering algorithm is used to cluster similar duplicate data to achieve the purpose of cleaning. Experimental results on a variety of data sets show that the parallel cleaning algorithm proposed in this paper not only has good speedup and scalability but also improves the precision and recall of similar duplicate data cleaning, which will be of great significance for subsequent data mining.

RETRACTED ARTICLE: Forest rainfall characteristics based on heterogeneous computing and influencing factors of athletes’ physical supplement

The advent of the era of big data greatly stimulates the research and application of heterogeneous algorithms. Firstly, based on the characteristics of heterogeneous FPGA computing platform, this paper develops kb-knn heterogeneous algorithm based on KNN. In order to make full use of the heterogeneous platform, this paper classifies the unclassified data and adopts the parallel implementation scheme of flow between devices, so that the master and slave devices in the heterogeneous system can participate in the calculation cycle of global hydrology and material energy. This paper explains the importance of forest rainfall distribution for regional social and economic development and agricultural production, ecological balance, optimal allocation of water resources, and environmental protection. Due to the limited availability of data from multiple sources, there are few studies to analyze the precipitation changes of different time scales in mountainous areas. The forest precipitation data used in this paper usually have low temporal and spatial resolution, and cannot describe the spatiotemporal heterogeneity of precipitation in mountainous areas. In addition, the physical fitness of athletes mainly includes strength training and speed training. The combination of recovery and nutrition is the basic knowledge that coaches must have. The rehabilitation of athletes mainly depends on the amount of exercise, physical therapy, and massage adjustment. Reasonable nutrition is one of the most important factors for athletes to win and ensure their health and sports ability. Heterogeneous computing platform provides a new solution to accelerate the implementation of such algorithms. In the heterogeneous computing platform, this paper discusses the nutrition of athletes’ physical supplement and describes the characteristics of forest rainfall.

Hybrid parallel adder for 3X multiple generation in radix-8 booth encoding using fast carry tree structure

PurposeIn most commercial processors, enhancing the speed of multiplication using radix-8 booth encoding is the preferred option. In radix-8 architecture, the 3X(= 2X + X) multiple generation is a major bottleneck. This paper aims to propose a parallel implementation scheme recognizing the symmetry in the carry recurrence equations of 3X multiples. The proposed architecture evaluates the odd (H) and even (K) carry signals separately. As prefix tree structure offers fast carry propagation, the parallel implementation is based on a hybrid style of two popular prefix architectures.Design/methodology/approachThe performance of the proposed architecture is evaluated using Cadence TSMC 180 nm library. A comparison of performance parameters with other architectures has been carried out to highlight the architectural advantages of the proposed architecture.FindingsA comparison of performance parameters with others shows that the proposed architecture has a reduced critical path and a commensurate improvement in delay for a bit width of 64. It is shown that up to 32 bits, this parallel architecture has a superior performance and would be the appropriate choice for Application Specific Integrated Circuit (ASIC) implementation. It has also been suggested that higher-order bit widths could be implemented using a modular arrangement.Originality/valueThis paper proposes a new parallel architecture for hard multiple (3X) generation in Radix-8 Booth encoding. As the multiplication is the key operation in digital signal processors, this type of high-speed architectures gains importance in the future processor design. Defence applications such as target finding and multiple target recognitions and image processing applications necessitate this type of high-speed multipliers. Also, it is appropriate for the ASIC implementation. The authors would like to mention that this paper is not yet published anywhere, and it is the research paper of Dr R. Nirmaladevi.

Towards Efficient Neuromorphic Hardware: Unsupervised Adaptive Neuron Pruning

To solve real-time challenges, neuromorphic systems generally require deep and complex network structures. Thus, it is crucial to search for effective solutions that can reduce network complexity, improve energy efficiency, and maintain high accuracy. To this end, we propose unsupervised pruning strategies that are focused on pruning neurons while training in spiking neural networks (SNNs) by utilizing network dynamics. The importance of neurons is determined by the fact that neurons that fire more spikes contribute more to network performance. Based on these criteria, we demonstrate that pruning with an adaptive spike count threshold provides a simple and effective approach that can reduce network size significantly and maintain high classification accuracy. The online adaptive pruning shows potential for developing energy-efficient training techniques due to less memory access and less weight-update computation. Furthermore, a parallel digital implementation scheme is proposed to implement spiking neural networks (SNNs) on field programmable gate array (FPGA). Notably, our proposed pruning strategies preserve the dense format of weight matrices, so the implementation architecture remains the same after network compression. The adaptive pruning strategy enables 2.3× reduction in memory size and 2.8× improvement on energy efficiency when 400 neurons are pruned from an 800-neuron network, while the loss of classification accuracy is 1.69%. And the best choice of pruning percentage depends on the trade-off among accuracy, memory, and energy. Therefore, this work offers a promising solution for effective network compression and energy-efficient hardware implementation of neuromorphic systems in real-time applications.

Remote implementation of single-qubit operations via hyperentangled states with cross-Kerr nonlinearity

Quantum information processing via hyperentanglement can improve the quantum channel capacity for long-distance quantum communication and large-scale quantum communication networks. Some important works have been presented in quantum remote state preparation with hyperentangled states. However, the protocols for quantum operation remote implementation are based on quantum systems encoded in one degree of freedom. We present a quantum operation remote implementation protocol for arbitrary single-qubit operations with two-photon hyperentangled states via cross-Kerr nonlinearities. Moreover, we discuss the scheme for parallel remote implementation of partially unknown quantum operations via two-photon hyperentangled states.

GPU‐based parallel real‐time volt/var optimisation for distribution network considering distributed generators

Although the wide integration of advanced metering infrastructure on distribution network facilitates the application of volt/var optimisation (VVO) in real-time circumstance, the contradiction between heavy computation load and low solution efficiency is still a big challenge, thus the system scales investigated in the literature are limited. In this study, the full AC real-time VVO is formulated based on particle swarm optimisation (PSO) framework and direct approach (DA) power flow method, where all components, such as distributed generator and on-load tap changer transformer, are formulated and integrated into the iterative DA process. Since both PSO and DA are suitable for parallel implementation, the graphics processing unit (GPU) is introduced for acceleration in order to achieve the possibility for real-time application. All the solution process is executed by GPU with the well-established data structure and thread organisation pattern, resulting in high efficiency by guaranteeing coalesced access within each warp. Case studies are conducted on four systems with sizes ranging from 136-bus to 1760-bus. Solution accuracy and convergence property are validated by the popular open source package Matpower. Based on the results from solution efficiency comparison between CPU sequential, CPU parallel, and GPU parallel programs, the promise of the proposed parallel implementation scheme for practical application is established.

A new parallel lattice reduction algorithm for BKZ reduced bases

In order to implement the original BKZ algorithm in parallel, we describe it in terms of parallelism and give its parallel implementation scheme. Then we analyze the efficiency of algorithm’s parallel implementation and show that the speedup factor of BKZ algorithm in parallel is extremely low. Therefore we present a new parallel lattice reduction algorithm suitable for multiprocessor computer architecture. The new algorithm can obtain a BKZ reduced basis and the parallel speedup is effective. Also with the practical results, although the computational complexity increases compared with the original BKZ algorithm, we still indicate that the new algorithm performs well in parallel and the time cost in parallel is less. At the same time, we show that the length of the shortest vector is smaller.

A Data Parallel Implementation Scheme of Geometric Operations

A data parallel implementation of geometric operations is proposed and conclusions are proved. It shows that the computation complexity of data parallel implementation scheme presented in this paper is Ο(M+N). It can be used to improve the efficiency of geometric operations and can easily meet the real time requirements of the digital image processing.

Data Parallel Implementation of Geometric Operations

The data parallel implementation scheme of zero-order interpolation and first-order interpolation of backward mapping is proved and discussed. It is shown that the complexity of data parallel implementation scheme presented in this paper is Ο(M+N) instead of Ο(MN) in sequential processing, thereby it can easily meet the real time requirements of the digital image processing.

A Data Parallel Implementation Scheme of Geometric Operations

A data parallel implementation of geometric operations is proposed and conclusions are proved. It shows that the computation complexity of data parallel implementation scheme presented in this paper is Ο(M+N). It can be used to improve the efficiency of geometric operations and can easily meet the real time requirements of the digital image processing.

Performance Analysis and Optimization of PalaBos on Petascale Sunway BlueLight MPP Supercomputer

We present some results conceming the computational performances of the open source general purpose CFD code PalaBos, in terms of scalability and efficiency, on the petascale Sunway BlueLight MPP system. Based on the numerical simulated program of 3D cavity lid driven flow, the optimization methods in I/O, communication, memory access, etc, are applied in debugging and optimization of the parallel MPI program. Experimental results of large scalar parallel computing of 3D cavity lid driven flow show that, the parallel strategy and optimization methods are correct and efficient. The parallel implementation scheme is very useful and can shorten the computing time explicitly.

Parallel processing of the Building-Cube Method on a GPU platform

The Building-Cube Method (BCM) based on equally-spaced Cartesian meshes has been proposed as a next generation CFD method. Due to the equally-spaced meshes, it is well suited for highly parallel computation. This paper proposes a parallel implementation scheme of BCM on a GPU cluster system, which needs efficient hierarchical parallel processing to exploit the potential of the cluster system. The proposed scheme employs the Red-Black SOR method for the pressure calculations, which is the most time-consuming part of BCM, to obtain massive data parallelism of BCM. By exploiting the coarse-grain and fine-grain parallelism of BCM, the proposed scheme hierarchically assigns equally-divided tasks into the GPU cluster system. Furthermore, to exploit the computational power of GPUs in the cluster system, the proposed scheme employs an efficient data management such as coalesced data transfer and reusing data on an on-chip memory. Experimental results show that the single GPU implementation can achieve about three times higher performance than the single CPU one. Moreover, the multiple GPU implementation can achieve an almost ideal scalability. Finally, the possibility of further acceleration of not only the pressure calculation but also the whole BCM is discussed.

A Parallel Implementation Scheme of Relational Tables Based on Multidimensional Extendible Array

In this article, an efficient parallel implementation scheme of relational tables is proposed and evaluated. The scheme implements a relational table by employing an extendible multidimensional array. Data allocation is a key performance factor for parallel database systems. This holds especially for data warehousing environments in which huge amounts of data have to be dealt with. In our scheme, an efficient data allocation technique is used, based on the notion of extendible array. The dynamic load balancing is conducted when load on each processor is not uniformly distributed in order to maximize processor utilization.

Parallel and pipelined implementations of injected numerator lattice digital filters

Parallel and pipelined implementations are effective measures for improving the maximum permissible sampling rate of a digital filter if all the data required by the arithmetic units are immediately available on demand. This implies that parallel access to the data should be possible and that for any loop in the signal flow graph the total number of series delay elements should be at least equal to the total number of pipelined stages in that loop. In the conventional lattice form IIR digital filter, the feedback loops are single-delay loops. As a consequence, the conventional lattice form IIR filter does not benefit significantly from parallel and pipelined implementation scheme. In this paper, we introduce a new lattice form IIR filter structure where the number of delay elements in the loops can be set arbitrarily. This renders the new lattice form IIR filter amenable to parallel and pipelined implementation. >

New approach to parallel systolic algorithm implementations — RLSL example

Many signal processing algorithms are very computationally intensive. To execute them fast enough, highly parallel computing structures are needed. One such is the systolic array structure. Its implementation requires mapping of the given algorithm to the systolic structure. The existing mapping procedures known from the literature are limited in various ways. In our article a new approach to find the optimal scheduling vector is presented. The procedure is suitable for mapping multi-equation systems. It takes into account the exact low-level computational requirements of the algorithm. The mapping procedure is applied to the RLSL algorithm, yielding its simplified parallel implementation scheme.