Abstract
Many signal processing algorithms are very computationally intensive. To execute them fast enough, highly parallel computing structures are needed. One such is the systolic array structure. Its implementation requires mapping of the given algorithm to the systolic structure. The existing mapping procedures known from the literature are limited in various ways. In our article a new approach to find the optimal scheduling vector is presented. The procedure is suitable for mapping multi-equation systems. It takes into account the exact low-level computational requirements of the algorithm. The mapping procedure is applied to the RLSL algorithm, yielding its simplified parallel implementation scheme.
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