Abstract
Many signal processing algorithms are very computationally intensive. To execute them fast enough, highly parallel computing structures are needed. One such is the systolic array structure. Its implementation requires mapping of the given algorithm to the systolic structure. The existing mapping procedures known from the literature are limited in various ways. In our article a new approach to find the optimal scheduling vector is presented. The procedure is suitable for mapping multi-equation systems. It takes into account the exact low-level computational requirements of the algorithm. The mapping procedure is applied to the RLSL algorithm, yielding its simplified parallel implementation scheme.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
