Parallel Decoding Research Articles

QC-IRA-d Codes Based on Circulant Permutation Matrices

This paper presents a new kind of quasi-cyclic irregular repeat accumulate (IRA) codes based on circulant permutation matrices called QC-IRA-rf codes. The presented QC IRA-rf codes have lower encoding complexity than traditional IRA codes and can be decoded in a partially parallel decoder like QC-LDPC codes. Simulation results show that QC-IRA-rf codes have good error-correcting performance.

Serial decoding of rateless code over noisy channels

Rateless code usually generates a potentially infinite number of coded packets at the encoder and collects enough packets at the decoder to ensure reliable recovery of multiple information packets. The conventional rateless decoder usually works in a parallel manner which needs to initiate a new belief propagation (BP) decoding procedure upon each newly received collection of coded packets, thereby resulting in prohibitive decoding complexity in practice. In this paper, we present a novel serial decoding algorithm, i.e., the serial storage belief propagation (SS BP) algorithm, for rateless codes over noisy channels. Specifically, upon receiving a new group of coded packets, the decoder initiates a new attempt to decode all the packets received so far, using the results of the previous attempt as initial input. Moreover, in each iteration of the new attempt, the decoder serially propagates the messages group by group from the most recent one to the earliest one. In this way, the newly updated messages can be propagated faster, expediting the recovery of information packets. In addition, the proposed serial decoding algorithm has significantly lower complexity than the existing parallel decoding algorithms. Simulation results validate its effectiveness in AWGN, Rayleigh, and Rician fading channels.

High Throughput Parallel Fano Decoding

In this paper, a bidirectional Fano algorithm (BFA) is proposed, in which a forward decoder (FD) and a backward decoder (BD) search in the opposite direction in the code tree simultaneously. It is shown that the proposed BFA can achieve more than twice the decoding throughput compared to the conventional unidirectional Fano algorithm (UFA) and there is higher throughput improvement at low signal-to-noise ratio (SNR). This new BFA decoding technique is applied in the parallel convolutional decoding architecture in very high throughput systems, such as the WirelessHD system. Due to the variability in the decoding delays of the parallel codewords, a scheduler is introduced in the parallel Fano decoding architecture which can dynamically allocate the idle decoders to assist with decoding the other parallel codewords in a bidirectional manner. It is shown that the proposed parallel Fano decoding with scheduling can dramatically increase the decoding throughput compared to the parallel Fano decoding without scheduling, and its computational complexity is much lower than that of parallel Viterbi decoding, especially at high SNR. The performance of the parallel Fano decoding with different scheduling schemes is also compared and analyzed in detail in the paper.

High efficient distributed video coding with parallelized design for LDPCA decoding on CUDA based GPGPU

Distributed video coding (DVC) is a new coding paradigm targeting on applications with the need of low-complexity and/or low-power encoding at the cost of a high-complexity decoding. In the DVC architectures based on Error Control Codes (ECCs) with a feedback channel, the high decoding complexity comes from the decode-check-request iterations between the ECC encoder and the ECC decoder. In this paper, a parallel message-passing decoding algorithm for computing low density parity check (LDPC) syndromes is applied through the Compute Unified Device Architecture (CUDA) based on General Purpose Graphics Processing Unit (GPGPU). Furthermore, we proposed a novel rate control mechanism, dubbed as the Ladder Step Size Request (LSSR), to reduce the number of requests which leads to much speedup gain. Experimental results show that, through our work, the overall DVC decoding speedup gain can reach 46.52 with only 0.2 dB rate distortion performance loss.

High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver

This paper presents a high-efficiency parallel architecture for a turbo decoder using a quadratic permutation polynomial (QPP) interleaver. Conventionally, two half-iterations for different component codewords alternate during the decoding flow. Due to the initialization calculation and pipeline delays in every half-iteration, the functional units in turbo decoders will be idle for several cycles. This inactive period will degrade throughput, especially for small blocks or high parallelism. To resolve this issue, we impose several constraints on the QPP interleaver and rearrange the processing schedule; then the following half-iteration can be executed before the completion of the current half-iteration. Thus, it can eliminate the idle cycles and increase the efficiency of functional units. Based on this modified schedule with 100% efficiency, a parallel turbo decoder which contains 32 radix-24 SISO decoders is implemented with 90 nm technology to achieve 1.4 Gb/s while decoding size-4096 blocks for 8 iterations.

Embedded Real-Time MPEG-4 Decoder Based on ADSP-BF527

In this paper, we propose an embedded real-time MPEG-4 decoder based on ADSP-BF527 Blackfin DSP. In order to achieve the real-time requirement of MPEG-4 decoding, we modify and optimize the decoding modules. Firstly, we analyze the number of operations for various modules, and then use two buffer groups (BG) as parallel decoding mechanism of broadcast transformation. Finally, we make use of direct memory access (DMA) to carry out program steps. Experimental results demonstrate that the proposed method can decode a CIF video which reduces approximately 40.3 MHz core cycles. In addition, the decoded frame playing rate can increase from 3 fps to 25 fps when applied the PPI procedure. The playing rate can reach above 30 fps as using QCIF video so that the proposed method can achieve a real-time decoder and player.

Performance Evaluation of a Massively Parallel Decoder for CISC Microprocessors

Performance of the decoder unit is critical for CISC microprocessors. To take x86 ISA for an example, we analyzes the x86 instruction formats in detail. We compare two decoding strategies used in Longteng C1&C2 microprocessors: One is a simply direct serial decoder; another is a massively parallel decoder. Simulation results show speedups around 2.2~3.6 are obtained by using 10 parallel sub-decoders.

A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes

A reduced-complexity low density parity check (LDPC) layered decoding architecture is proposed using an offset permutation scheme in the switch networks. This method requires only one shuffle network, rather than the two shuffle networks which are used in conventional designs. In addition, we use a block parallel decoding scheme by suitably mapping between required memory banks and processing units in order to increase the decoding throughput. The proposed architecture is realized for a 672-bit, rate-1/2 irregular LDPC code on a Xilinx Virtex-4 FPGA device. The design achieves an information throughput of 822 Mb/s at a clock speed of 335 MHz with a maximum of 8 iterations.

Multi-threaded syntax element partitioning for parallel entropy decoding

Strong demand for high resolution video services leads to active studies on high speed video processing. Especially, widespread deployment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. Even if parallelization of other decoding steps on a multi-core platform may improve performance, entropy decoding often becomes a performance bottleneck since it should be processed sequentially. To resolve this concern, parallel entropy coding algorithms have been proposed. Syntax element partitioning is an algorithm for parallelization of Context Adaptive Binary Arithmetic Coding (CABAC). In this paper, we propose Multi-Threaded Syntax Element Partitioning (MT-SEP) for parallel entropy decoding. One major advantage of software parallel video decoding over hardware implementations will be that versatile video codecs can be implemented flexibly. We parallelized the KTA 2.7 decoder with the proposed technique on an Intel Quad-Core platform. We achieved up to 56% performance improvement using the proposed version of syntax element partitioning.

Switching Activity Minimization in Iterative LDPC Decoders

LDPC codes can be designed to perform extremely close to the Shannon limit. Achieving such performance with high energy efficiency is now a main goal in the research community. This work combines knowledge of LDPC decoder message statistics, provided by density evolution, with knowledge of the physical implementation of decoders to predict switching activity in the decoder interconnect. In this work we provide results for the switching activity on the interconnect for fully parallel decoders. However, our model can be applied to partially parallel and serial implementations, and is not limited to interconnect. It is shown that switching activity can vary by as much as 300%, depending on several hardware design choices. Results of this work validate the usefulness of the presented model for providing designers with an understanding of how their decoder implementation choices affect power consumption for any size of LDPC code. This knowledge can be used for making design choices that minimize decoder power consumption very early in the hardware design process.

GPU-based DVB-S2 LDPC decoder with high throughput and fast error floor detection

A new strategy is proposed for implementing computationally intensive high-throughput decoders based on the long length irregular LDPC codes adopted in the DVB-S2 standard. It is supported on manycore graphics processing unit (GPU) architectures, for performing parallel multi-threaded decoding of multiple codewords with reduced accesses to global memory. This novel approach is flexible and scalable, and achieves throughputs superior to the 90 Mbit/s required by the DVB-S2 standard, while at the same time it improves error-correcting performances such as BER and error floors regarding conventional VLSI-based decoders.

Collision-free interleaver applied to parallel decoding Turbo codes

To improve the decoding performance of Parallel Decoding Turbo Codes (PDTC), a memory collision-free interleaver to avoid the data collision was proposed. The information was written into a matrix first, and then S-random interleaving was done on its rows and columns. The simulation shows the distances spectrum of this interleaver is close to the full random interleaver, the bit error rate performance of PDTC is better than other interleavers which have the same algorithm complexity, and with the increase of the length frame, the improved result is more obvious. Hence this design has outstanding performances in PDTC.

Accelerated Network Coding with Dynamic Stream Decomposition on Graphics Processing Unit

Network coding, a well-known technique for optimizing data-flow in wired and wireless network systems, has attracted considerable attention in various fields. However, the decoding complexity in network coding becomes a major performance bottleneck in the practical network systems; thus, several researches have been conducted for improving the decoding performance in network coding. Nevertheless, previously proposed parallel network coding algorithms have shown limited scalability and performance imbalance for different-sized transfer units and multiple streams. In this paper, we propose a new parallel decoding algorithm for network coding using a graphics processing unit (GPU). This algorithm can simultaneously process multiple incoming streams and can maintain its maximum decoding performance irrespective of the size and number of transfer units. Our experimental results show that the proposed algorithm exhibits a 682.2 Mbps decoding bandwidth on a system with GeForce GTX 285 GPU and speed-ups of up to 26 as compared to the existing single stream decoding procedure with a 128 × 128 coefficient matrix and different-sized data blocks.

Parallelism Efficiency in Convolutional Turbo Decoding

Parallel turbo decoding is becoming mandatory in order to achieve high throughput and to reduce latency, both crucial in emerging digital communication applications. This paper explores and analyzes parallelism techniques in convolutional turbo decoding with the BCJR algorithm. A three-level structured classification of parallelism techniques is proposed and discussed: BCJR metric level parallelism, BCJR-SISO decoder level parallelism, and Turbo-decoder level parallelism. The second level of this classification is thoroughly analyzed on the basis of parallelism efficiency criteria, since it offers the best tradeoff between achievable parallelism degree and area overhead. At this level, and for subblock parallelism, we illustrate how subblock initializations are more efficient with the message passing technique than with the acquisition approach. Besides, subblock parallelism becomes quite inefficient for high subblock parallelism degree. Conversely, component-decoder parallelism efficiency increases with subblock parallelism degree. This efficiency, moreover, depends on BCJR computation schemes and on propagation time. We show that component-decoder parallelism using shuffled decoding enables to maximize architecture efficiency and, hence, is well suited for hardware implementation of high throughput turbo decoder.

A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding

In this brief, we introduce a new iterative decoder implementation called pulsewidth-modulated min-sum (PWM-MS), in which messages are exchanged in a pulsewidth-encoded format. The advantages of this method are low switching activity, very low complexity check nodes, low routing congestion, and excellent energy efficiency. We implement a fully parallel PWM offset MS decoder for a (660, 484) regular (4, 15) low-density parity-check code with 4-bit quantization in 0.13-μm CMOS, with a core area of 5.76 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (4.24-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> cell area or 556K equivalent and gates). In postlayout simulations, this decoder achieves an average information throughput of 5.71 Gb/s and an energy consumption of 65.8 pJ per information bit at a signal-to-noise ratio of 5.5 dB. Our results show a 21% reduction in area, a 0.6-dB improvement in coding gain, and an energy efficiency improvement of 19% over the comparable bit-serial MS decoder architecture. We also demonstrate 3-bit implementations, in which the coding gain is traded off for further improvements in throughput, area, and energy efficiency.

Majority-Based Tracking Forecast Memories for Stochastic LDPC Decoding

This paper proposes majority-based tracking forecast memories (MTFMs) for area efficient high throughput ASIC implementation of stochastic Low-Density Parity-Check (LDPC) decoders. The proposed method is applied for ASIC implementation of a fully parallel stochastic decoder that decodes the (2048, 1723) LDPC code from the IEEE 802.3an (10GBASE-T) standard. The decoder occupies a silicon core area of 6.38 mm2 in CMOS 90 nm technology, achieves a maximum clock frequency of 500 MHz, and provides a maximum core throughput of 61.3 Gb/s. The decoder also has good decoding performance and error-floor behavior and provides a bit error rate (BER) of about 4 × 10-13 at Eb/N0=5.15 dB. To the best of our knowledge, the implemented decoder is the most area efficient fully parallel soft -decision LDPC decoder reported in the literature.

On chip interconnects for multiprocessor turbo decoding architectures

Turbo codes are among the most powerful and widely adopted error correcting codes in several communication applications. The high throughput requirements of current and future standards impose that parallel decoders composed by multiple interconnected processing elements are used at the receiver side to efficiently decode turbo codes. In this work, on chip interconnects for multiprocessor turbo decoding are investigated. Due to the dominant trend towards the design of flexible, multi-standard decoders, capable to support the decoding of several turbo codes, the Network-on-Chip approach is seen as a viable and promising solution, although the specific characteristics of the addressed application impose a drastic simplification in the network organization. Both indirect and direct network topologies are studied and experimental results show that a Network-on-Chip based decoder made of 16 processing elements can achieve a throughput of several hundreds of Mbps. Moreover, the area required by the network compares favorably with previously published works on flexible interconnect architectures for turbo decoding and the cost overhead of NOC based solutions with respect to a fully dedicated implementation is limited to 13%.

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

We present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The high-throughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several MAP decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed parallel Turbo decoder has been synthesized, placed and routed in a 65-nm CMOS technology with a core area of 8.3 mm 2 and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 MAP decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations

An efficient VLSI architecture for 4 × 4 16-QAM sorted QR-factorisation based V-BLAST decoder

This paper presents a practically realisable VLSI architecture for a 4 × 4 16-QAM MIMO wireless communication system using the Vertical Bell Labs Layered Space-Time (V-BLAST) detection scheme. The proposed implementation employs the QR-factorisation technique. The design and optimisation of the pre-decoder block are carried out using the COordinate Rotation DIgital Computer (CORDIC) processors. In order to avoid the numerical problems associated with Back Substitution (BS) based Symbol Interference Cancellation (SIC), a modified BS-SIC architecture that eliminates the need for division and multiplication is proposed. Not only does this substantially reduce the hardware cost, but also enjoys improved numerical stability. As the decoder hardware design can also be simplified by rendering it oblivious to the power normalisation in the transmitter side of the MIMO wireless system, we have designed a matching compensation unit at the receiver. The resulting VLSI architecture was implemented on an Altera Stratix Field Programmable Gate Array (FPGA) platform and on a 0.18 μm Application Specific Integrated Circuits (ASIC) platform. Detection throughput ratings of 149 Mbps and 212 Mbps were achieved. However, the lower hardware complexity of the BS-SIC based decoder architecture comes at the cost of a degradation in the Bit Error Rate (BER) performance with respect to the original higher complexity V-BLAST. Therefore, we also propose a novel parallel decoding scheme that is aimed at improving the system BER. This novel scheme allows for a compromise between the hardware overhead and the BER performance. As the hardware complexity is increased, the performance approaches the original V-BLAST limit.

System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor

The evolution of third generation mobile communications toward high-speed packet access and long-term evolution is ongoing and will substantially increase the throughput with higher spectral efficiency. This paper presents the system architecture of an LTE modem based on a programmable baseband processor. The architecture includes a baseband processor that handles processing time and frequency synchronization, IFFT/FFT (up to 2048-p), channel estimation and subcarrier de-mapping. The throughput and latency requirements of a Category four User Equipment (CAT4 UE) is met by adding a MIMO symbol detector and a parallel Turbo decoder supporting H-ARQ, which brings both low silicon cost and enough flexibility to support other wireless standards. The complexity demonstrated by the modem shows the practicality and advantage of using programmable baseband processors for a single-chip LTE solution.