Parallel Decoding Research Articles

Parallel HEVC Decoding on Multi- and Many-core Architectures

The Joint Collaborative Team on Video Decoding is developing a new standard named High Efficiency Video Coding (HEVC) that aims at reducing the bitrate of H.264/AVC by another 50 %. In order to fulfill the computational demands of the new standard, in particular for high resolutions and at low power budgets, exploiting parallelism is no longer an option but a requirement. Therefore, HEVC includes several coding tools that allows to divide each picture into several partitions that can be processed in parallel, without degrading the quality nor the bitrate. In this paper we adapt one of these approaches, the Wavefront Parallel Processing (WPP) coding, and show how it can be implemented on multi- and many-core processors. Our approach, named Overlapped Wavefront (OWF), processes several partitions as well as several pictures in parallel. This has the advantage that the amount of (thread-level) parallelism stays constant during execution. In addition, performance and power results are provided for three platforms: a server Intel CPU with 8 cores, a laptop Intel CPU with 4 cores, and a TILE-Gx36 with 36 cores from Tilera. The results show that our parallel HEVC decoder is capable of achieving an average frame rate of 116 fps for 4k resolution on a standard multicore CPU. The results also demonstrate that exploiting more parallelism by increasing the number of cores can improve the energy efficiency measured in terms of Joules per frame substantially.

High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard

Video encoding and decoding are computing intensive applications that require high performance processors or dedicated hardware. Video decoding offers a high parallel processing potential that may be exploited. However, a particular task challenges parallelization: entropy decoding. In H.264 and SVC video standards, this task is mainly carried out using arithmetic decoding, an strictly sequential algorithm that achieves results close to the entropy limit. By accelerating arithmetic decoding, the bottleneck is removed and parallel decoding is enabled. Many works have been published on accelerating pure binary encoding and decoding. However, little research has been done into how to integrate binary decoding with context managing and control without losing performance. In this work we propose a FPGA-based architecture that achieves real time decoding for high-definition video by sustaining a 1 bin per cycle throughput. This is accomplished by implementing fast bin decoding; a novel and area efficient context-managing mechanism; and optimized control scheduling.

A Parallel IRRWBF LDPC Decoder Based on Stream-Based Processor

Low-density parity check (LDPC) codes have gained much attention due to their use of various belief-propagation (BP) decoding algorithms to impart excellent error-correcting capability. The BP decoders are quite simple; however, their computation-intensive and repetitive process prohibits their use in energy-sensitive applications such as sensor networks. Bit flipping-based decoding algorithms, especially implementation-efficient, reliability ratio-based, weighted bit-flipping (IRRWBF) decoding; have shown an excellent tradeoff between error-correction performance and implementation cost. In this paper, we show that with IRRWBF, iterative re-computation can be replaced by iterative selective updating. When compared with the original algorithm, simulation results show that, decoding speed can be increased by 200 to 600 percent , as the number of decoding iterations is increased from 5 to 1,000. The decoding steps are broken down into various stages such that the update operations are mostly of the single-instruction, multiple-data (SIMD) type. In this paper, we show that by using Intel Wireless MMX 2 accelerating technology in the proposed algorithm, the speed increased by 500 to 1,500 percent. The results of implementing the proposed scheme using an Intel/Marvell PXA320 (806 MHz) CPU are presented. The proposed scheme can be used effectively in real-time LDPC codes for energy-sensitive mobile devices.

The Design of Efficient Viterbi Decoder and Realization by FPGA

Convolution code is a kind of widely used error-correcting codes in the error control field, in order to solve the Viterbi decoding of higher complex degree and lower speed etc. problem, a kind of efficient and reliable Viterbi decode method has been put forward specially. Firstly, the principle of Viterbi decode has been introduced by detail; Secondly, in order to improve the parallel decoding speed, Viterbi decoding algorithm is improved; And then, according to the improved algorithm to achieve high speed and parallel Viterbi decoding method, which is realized easily by FPGA; Finally, the function simulation and test for (2, 1, 7) convolution code has been carried out. The experimental results show that: when the system clock is 64 MHz, eventually the decoding rate of not less than 16 Mbps, improved Viterbi decoding algorithm has lower complexity, improved Viterbi decoding efficiency.

High throughput sequential decoding with state estimation

Sequential decoding can achieve high throughput convolutional decoding with much lower computational complexity when compared with the Viterbi algorithm (VA) at a relatively high signal-to-noise ratio (SNR). A parallel bidirectional Fano algorithm (BFA) decoding architecture is investigated in this paper. In order to increase the utilisation of the parallel BFA decoders, and thus improve the decoding throughput, a state estimation method is proposed which can effectively partition a long codeword into multiple short sub-codewords. The parallel BFA decoding with state estimation architecture is shown to achieve 30–55% decoding throughput improvement compared with the parallel BFA decoding scheme without state estimation. Compared with the VA, the parallel BFA decoding only requires 3–30% computational complexity of that required by the VA with a similar error rate performance.

A Real-Time H.264 BP Decoder Based on ADSP-BF548

In this paper, we propose an embedded real-time H.264 Baseline Profile (BP) decoder based on ADSP-BF548 Blackfin processor. In order to achieve the real-time requirement of H.264 decoding, we modify and optimize the decoding modules and codes, respectively. Firstly, we analyze the number of operations for various modules using assembly code, and then use direct memory access (DMA) to carry out the parallelism between algorithm execution and data movement. Finally, we make use of two buffer groups (BG) as parallel decoding mechanism of broadcast transformation. Experimental results demonstrate that the play rate can reach above 25 fps as using QCIF video. According to some tests, a real-time H.264 BP decoding can be achieved with a 600 MHz DSP.

VHDL Design and FPGA Implementation of a Fully Parallel Architecture for Iterative Decoder of Majority Logic Codes for High Data Rate Applications

In this work, we propose a design and FPGA (Field Programmable Gate Arrays) implementation of three parallel architectures for majority logic decoder of low complexity for high data rate applications. These architectures are hard decision decoder architecture (Hard in - Hard out (HIHO)), the SIHO threshold decoding (Soft in – Hard out) and the SISO threshold decoding (Soft in – Soft out). The chosen code is the Difference Set Cyclic DSC code. The VHDL (Very high speed integrated circuit Hardware Description Language) design and the synthesis of such architectures show that such decoders can achieve high data rate with low complexity. In our case, the iterative decoder associated to the fully parallel SISO threshold decoders allows achieving high data rates, 2 clock cycles for two iterations with a complexity of 7350LEs.

Energy efficient low-cost video communications

Although traditional video coding is based on complex encoders and simple decoders, more recent codecs can reverse the complexity in order to provide low-cost encoders for mobile devices. However, the complexity is moved from the encoder to the decoder, accumulating high complexity on the decoder side. In this work, a parallel decoding architecture is proposed which exploits multiplecore processors to tackle this high complexity. In particular, the data distribution scheme in this architecture considers two parallelism levels: Group of Pictures and spatial frame distribution. Our results, for a four-core Multicore Processor, it is achieved a time reduction of up to 70% on average, with a negligible Rate-Distortion penalty. In addition, the usage of the CPU is also analyzed, reaching 80% on average and the energy consumption of the decoder is reduced up to 60%.

Toward fast Wyner-Ziv video decoding on multicore processors

The Wyner-Ziv video coding paradigm provides a framework where most of the complexity is moved from the encoder to the decoder. In this way, Wyner-Ziv coding efficiently supports multimedia services for mobile devices which have to capture, encode and send video. However, the complexity of the decoder is quite high and it should be reduced. This work presents several parallel Wyner-Ziv decoding algorithms aimed at reducing this high complexity. Considering the fact that technological advances provide us new hardware which supports parallel data processing, these algorithms efficiently distribute the burden of the complexity over the number of cores which are available in the architecture. Particularly four parallel approaches have been proposed and analyzed. In the first parallel approach, the each bitplane of a frame could be decoded in a parallel way by a different core, achieving a time reduction of 33.21 % in average, although it depends on the number of bitplanes used. The second approach proposes a spatial distribution of each frame, avoiding dependences between bitplanes and then obtaining a time reduction of 67 % in average. The third approach executes each GOP in a parallel way, avoiding all synchronization dependences and achieving 71 % of time reduction in average, although the maximum performance is reached when the key frame buffer is full. Finally, the last approach distributes the burden of complexity over two levels, namely GOP and frame, in order to obtain the advantages of both: a negligible rate distortion penalty based on the GOP approach, and a low delay introduced by the spatial distribution approach. By using this parallel approach, the decoding time is reduced up to 76 %. In addition, by using parallel decoding, 60 % of the energy consumption is saved. The proposed methods are scalable for any multicore processor architecture and adaptable for different Wyner-Ziv decoding schemes.

Low-complexity high-throughput decoding architecture for convolutional codes

Sequential decoding can achieve a very low computational complexity and short decoding delay when the signal-to-noise ratio (SNR) is relatively high. In this article, a low-complexity high-throughput decoding architecture based on a sequential decoding algorithm is proposed for convolutional codes. Parallel Fano decoders are scheduled to the codewords in parallel input buffers according to buffer occupancy, so that the processing capabilities of the Fano decoders can be fully utilized, resulting in high decoding throughput. A discrete time Markov chain (DTMC) model is proposed to analyze the decoding architecture. The relationship between the input data rate, the clock speed of the decoder and the input buffer size can be easily established via the DTMC model. Different scheduling schemes and decoding modes are proposed and compared. The novel high-throughput decoding architecture is shown to incur 3-10% of the computational complexity of Viterbi decoding at a relatively high SNR.

Low-Decoding-Latency Buffer Compression for Graphics Processing Units

Power consumption is the key design factor for graphics processing units (GPUs), especially for mobile applications. The increasing bandwidth required to produce more realistic graphics is a major power draw. To address this factor, in this paper, we present a new universal buffer compression method that can handle both color and depth data with the same hardware unit. In contrast to the current state-of-art technologies, which mainly focus on achieving higher and higher compression ratios but discarded the decompression latency, our method reaches a good compromise between the two, which are factors critical to system performance. With spatial prediction and bitstream rearrangement, the data dependencies between different samples are reduced, which enables a parallel decoding process and makes the proposed system have 6.78 times lower decoding latency. Moreover, by adopting a similar concept for the color/depth compression in the DXT5 texture compression method, better quality in terms of PSNR can be achieved without introducing any decoding latency when retrieving a texel.

Adaptive ‘soft’ sliding block decoding of convolutional code using the artificial neural network

A Viterbi algorithm (VA) is the optimal decoding strategy for the convolutional code. The Viterbi algorithm is complex and requires a large memory and delay. In this paper, an alternative sub-optimal decoder based on the artificial neural network (ANN) is proposed and studied using a sliding block decoding algorithm. The ANN is trained in a supervised manner and the system parameters are optimised using computer simulations for the optimum performance. Comparative study with the Viterbi decoder is carried out. The performance of the ANN decoder is found to be comparable to the Viterbi ‘soft’ decoding with much reduced decoding length. The key advantages of the proposed ANN decoder compared with other ANN decoders are the reduced decoding and training length, adaptive decoding, no iteration required and possibility of parallel decoding.

Massively parallel neural encoding and decoding of visual stimuli

The massively parallel nature of video Time Encoding Machines (TEMs) calls for scalable, massively parallel decoders that are implemented with neural components. The current generation of decoding algorithms is based on computing the pseudo-inverse of a matrix and does not satisfy these requirements. Here we consider video TEMs with an architecture built using Gabor receptive fields and a population of Integrate-and-Fire neurons. We show how to build a scalable architecture for video Time Decoding Machines using recurrent neural networks. Furthermore, we extend our architecture to handle the reconstruction of visual stimuli encoded with massively parallel video TEMs having neurons with random thresholds. Finally, we discuss in detail our algorithms and demonstrate their scalability and performance on a large scale GPU cluster.

A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder

In this paper, a high throughput context-based adaptive binary arithmetic coding decoder design is proposed. This decoder employs a syntax element prediction method to solve pipeline hazard problems. It also uses a new hybrid memory two-symbol parallel decoding in order to enhance performance as well as to reduce costs. The critical path delay of the two-symbol binary arithmetic decoding engine is improved by 28% with an efficient mathematical transform. Experimental results show that the throughput of our proposed design can reach 485.76 Mbins/s in the high bit-rate coding and 446.2 Mbins/s on average at 264MHz operating frequency, which is sufficient to support H.264/AVC level 5.1 real-time decoding.

Parallel Decoding Scheme Based on OSD and KNIH Algorithms

In this contribution, KNIH algorithm and Ordered Statistic Decoding (OSD) algorithm are investigated, based on which, a novel KNIH-OSD parallel decoding scheme for LDPC codes is proposed. KNIH decoding algorithm processes certain LRPs of a received sequence, while OSD algorithm processes certain MRIPs of a received sequence. If there are too many errors in MRIPs, the OSD algorithm will fail, on the contrary, if there are too many errors in LRPs, the KNIH algorithm will fail. This contribution proposes a parallel decoding scheme based on the complementary characteristic of these two algorithms. Simulation results show that the proposed scheme is feasible and effective. Compared with OSD and KNIH algorithm, the decoding performance is improved.

A Highly Parallel and Scalable CABAC Decoder for Next Generation Video Coding

Future video decoders will need to support high resolutions such as Quad Full HD (QFHD, 4096 × 2160) and fast frame rates (e.g., 120 fps). Many of these decoders will also reside in portable devices. Parallel processing can be used to increase the throughput for higher performance (i.e., processing speed), which can be traded-off for lower power with voltage scaling. The next generation standard called High Efficiency Video Coding (HEVC), which is being developed as a successor to H.264/AVC, not only seeks to improve the coding efficiency but also to account for implementation complexity and leverage parallelism to meet future power and performance demands. This paper presents a silicon prototype for a pre-standard algorithm developed for HEVC (“H.265”) called Massively Parallel CABAC (MP-CABAC) that addresses a key video decoder bottleneck. A scalable test chip is implemented in 65-nm and achieves a throughput of 24.11 bins/cycle, which enables it to decode the max H.264/AVC bit-rate (300 Mb/s) with only a 18 MHz clock at 0.7 V, while consuming 12.3 pJ/bin. At 1.0 V, it decodes a peak of 3026 Mbins/s for a bit-rate of 2.3 Gb/s, enough for QFHD at 186 fps. Both architecture and joint algorithm-architecture optimizations used to reduce critical path delay, area cost and memory size are discussed.

A High-Speed Low-Complexity Time-Multiplexing Reed-Solomon-Based FEC Architecture for Optical Communications

SUMMARY A high-speed low-complexity time-multiplexing ReedSolomon-based forward error correction architecture based on the pipelined truncated inversionless Berlekamp-Massey algorithm is presented in this paper. The proposed architecture has very high speed and very low hardware complexity compared with conventional ReedSolomon-based forward error correction architectures. Hardware complexity is improved by employing a truncated inverse Berlekamp-Massey algorithm. A high-speed and high-throughput data rate is facilitated by employing a three-parallel processing pipelining technique and modified syndrome computation block. The time-multiplexing method for pipelined truncated inversionless Berlekamp-Massey architecture is used in the parallel ReedSolomon decoder to reduce hardware complexity. The proposed architecture has been designed and implemented with 90-nm CMOS technology. Synthesis results show that the proposed 16-channel Reed-Solomon-based forward error correction architecture requires 417,600 gates and can operate at 640 MHz to achieve a throughput of 240 Gb/s. The proposed architecture can be readily applied to Reed-Solomon-based forward error cor

Low-Complexity Memory Access Architectures for Quasi-Cyclic LDPC Decoders

Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.

Design Space of Flexible Multigigabit LDPC Decoders

Multigigabit LDPC decoders are demanded by standards like IEEE 802.15.3c and IEEE 802.11ad. To achieve the high throughput while supporting the needed flexibility, sophisticated architectures are mandatory. This paper comprehensively presents the design space for flexible multigigabit LDPC applications for the first time. The influence of various design parameters on the hardware is investigated in depth. Two new decoder architectures in a 65 nm CMOS technology are presented to further explore the design space. In the past, the memory domination was the bottleneck for throughputs of up to 1 Gbit/s. Our systematic investigation of column‐ versus row‐based partially parallel decoders shows that this is no more a bottleneck for multigigabit architectures. The evolutionary progress in flexible multigigabit LDPC decoder design is highlighted in an extensive comparison of state‐of‐the‐art decoders.

Modified Collision-Free Interleavers for High Speed Turbo Decoding

Inter-window shuffle (IWS) interleavers are a class of collision-free (CF) interleavers that have been applied to parallel turbo decoding. In this paper, we present modified IWS (M-IWS) interleavers that can further increase turbo decoding throughput only at the expense of slight performance degradation. By deriving the number of M-IWS interleavers, we demonstrate that the number is much smaller than that of IWS interleavers, whereas they both have a very simple algebraic representation. Further, it is shown by analysis that under given conditions, storage requirements of M-IWS interleavers can be reduced to only 368 storage bits for variable interleaving lengths. In order to realize parallel outputs of the on-line interleaving addresses, a low-complexity architecture design of M-IWS interleavers for parallel turbo decoding is proposed, which also supports variable interleaving lengths. Therefore, the M-IWS interleavers are very suitable for the turbo decoder in next generation communication systems with the high data rate and low latency requirements.