Parallel Cyclic Redundancy Check Research Articles

An Efficient Parallel CRC Computing Method for High Bandwidth Networks and FPGA Implementation

A cyclic redundancy check (CRC) is a widely used technique in data communication for detecting data transmission errors. However, existing FPGA-based parallel CRC hardware implementation schemes often face problems of excessive resource utilization and timing convergence difficulties in high-bandwidth networks. In addition, these problems are further exacerbated by the variable length of the end of the checksum data frame during data transmission. To address these challenges, this paper proposes a parallel CRC computation method based on precomputed seed values for bit-width normalization (named PSV-WN-CRC). The algorithm selects the corresponding primitive seed value according to the length of the data frame tail and converts the CRC computation with arbitrary bit-width to the CRC computation with fixed bit-width, thus adapting to the case of the indefinite length of the data frame tail. Based on this algorithm, this paper designs an efficient parallel CRC circuit on FPGA to reduce the consumption of resources. The experimental results show that the CRC algorithm and circuit proposed in this paper implemented on Virtex UltraScale+ FPGAs with 1024-bit wide CRC consumes only 5981 LUTs and achieves a maximum throughput of 392.2 Gbps. The method effectively reduces the resource consumption and improves the maximum throughput as compared to three advanced works.

Design and Implementation of Cyclic Redundancy Check with Variable Computing Width Based on Formula Recursive Algorithm

Cyclic Redundancy Check (CRC) is used in cascade with channel coding to improve the convergence of the decoding. In the new generation of wireless communication systems, such as 5G, both code length and code rate are diverse. To improve the decoding efficiency of cascaded systems, a CRC parallel algorithm with variable computing width is proposed in this paper. Based on the existing fixed bit-width parallel algorithm, this algorithm combines the parallel calculation of feedback data and input data in the formula recursive method, realizing a highly parallel CRC check architecture with variable bit-width CRC calculation. Compared with the existing parallel algorithms, the merged algorithm saves the overhead of circuit resources. When the bit-width is fixed, the resource saving effect is obvious, and at the same time, the feedback delay is also optimized by nearly 50%. When the bit-width is variable, the use of resources is also optimized accordingly.

Design and implementation of parallel CRC algorithm for fibre channel on FPGA

Fibre channel (FC) provides the high-speed and low-latency communication between the end systems, widely used in data storage, aerospace applications and large electronic equipment including radar systems. Excellent in error detection and easy to be implemented in hardware, cyclic redundancy check (CRC) is an important error detection method widely used in network data transmission. This study introduces a design and development of parallel CRC algorithm for the hardware implementation on FPGA to meet the specifications for FC. The algorithm can process 128-bit parallel data in a block by broken it into four 32-bit data and calculate their CRC, respectively, based on the linear feedback shift register, simplifying the calculation process and reducing resource consumption.

Parallel CRC architecture for broadband communication systems

Parallel cyclic redundancy check (CRC) architecture for high-throughput forward error correction decoders in broadband communication systems is proposed. Large amount of data bits are needed to be transmitted in a unit of a transport block (TB) in broadband communication systems. Owing to implementation complexity, TB is segmented into multiple small units of code blocks (CBs). The parallel CRC architecture proposed recursively calculates the TB CRC using individual CB CRCs. The proposed parallel CRC architecture is used to balance optimally between memory requirement and computational complexity.

VLSI Implementation of Parallel CRC Using Pipelining, Unfolding and Retiming

Abstract : Error detection is important whenever there is a non-zero chance of data getting corrupted. A Cyclic Redundancy Check (CRC) is the remainder, or residue, of binary division of a potentially long message, by a CRC polynomial. This technique is ubiquitously employed in communication and storage applications due to its effectiveness at detecting errors and malicious tampering. The hardware implementation of a bit-wise CRC is a simple linear feedback shift register. Such a circuit is very simple and can run at very high clock speeds, but it requires the stream to be bit-serial. This means that ‘n’ clock cycles will be required to calculate the CRC values for an n-bit data stream. This latency is intolerable in many high speed data networking applications where data frames need to be processed at high speed and hence implementation of CRC generation and checking on a parallel stream of data becomes desirable. This paper presents implementation of parallel Cyclic Redundancy Check (CRC) based upon DSP algorithms of pipelining, retiming and unfolding. The architectures are first pipelined to reduce the iteration bound by using novel look-ahead techniques and then unfolded and retimed to design high speed parallel circuits. This paper presents the comparison between the parallel implementation of CRC-9 and its serial implementation. It also shows that parallel implementation uses less number of clock cycles than the serial implementation of CRC-9 thereby increasing the speed of the architecture. This paper is implemented using Verilog hardware description language, simulated using Xilinx ISE tools and synthesized using Cadence tools.

Parallel Computation of CRC Using Special Generator Polynomials

CRC (Cyclic Redundancy Check) is an error detection method commonly used in data communication systems, computer networksand storage environments. In this method, the transmitter divides the message by an agreed upon polynomial called the generator and concatenates the calculated residue to the message. The properties of the generator determine the range of errors which are detectable in the receiver side. The division operation is currently performed using serial circuits called Linear Feedback Shift Registers especially in the Ethernetnetwork access protocol. Developing methods for parallel computation of the residue makes CRC suitable for higher layer protocols and software applications. This paper studies a case for parallel CRC computation using special generators which have special multiples called OZO (One-Zero-One) polynomials are divisible. We first provide a system atic approach to finding such polynomials and then design and evaluate the algorithm and the hardware required to perform the parallel division.

High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming

This brief presents a high-speed parallel cyclic redundancy check (CRC) implementation based on unfolding, pipelining, and retiming algorithms. CRC architectures are first pipelined to reduce the iteration bound by using novel look-ahead pipelining methods and then unfolded and retimed to design high-speed parallel circuits. A comparison on commonly used generator polynomials between the proposed design and previously proposed parallel CRC algorithms shows that the proposed design can increase the speed by up to 25% and control or even reduce hardware cost

A universal algorithm for parallel CRC computation and its implementation

Derived from a proposed universal mathematical expression, this paper investigates a novel algorithm for parallel Cyclic Redundancy Check (CRC) computation, which is an iterative algorithm to update the check-bit sequence step by step and suits to various argument selections of CRC computation. The algorithm proposed is quite suitable for hardware implementation. The simulation implementation and performance analysis suggest that it could efficiently speed up the computation compared with the conventional ones. The algorithm is implemented in hardware at as high as 21Gbps, and its usefulness in high-speed CRC computations is implied, such as Asynchronous Transfer Mode (ATM) networks and 10G Ethernet.

A high-performance CMOS 32-bit parallel CRC engine

Design highlights for a 32-bit parallel cyclic redundancy check (CRC) generator engine are presented. In a 0.8-/spl mu/m three-layer-metal CMOS process, the engine could handle about 5 Gbps data throughput. A compact layout is achieved by predecoding eight groups of four bits followed by performing a binary tree reduction on nets that are sorted by fanout. There are six gate delays plus a single-phase clock edge-triggered register.

Parallel realization of the ATM cell header CRC

Parallel Cyclic Redundancy Check (CRC) implementations simultaneously process multiple bits of data in parallel, increasing the data processing rate, with only a relatively small increase in the hardware complexity of serial CRC implementations that process data bit serially. This paper develops octet (8 bit), 16 bit and 32 bit parallel realizations of two serial ATM cell header CRC circuits. We show that both octet parallel ATM cell header CRC implementations can perform CRC error detection at a speed of 4 to 6 times the data processing rate of equivalent serial implementations, with the 16 and 32 bit realizations yielding even greater improvement. We also explore other practical applications of these parallel realizations, such as cell header HEC generation and cell delineation. The circuit operation of the octet parallel CRC Register ATM cell header error detection circuit and octet parallel moving window Polynomial Divider ATM cell delineation circuit has been implemented and verified experimentally in the laboratory, with the circuit operation of all other parallel realizations verified in simulation using MAX+plus II.