Abstract
Parallel cyclic redundancy check (CRC) architecture for high-throughput forward error correction decoders in broadband communication systems is proposed. Large amount of data bits are needed to be transmitted in a unit of a transport block (TB) in broadband communication systems. Owing to implementation complexity, TB is segmented into multiple small units of code blocks (CBs). The parallel CRC architecture proposed recursively calculates the TB CRC using individual CB CRCs. The proposed parallel CRC architecture is used to balance optimally between memory requirement and computational complexity.
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