Parallel Arithmetic Research Articles

On Polynomial Approximation of the Discrete Logarithm and the Diffie—Hellman Mapping

We obtain several lower bounds, exponential in terms of lg p , on the degrees of polynomials and algebraic functions coinciding with values of the discrete logarithm modulo a prime p at sufficiently many points; the number of points can be as little as p1/2 + ? . We also obtain improved lower bounds on the degree and sensitivity of Boolean functions on bits of x deciding whether x is a quadratic residue. Similar bounds are also proved for the Diffie--Hellman mapping gx? gx2 , where g is a primitive root of a finite field of q elements Fq . These results can be used to obtain lower bounds on the parallel arithmetic and Boolean complexity of computing the discrete logarithm and breaking the Diffie--Hellman cryptosystem. The method is based on bounds of character sums and numbers of solutions of some polynomial equations.

Optical arithmetic processing using improved redundant binary algorithms

Carry-free parallel arithmetic computing using redundant binary number representation is exploited. Based on the original two-step algorithm, several improved algorithms including modified two-step, one- step, canonical, and three-input algorithms are proposed to increase processing speed and simplify the implementation system. The symbolic substitution rules for redundant binary addition are represented by binary logic operations and realized using optical space-variant binary logic gates. The proposed optical architecture is suitable for realizing both binary logic and arithmetic operations.

Fast arithmetic for public-key algorithms in Galois fields with composite exponents

The article describes a novel class of arithmetic architectures for Galois fields GF(2/sup k/). The main applications of the architecture are public key systems which are based on the discrete logarithm problem for elliptic curves. The architectures use a representation of the field GF(2/sup k/) as GF((2/sup n/)/sup m/), where k=n/spl middot/m. The approach explores bit parallel arithmetic in the subfield GF(2/sup n/) and serial processing for the extension field arithmetic. This mixed parallel-serial (hybrid) approach can lead to fast implementations. As the core module, a hybrid multiplier is introduced and several optimizations are discussed. We provide two different approaches to squaring. We develop exact expressions for the complexity of parallel squarers in composite fields, which can have a surprisingly low complexity. The hybrid architectures are capable of exploring the time-space trade-off paradigm in a flexible manner. In particular, the number of clock cycles for one field multiplication, which is the atomic operation in most public key schemes, can be reduced by a factor of n compared to other known realizations. The acceleration is achieved at the cost of an increased computational complexity. We describe a proof-of-concept implementation of an ASIC for multiplication and squaring in GF((2/sup n/)/sup m/), m variable.

The multipolynomial channel polynomial residue arithmetic system

The residue number system (RNS) is an integer system appropriate for implementing fast digital signal processors since it can support parallel carry-free high-speed arithmetic. A recent development in residue arithmetic is the polynomial RNS (PRNS) which can perform a polynomial product module (x/sup N//spl plusmn/1) with only S multiplications instead of N/sup 2/, provided that arithmetic takes place in appropriate modular rings. The PRNS, however, has one major limitation in that the sizes of the modular rings used for the PRNS arithmetic are proportional to the size N of the polynomials to be multiplied. As a result, if large polynomials need to be multiplied, large modular rings must be chosen, a fact which can imply severe performance degradation of the entire system. In this paper, a solution to the major limitation of the PRNS is offered. The solution is the multipolynomial channel PRNS, which is capable of performing large polynomial products requiring large dynamic ranges with arithmetic performed in many small modular rings. This way, very high-speed internal PRNS processing is ensured.

Classified one-step high-radix signed-digit arithmetic units

High-radix number systems enable higher information storage density, less complexity, fewer system components, and fewer cascaded gates and operations. A simple one-step fully parallel high-radix signed-digit arithmetic is proposed for parallel optical computing based on new joint spatial encodings. This reduces hardware requirements and improves throughput by reducing the space-bandwidth product needed. The high-radix signed-digit arithmetic operations are based on classifying the neighboring input digit pairs into various groups to reduce the computation rules. A new joint spatial encoding technique is developed to present both the operands and the computation rules. This technique increases the spatial bandwidth product (SBWP) of the spatial light modulators (SLMs) of the system. An optical implementation of the proposed high-radix signed-digit arithmetic operations is also presented. It is shown that our one-step trinary signed-digit (TSD) and quarternary signed-digit (QSD) arithmetic units are much simpler and better than all previously reported high-radix signed-digit techniques.

An arithmetic free parallel mixed-radix conversion algorithm

A new, parallel mixed-radix (MR) conversion algorithm, based upon lookup tables, with no required arithmetic is presented. When pipelined, an effective conversion rate of one conversion per table lookup is achieved. The new algorithm is attractive for hardware implementation since it requires no arithmetic or logical units. The algorithm is shown to be faster than existing pipelined algorithms.

Parallel optical negabinary arithmetic based on logic operations

On the basis of signed-digit negabinary representation, parallel two-step addition and one-step subtraction can be performed for arbitrary-length negabinary operands. The arithmetic is realized by signed logic operations and optically implemented by spatial encoding and decoding techniques. The proposed algorithm and optical system are simple, reliable, and practicable, and they have the property of parallel processing of two-dimensional data. This leads to an efficient design for the optical arithmetic and logic unit.

A new approach to fixed-coefficient inner product computation over finite rings

Inherently parallel arithmetic based on the residue number system (RNS) lends itself very well to implementation of high-speed digital signal processing (DSP) hardware. In most cases, DSP computations can be decomposed to the inner product form Y=/spl Sigma//sub i=0//sup N-1/C/sub i/X/sub i/. Therefore, implementation of the inner product computation over finite rings is of paramount importance for RNS-based DSP hardware. Recently, periodic properties of residues of powers of 2 have been found useful in designing residue arithmetic circuits. This paper presents a deeper insight to the periodicity concepts by applying abstract algebra and number theory methods. Advantage is taken of the fact that the set Z/sub m//sup +/={1, 2, ..., m-1} splits completely, with respect to some g/spl isin/Z/sub m//sup +/, into sets which are closed under multiplication by g modulo m. Properties of such a decomposition of Z/sub m//sup +/ are investigated and the theory is applied to develop new fixed-coefficient inner product circuits for finite-ring arithmetic. The new designs are almost exclusively composed of full adders and they can easily be pipelined to achieve very high throughput. A VLSI implementation study of the new inner product circuits is presented. It shows that, compared with the best method known to date, both smaller area requirements and higher throughput are achieved.

Performance evaluation in image processing with GAPP array processor

The application of parallelism considering the field of image processing is an alternative to implement real time image processing. The data parallelism found in array processors simplify the mapping of this kind of problem as each processing element works on part of the image. The GAPP board (Geometric Arithmetic Parallel Processor) is a near-neighbor mesh architecture with 144 processors interconnected as a 12 × 12 bidimensional array. This work analyzes the performance of the GAPP board regarding image processing. The implementation of two image convolution algorithms and the analyses of the obtained results, as well as the utilization of the GAPP board in this kind of application and the performance achieved are discussed. The results found in this work are also compared to the results presented in [11]. Some ways to achieve a better performance of the GAPP array in this kind of application are also presented.

Efficient error correcting technique for digitalequipment

Error detection/correction represents one of the most stimulating problems to be solved in digital equipment. A residue encoding guarantees the best exploitation of the code redundancy and natural, parallel and fast arithmetic. This approach has been considered in digital signal processing. However, the error correcting procedures are still heavy and time consuming. The authors present a new technique which permits modular and fast error decoding.

High efficiency redundant binary number representations for parallel arithmetic on optical computers

A family of redundant binary number representations, obtained by generalization of the RB (redundant binary) number representation, is introduced. All these number representations are suitable for optical computing and have properties similar to the RB representation. In particular, the p-RB (packed redundant binary) number representation introduced in this work has efficiency greater than both RB and MSD (modified signed digit) representations. With p-RB numbers the algebraic sum is always permitted in constant time for any efficiency value. p-RB representations also fit in a natural way the 2's complement binary number system. Symbolic substitution truth tables for the algebraic sum and several examples of computation are also given.

Redundant binary number representation for an inherently parallel arithmetic on optical computers

A simple redundant binary number representation suitable for digital-optical computers is presented. By means of this representation it is possible to build an arithmetic with carry-free parallel algebraic sums carried out in constant time and parallel multiplication in log N time. This redundant number representation naturally fits the 2's complement binary number system and permits the construction of inherently parallel arithmetic units that are used in various optical technologies. Some properties of this number representation and several examples of computation are presented.

A fast algorithm for gaussian elimination over GF(2) and its implementation on the GAPP

A fast algorithm for Gaussian elimination over GF(2) is proposed. The proposed algorithm employs binary search technique to locate is along the columns of the large binary matrix being triangularized. The algorithm requires 2 m 2 + m log 2 n - 2 m bit operations to triangularize an n × m matrix on a bit-array with n processors and m + 2 + [log 2 n] bits of vertical memory per processor. Details of an implementation on the Geometric Arithmetic Parallel Processor are also presented.

Fast Parallel Arithmetic via Modular Representation

An almost uniform $NC^1 $ circuit family for integer division is presented. The circuit size is $O(n^6 / \log (n))$. The circuit design is based on modular representation for integers below $2^n $. In particular, a very efficient technique is introduced for computing “$a < b$?” when a and b in modular representation. This leads to a uniform $NC^1 $ circuit of $O(n^2 )$ size for comparison of integers in modular representation.

Normalized Convergence Rates for the PSMG Method

In a previous paper [“Parallel Superconvergent Multigrid,” in Multigrid Methods, Marcel Dekker, New York, 1988] the authors introduced an efficient multiscale PDE solver for massively parallel architectures, which was called Parallel Superconvergent Multigrid, or PSMG. In this paper, sharp estimates are derived for the normalized work involved in PSMG solution—the number of parallel arithmetic and communication operations required per digit of error reduction. PSMG is shown to provide fourth-order accurate solutions of Poisson-type equations at convergence rates of .00165 per single relaxation iteration, and with parallel operation counts per grid level of 5.75 communications and 8.62 computations for each digit of error reduction. The authors show that PSMG requires less than one-half as many arithmetic and one-fifth as many communication operations, per digit of error reduction, as a parallel standard multigrid algorithm (RBTRB) presented recently by Decker [SIAM J. Sci. Statist. Comput., 12 (1991), pp. 208–220].

Fast hybrid parallel carry look-ahead adder

A new optical parallel arithmetic processing scheme using a nonholographic optoelectronic content-addressable memory (CAM) is discussed. The design of a four-bit CAM-based optical carry look-ahead adder (CLA) is presented. Compared with existing optoelectronic binary addition approaches, this nonholographic CAM scheme offers a number of practical advantages, such as faster processing speed and ease of optical implementation and alignment. For the addition of numbers longer than four bits, by incorporating the previous stages' carry, a number of four-bit CLA's can be cascaded. Experimental results are also presented.

A preliminary evaluation of a massively parallel processor: GAPP

The Geometric Arithmetic Parallel Processor (GAPP) is a systolic planar array processor with 72 (6 × 12) processing elements arranged in a mesh network. It runs at a clock speed of 10 MHz. The greatest advantage of such a design is that as many processor chips as are needed can be implemented without the loss of processing speed as interprocessor communication has been designed into the hardware architecture. It is therefore particularly suitable for processing of large image files with SIMD type of program execution. In this paper we report our study of the GAPP's performance in comparison with a number of other array processor systems, including: CLIP4, ICL DAP and Goodyear MPP. We also compare GAPP with some DSPs such as TMS32020, INMOS Transputer. We have found that GAPP's performance is in the same order of magnitude as these processors.

Detection of weak, subpixel targets using mesh-connected cellular automata

Effective use of military cellular automata such as military data array processor (MilDAP) and geometric arithmetic parallel processor (GAPP), in weak, subpixel target detection is shown to be possible by using new signal processing regimes based on binary ranking filter theory. By using binary ranking filters, the MilDAP can furnish 6 dB of processing gain against white Gaussian noise while monitoring from one to four million potential target tracks at 10-40 frames/s. GAPP is shown to be capable of monitoring 3.7 million tracks over 216*384 detectors at 14000 frames/s and, in a time sharing mode, 15 million tracks over 432*768 detectors at 24 frames/s. The special case of threatening targets is discussed, as well as alternate cellular architectures which use multidimensional binary ranking filters in multidimensional coordinate systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Parallel optical arithmetic on images by a redundant binary number representation

A redundant binary number representation allows the algebraic sum on signed numbers in constant time. This number representation is suitable for parallel arithmetic on images made by symbolic substitution on optical computers.

A Neural Net Associative Memory for Real-Time Applications

A parallel hardware implementation of the associative memory neural network introduced by Hopfield is described. The design utilizes the Geometric Arithmetic Parallel Processor (GAPP), a commercially available single-chip VLSI general-purpose array processor consisting of 72 processing elements. The ability to cascade these chips allows large arrays of processors to be easily constructed and used to implement the Hopfield network. The memory requirements and processing times of such arrays are analyzed based on the number of nodes in the network and the number of exemplar patterns. Compared with other digital implementations, this design yields significant improvements in runtime performance and offers the capability of using large neural network associative memories in real-time applications.