Parallel Architecture Research Articles

Lightweight human activity recognition method based on the MobileHARC model

In recent years, Human activity recognition (HAR) based on wearable devices has been widely applied in health applications and other fields. Currently, most HAR models are based on the Convolutional Neural Network (CNN), Long Short-Term Memory (LSTM), or their combination. Recently, there have been proposals based on Transformer and its variant models. However, due to the fact that these models have sequential network structures and are unable to simultaneously focus on local and global features, thus, resulting in a reduction in recognition performance. In addition, along with the substantial computational resources required by Transformers, they are not suitable for resource-constrained devices. In this paper, the primary distinction of our proposed model from other hybrid models that combine CNN and Transformer is that our model adopts a completely new parallel network architecture and primarily focuses on lightweight design. Particularly, We proposed the Mobile Human Activity Recognition Conformer (MobileHARC), which adopts the parallel structure with a lightweight Transformer and CNN as the backbone networks. Furthermore, we proposed the Inverted Residual Lightweight Convolution Block and Multiscale Lightweight Multi-Head Self-Attention Mechanism. We systematically evaluate the proposed models on four public datasets. Experimental results show that MobileHARC achieves superior recognition performance, and uses fewer Floating-Point Operations per Second (FLOPs) and parameters compared to current models.

Kinematics Mathematical Modelling of Lower Limb Exoskeleton for Paralyzed Stroke Patients

This paper presents the development of a lower limb rehabilitation robot to be used with bedridden patients. Strokes are one of the significant causes of death in 17% of the 109,155 medically certified death in 2020 in Malaysia. In most cases, stroke paralysis affects the opposite side of the damaged brain, and any part of the body can be affected. 90% of stroke patients get paralysis to some degree. Patients can recover from the disease and restore body motions by undergoing paralysis stroke physiotherapy, which involves numerous sessions with patients. There were several successful robotic rehabilitations in recent years; however, their design is inflexible and large, requiring the patient to sit or stand in a static position. This project will be built on a motor-driven parallel architecture that will offer motion assistance throughout the human’s wide range of motion (ROM). This project development is divided into two parts: structure design and simulation. The design process for the lower limb devices used syncretization and mathematical analysis. The structure design is from the kinematic analysis. The mathematical models are then used to design in MATLAB simulation which is trajectory simulation. The outcome shows that the simulations that have been developed is compatible with the motion of human lower limb. This robot develops for bedridden use of lower limb rehabilitation exercises.

Harnessing Manycore Processors with Distributed Memory for Accelerated Training of Sparse and Recurrent Models

Current AI training infrastructure is dominated by single instruction multiple data (SIMD) and systolic array architectures, such as Graphics Processing Units (GPUs) and Tensor Processing Units (TPUs), that excel at accelerating parallel workloads and dense vector matrix multiplications. Potentially more efficient neural network models utilizing sparsity and recurrence cannot leverage the full power of SIMD processor and are thus at a severe disadvantage compared to today's prominent parallel architectures like Transformers and CNNs, thereby hindering the path towards more sustainable AI. To overcome this limitation, we explore sparse and recurrent model training on a massively parallel multiple instruction multiple data (MIMD) architecture with distributed local memory. We implement a training routine based on backpropagation though time (BPTT) for the brain-inspired class of Spiking Neural Networks (SNNs) that feature binary sparse activations. We observe a massive advantage in using sparse activation tensors with a MIMD processor, the Intelligence Processing Unit (IPU) compared to GPUs. On training workloads, our results demonstrate 5-10x throughput gains compared to A100 GPUs and up to 38x gains for higher levels of activation sparsity, without a significant slowdown in training convergence or reduction in final model performance. Furthermore, our results show highly promising trends for both single and multi IPU configurations as we scale up to larger model sizes. Our work paves the way towards more efficient, non-standard models via AI training hardware beyond GPUs, and competitive large scale SNN models.

Global to multi‐scale local architecture with hardwired CNN for 1‐ms tomato defect detection

AbstractA 1 millisecond (1‐ms) vision system that guarantees high efficiency and timely response for tomato defect detection is essential for factory automation. Because of various defect appearances, recently many existing researches focus on CNN based defect detection, but few of them attempt to reach high processing speed to adapt to the factorial assembly line. This paper proposes a global to multi‐scale local based parallel architecture with hardwired CNN for tomato defect detection. This architecture breaks down image‐wise detection into pixel‐wise localization and block‐wise classification. The pixel‐wise localization utilizes tomato‐aware information as constraints for localization performance. The block‐wise classification uses a fully pipelined network structure to obtain the classification result for each block as the pixel stream moves through the network. The classification network has a six‐layer lightweight network structure with quantization for hardwired type implementation on FPGA. The experiment results show that the proposed architecture processes 1000 FPS images with 0.9476 ms/frame delay. And for detection performance, this architecture keeps at 80.18%, only 1.31% lower than ResNet50 based detection system.

Extending the Architecture of Language From a Multimodal Perspective.

Language is inherently multimodal. In spoken languages, combined spoken and visual signals (e.g., co-speech gestures) are an integral part of linguistic structure and language representation. This requires an extension of the parallel architecture, which needs to include the visual signals concomitant to speech. We present the evidence for the multimodality of language. In addition, we propose that distributional semantics might provide a format for integrating speech and co-speech gestures in a common semantic representation.

EPHA: An Energy-efficient Parallel Hybrid Architecture for ANNs and SNNs

Artificial neural networks (ANNs) and spiking neural networks (SNNs) are two general approaches to achieve artificial intelligence (AI). The former have been widely used in academia and industry fields; the latter, SNNs, are more similar to biological neural networks and can realize ultra-low power consumption, thus have received widespread research attention. However, due to their fundamental differences in computation formula and information coding, the two methods often require different and incompatible platforms. Alongside the development of AI, a general platform that can support both ANNs and SNNs is necessary. Moreover, there are some similarities between ANNs and SNNs, which leaves room to deploy different networks on the same architecture. However, there is little related research on this topic. Accordingly, this article presents an energy-efficient, scalable, and non-Von Neumann architecture (EPHA) for ANNs and SNNs. Our study combines device-, circuit-, architecture-, and algorithm-level innovations to achieve a parallel architecture with ultra-low power consumption. We use the compensated ferrimagnet to act as both synapses and neurons to store weights and perform dot-product operations, respectively. Moreover, we propose a novel computing flow to reduce the operations across multiple crossbar arrays, which enables our design to conduct large and complex tasks. On a suite of ANN and SNN workloads, the EPHA is 1.6× more power-efficient than a state-of-the-art design, NEBULA, in the ANN mode. In the SNN mode, our design is 4 orders of magnitude more than the Loihi in power efficiency.

Real‐time assessment on health state for bearing based on parallel encoder‐decoder observer

AbstractBearings are foundational supporting components in diverse mechanical systems, essential for the reliable operation of these systems through real‐time monitoring and precise health state assessment. However, vibration signals from bearings in practical equipment often contain excessive noise and redundant information, complicating health state assessment. To address this challenge, this paper proposes a neural network‐based method named parallel encoder‐decoder (PED). This method features a parallel architecture that combines the long short‐term memory network and the temporal convolutional network for the encoder, along with a self‐attention module for the decoder. PED is adept at learning the temporal representations hidden in original signals and filtering vibration signals to remove noise and redundant information. Additionally, a multi‐objective loss function is developed to enhance the prediction results. A normalized Mahalanobis distance‐based metric is then employed to compare residual signals during bearing operation with those under normal conditions. The case study evaluates the PED observer's proficiency in accurately predicting vibration signals and assessing the performance of health indicator curves, demonstrating the proposed PED observer's superiority over conventional networks.

Real-time Arabic Video Captioning Using CNN and Transformer Networks Based on Parallel Implementation

Video captioning techniques have practical applications in fields like video surveillance and robotic vision, particularly in real-time scenarios. However, most of the current approaches still exhibit certain limitations when applied to live video, and research has predominantly focused on English language captioning. In this paper, we introduced a novel approach for live real-time Arabic video captioning using deep neural networks with a parallel architecture implementation. The proposed model primarily relied on the encoder-decoder architecture trained end-to-end on Arabic text. Video Swin Transformer and deep convolutional network are employed for video understanding, while the standard Transformer architecture is utilized for both video feature encoding and caption decoding. Results from experiments conducted on the translated MSVD and MSR-VTT datasets demonstrate that utilizing an end-to-end Arabic model yielded better performance than methods involving the translation of generated English captions to Arabic. Our approach demonstrates notable advancements over compared methods, yielding a CIDEr score of 78.3 and 36.3 for the MSVD and MSRVTT datasets, respectively. In the context of inference speed, our model achieved a latency of approximately 95 ms using an RTX 3090 GPU for a temporal video segment with 16 frames captured online from a camera device.

Accelerating the detection of DNA differentially methylated regions using multiple GPUs

DNA methylation analysis has become an important topic in the study of human health. In previous work, we developed a suite of tools to perform this analysis. It includes HPG-Dhunter, a web-based tool for automatic detection of differentially methylated regions (DMRs) between different samples. The back-end of that tool receives an undefined number of simultaneous requests to detect DMRs on different datasets. Currently, simultaneous requests are queued and processed one at a time. This paper proposes a parallel architecture where multiple daemons serve requests simultaneously. Daemons can also share the same physical GPUs. A scheduler manages requests and forwards them to daemons. The number of daemons per GPU is configurable, thus adapting the architecture to the available hardware. Results show that the proposed parallel architecture hugely reduces the execution time. Furthermore, the speedup increases proportionally to the number of available GPUs (up to 7.47x in our experimental setup).

Optimizing dual modal biometric authentication: hybrid HPO-ANFIS and HPO-CNN framework

In the realm of secure data access, biometric authentication frameworks are vital. This work proposes a hybrid model, with a 90% confidence interval, that combines "hyperparameter optimization-adaptive neuro-fuzzy inference system (HPO-ANFIS)" parallel and "hyperparameter optimization-convolutional neural network (HPO-CNN)" sequential techniques. This approach addresses challenges in feature selection, hyperparameter optimization (HPO), and classification in dual multimodal biometric authentication. HPO-ANFIS optimizes feature selection, enhancing discriminative abilities, resulting in improved accuracy and reduced false acceptance and rejection rates in the parallel modal architecture. Meanwhile, HPO-CNN focuses on optimizing network designs and parameters in the sequential modal architecture. The hybrid model's 90% confidence interval ensures accurate and statistically significant performance evaluation, enhancing overall system accuracy, precision, recall, F1 score, and specificity. Through rigorous analysis and comparison, the hybrid model surpasses existing approaches across critical criteria, providing an advanced solution for secure and accurate biometric authentication.

RIBM3DU‐Net: Glioma tumour substructures segmentation in magnetic resonance images using residual‐inception block with modified 3D U‐Net architecture

AbstractGlioma brain tumour is one of the life‐threatening diseases in the world. Tumour substructure segmentation by physicians is a time‐consuming task with the magnetic resonance imaging (MRI) technique due to the size of clinical data. An automatic and well‐trained method is essential to detect and segment the tumour which increase the survival of the patients. The proposed work aims to produce high accuracy on glioma substructures segmentation with less computation time using deep learning. From the literature survey, the following challenges are found: (i) computing complex spatial boundaries between normal and tumour tissues, (ii) feature reduction and (iii) overfitting problems. Hence, we proposed a fully automatic glioma tumour segmentation using a residual‐inception block (RIB) with a modified 3D U‐Net (RIBM3DU‐Net). It includes three phases: pre‐processing, modified 3D U‐Net segmentation and post‐processing. From the results, RIB with U‐Net enhances the segmentation accuracy. GPU parallel architecture reduces the computation time while training and testing. For quantitative analysis, comprehensive experiment results were computed and compared with state‐of‐the‐art methods. It achieves better Dice scores on enhancing tumour, tumour core and complete tumour of 87%, 87% and 94%, respectively. GPU speedup folds yield up to 48× when compared with CPU. Quantitatively, 3D glioma volume is rendered from the obtained segmented results and estimated using the Cavalieri estimator.

ДОСЛІДЖЕННЯ ЕФЕКТИВНОСТІ ПАРАЛЕЛЬНОЇ ОБЧИСЛЮВАЛЬНОЇ СХЕМИ ІДЕНТИФІКАЦІЇ ІНТЕРВАЛЬНИХ ДИСКРЕТНИХ МОДЕЛЕЙ НА ОСНОВІ РОЙОВОГО ІНТЕЛЕКТУ

The research addressed in the paper focuses on organizing computations to solve NP-complex problems. Specifically, it examines the task of parametric identification of discrete models with distributed parameters based on the analysis of interval data. Computational algorithms inspired by the behavioral models of honeybee colonies are proposed to address this task. The application of the proposed algorithm enhances the efficiency of solving parametric identification problems for interval discrete models with distributed parameters, albeit with high computational time complexity. Therefore, the study suggests using parallel computing algorithms to reduce the time complexity. To assess the effectiveness of parallel computing in identifying interval discrete models with distributed parameters, computational experiments are proposed using examples of modeling air distribution and pollution by automotive exhaust emissions. The computational experiments, based on behavioral models of honeybee colonies on a four-core processor, demonstrate increased efficiency in all experiments, with higher task complexity leading to greater parallelization efficiency. However, it is noted that the average number of generations required for the parallel algorithm to find a solution is significantly higher in some experiments compared to the sequential algorithm. This sensitivity indicates that the algorithm is highly influenced by the initially generated points in the solution search space. Overall, the study establishes the feasibility of parallelizing the computational scheme for solving parametric identification problems on other promising parallel architectures, such as graphical processors.

Optimization of layout for embedding half hypercube into conventional tree architectures

SummaryEmbedding a graph into another graph can be utilized for structural simulation, processor allocation, and algorithm porting in the field of parallel architecture. This has the potential to enhance the physical layout of network‐on‐chip (NoC) devices as well as to investigate their virtualization possibilities. Layout is one of the many indicators of graph embedding. An optimal layout in NoC design can result in a decreased wiring area and cost, as well as the reduction in communication delay between parallel processing components. In this work, the guest graph is the half hypercube, which possess efficient routing, fault tolerance, and Hamiltonian features. The edge isoperimetric problems is solved for the half hypercube using a novel technique called the isochronal ordering. The host graphs considered in our work are complete binary trees, ‐rooted complete binary trees, and other few predominantly investigated tree based architectures.

Parallel Implementation of Lightweight Secure Hash Algorithm on CPU and GPU Environments

Currently, cryptographic hash functions are widely used in various applications, including message authentication codes, cryptographic random generators, digital signatures, key derivation functions, and post-quantum algorithms. Notably, they play a vital role in establishing secure communication between servers and clients. Specifically, servers often need to compute a large number of hash functions simultaneously to provide smooth services to connected clients. In this paper, we present highly optimized parallel implementations of Lightweight Secure Hash (LSH), a hash algorithm developed in Korea, on server sides. To optimize LSH performance, we leverage two parallel architectures: AVX-512 on high-end CPUs and NVIDIA GPUs. In essence, we introduce a word-level parallel processing design suitable for AVX-512 instruction sets and a data parallel processing design appropriate for the NVIDIA CUDA platform. In the former approach, we parallelize the core functions of LSH using AVX-512 registers and instructions. As a result, our first implementation achieves a performance improvement of up to 50.37% compared to the latest LSH AVX-2 implementation. In the latter approach, we optimize the core operation of LSH with CUDA PTX assembly and apply a coalesced memory access pattern. Furthermore, we determine the optimal number of blocks/threads configuration and CUDA streams for RTX 2080Ti and RTX 3090. Consequently, in the RTX 3090 architecture, our optimized CUDA implementation achieves about a 180.62% performance improvement compared with the initially ported LSH implementation to the CUDA platform. As far as we know, this is the first work on optimizing LSH with AVX-512 and NVIDIA GPU. The proposed implementation methodologies can be used alone or together in a server environment to achieve the maximum throughput of LSH computation.

Implementation of Highly Reliable Convolutional Neural Network with Low Overhead on Field-Programmable Gate Array

Due to the advantages of parallel architecture and low power consumption, a field-programmable gate array (FPGA) is typically utilized as the hardware for convolutional neural network (CNN) accelerators. However, SRAM-based FPGA devices are extremely susceptible to single-event upsets (SEUs) induced by space radiation. In this paper, a fault tolerance analysis and fault injection experiments are applied to a CNN accelerator, and the overall results show that SEUs occurring in a control unit (CTRL) lead to the highest system error rate, which is over 70%. After that, a hybrid hardening strategy consisting of a finite state machine error-correcting circuit (FSM-ECC) and a triple modular redundancy automatic hardening technique (TMR-AHT) is proposed in this paper to achieve a tradeoff between radiation reliability and design overhead. Moreover, the proposed methodology has very small workload and good migration ability. Finally, by full exploiting the fault tolerance property of CNNs, a highly reliable CNN accelerator with the proposed hybrid hardening strategy is implemented with Xilinx Zynq-7035. When BER is 2 × 10−6, the proposed hybrid hardening strategy reduces the whole system error rate by 78.95% with the overhead of an extra 20.7% of look-up tables (LUTs) and 20.9% of flip-flops (FFs).

Analyzing GPU Performance in Virtualized Environments: A Case Study

The graphics processing unit (GPU) plays a crucial role in boosting application performance and enhancing computational tasks. Thanks to its parallel architecture and energy efficiency, the GPU has become essential in many computing scenarios. On the other hand, the advent of GPU virtualization has been a significant breakthrough, as it provides scalable and adaptable GPU resources for virtual machines. However, this technology faces challenges in debugging and analyzing the performance of GPU-accelerated applications. Most current performance tools do not support virtual GPUs (vGPUs), highlighting the need for more advanced tools. Thus, this article introduces a novel performance analysis tool that is designed for systems using vGPUs. Our tool is compatible with the Intel GVT-g virtualization solution, although its underlying principles can apply to many vGPU-based systems. Our tool uses software tracing techniques to gather detailed runtime data and generate relevant performance metrics. It also offers many synchronized graphical views, which gives practitioners deep insights into GVT-g operations and helps them identify potential performance bottlenecks in vGPU-enabled virtual machines.

Methodology to generate earthquake-tsunami fragility surfaces for community resilience modeling

Community resilience analysis and performance-based tsunami design methods typically use separate fragility curves for earthquake and near-field tsunami hazards to predict damage, neglecting the direct cascading effects of the earthquake damage on the subsequent tsunami damage analysis for coastal communities. This paper presents an improved two-phase successive analysis that can incorporate the most significant sources of uncertainties in structural modeling and hazards. However, generating multi-hazard 3D fragility surfaces that fully incorporate uncertainties through Monte Carlo Simulation requires millions of successive nonlinear analyses, which can be computationally intensive. To address this issue, a multi-distributed and parallel processing architecture was used and summarized herein. This methodology has been applied to a 4-story RC building as an illustrative example and demonstrated to be highly efficient and scalable in generating near-continuous fragility surfaces for earthquake and tsunami hazards, reducing the expected computational time by over 98%. Due to their near-continuous characteristic, these surfaces are easier to implement in resilience frameworks and applications. The fragility surfaces also feature earthquake-only and tsunami-only 2D fragility curves along the intensity measure axis boundaries, making them versatile for use in resilience frameworks that focus on a single hazard or both earthquake and tsunami hazards. Therefore, the proposed method is scalable making it helpful in developing fragility models for building portfolios to be used at the community resilience modeling of full coastal cities.

A Spiking LSTM Accelerator for Automatic Speech Recognition Application Based on FPGA

Long Short-Term Memory (LSTM) finds extensive application in sequential learning tasks, notably in speech recognition. However, existing accelerators tailored for traditional LSTM networks grapple with high power consumption, primarily due to the intensive matrix–vector multiplication operations inherent to LSTM networks. In contrast, the spiking LSTM network has been designed to avoid these multiplication operations by replacing multiplication and nonlinear functions with addition and comparison. In this paper, we present an FPGA-based accelerator specifically designed for spiking LSTM networks. Firstly, we employ a low-cost circuit in the LSTM gate to significantly reduce power consumption and hardware cost. Secondly, we propose a serial–parallel processing architecture along with hardware implementation to reduce inference latency. Thirdly, we quantize and efficiently deploy the synapses of the spiking LSTM network. The power consumption of the accelerator implemented on Artix-7 and Zynq-7000 is only about 1.1 W and 0.84 W, respectively, when performing the inference for speech recognition with the Free Spoken Digit Dataset (FSDD). Additionally, the energy consumed per inference is remarkably efficient, with values of 87 µJ and 66 µJ, respectively. In comparison with dedicated accelerators designed for traditional LSTM networks, our spiking LSTM accelerator achieves a remarkable reduction in power consumption, amounting to orders of magnitude.

UPFormer: U-sharped Perception lightweight Transformer for segmentation of field grape leaf diseases

In the smart agriculture community, segmentation models are de-facto for the timely detection and identification of plant diseases. However, the complex background and the small diseases make it challenging to segment the grape leaf disease. The performance improvement trend of the existing models comes at the cost of model size and computational cost, which hinders deployment on resource-constrained hardware. Towards this end, we propose a tailored lightweight segmentation architecture referred to as the U-sharped Perception Transformer (UPFormer) for field grape leaf diseases, which achieves a better trade-off between performance and efficiency. Concretely, we leverage the U-shaped hierarchy to acquire small tokens with superior cost efficiency. The prototype perception and the pixel-aware broadcast are developed in parallel architectures to learn low-frequency global information and mine high-frequency local information for small diseases in complex environments. Besides, a fast token aggregation recipe is designed to compensate for the sacrificed detail information in an efficient aggregation paradigm without increasing the count of parameters. Extensive experiments have demonstrated that UPFormer remarkably outperforms existing CNNs, ViTs, and CNN-Transformer hybrid architectures on the datasets, including Field-PV, Syn-PV, and Plant Village.

Detailed parallel social modeling for the analysis of COVID-19 spread

Agent-based epidemiological simulators have been proven to be one of the most successful tools for the analysis of COVID-19 propagation. The ability of these tools to reproduce the behavior and interactions of each single individual leads to accurate and detailed results, which can be used to model fine-grained health-related policies like selective vaccination campaigns or immunity waning. One characteristic of these tools is the large amount of input data and computational resources that they require. This relies on the development of parallel algorithms and methodologies for generating, accessing, and processing large volumes of data from multiple data sources. This work presents a parallel workflow for extending the social modeling of EpiGraph, an agent-based simulator. We have included two novel parallel social generation stages that generate a detailed and realistic social model and one new visualization stage. This work also presents a description of the algorithms used in each stage, different optimization techniques that permit to reduce the application convergence time, and a practical evaluation of large workloads on HPC systems. Results show that this contribution can be efficiently executed in parallel architectures and the results allow to increase the simulation detail level, representing a significant advance in the simulator scenario modeling. As a summary of results, the first contribution of this paper is the development of two models (a spatial and a social one) that assign geographical and socioeconomic indicators to each simulated individual (i.e., agents), reproducing the real social distribution of the city of Madrid. The second contribution presents an improved parallel and distributed algorithm that executes the two aforementioned models using different parallelization strategies and preserving the load balance.