Packet Switch Design Research Articles

Analysis of Hybrid Buffer Based Optical Data Center Switch

AbstractDue to the explosive growth in internet traffic, servers are facing bottleneck in speed and bandwidth requirements. To meet these ever increasing demands fiber optic technology can be used. This paper discusses, a hybrid buffer based optical packet switch design with its pros and cons. This hybrid buffer offers both electronic and optical buffering. This paper investigates the packet loss rate (PLR) performance of hybrid buffer under variety of conditions. The usage of buffer under different loading conditions has discussed. The sharing of electronic and optical buffers with respect to arrival of traffic is simulated, and delay ratio of electronic to optical buffering is computed. Average energy consumption at various loading condition is evaluated. The performance of switch is also investigated in a hypothetical five nodes network, and PLR is obtained under four different combinations of buffering and deflection of contending packets.

High-Port and Low-Latency Optical Switches for Disaggregated Data Centers: The Hipoλaos Switch Architecture [Invited

The emergence of disaggregation in data center (DC) architectures as a way to increase resource utilization introduces significant challenges to the DC switching infrastructure, which has to ensure high bandwidth and low-latency communication along with high-radix connectivity. This paper examines the network requirements in disaggregated systems and reviews the credentials of state-of-the-art high-radix optical switch architectures. We also demonstrate a novel optical packet switch design, called Hipoλaos, that satisfies these requirements by combining N-port broadcast-and-select and N × N arrayed waveguide grating router-based forwarding schemes in N2-port connectivity configurations. The Hipoλaos switch provides sub-μs latency and high throughput performance by utilizing distributed control and optical feed-forward buffering in a modified Spanke architecture. Feasibility of a 256 port Hipoλaos layout with a four-packet buffering stage is experimentally demonstrated at 10 Gb/s, revealing error-free performance with a mean power penalty value of 2.19 dB. Simulation analysis is carried out for a 256 node system and eight traffic profiles; this analysis reveals a low latency value of only 605 ns, with throughput reaching 85% even when employing only two-packet buffers. Finally, the architecture’s scalability up to 1024 × 1024 designs is discussed, along with a power consumption analysis and a roadmap toward an integrated version of the switch.

Design of Efficient Pipelined Router Architecture for 3D Network on Chip

As a relevant communication structure for integrated circuits, Network-on-Chip (NoC) architecture has attracted a range of research topics. Compared to conventional bus technology, NoC provides higher scalability and enhances the system performance for future System-on-Chip (SoC). Divergently, we presented the packet-switching router design for 2D NoC which supports 2D mesh topology. Despite the offered benefits compared to conventional bus technology, NoC architecture faces some limitations such as high cost communication, high power consumption and inefficient router pipeline usage. One of the proposed solutions is 3D design. In this context, we suggest router architecture for 3D mesh NoC, a natural extension of our prior 2D router design. The proposal uses the wormhole switching and employs the turn mod negative-first routing algorithm Thus, deadlocks are avoided and dynamic arbiter are implemented to deal with the Quality of Service (QoS) expected by the network. We also adduce an optimization technique for the router pipeline stages. We prototyped the proposal on FPGA and synthesized under Synopsys tool using the 28 nm technology. Results are delivered and compared with other famous works in terms of maximal clock frequency, area, power consumption and estimated peak performance.

Toward Ideal On-Chip Communication Using Express Virtual Channels

Current on-chip networks use a packet-switched design with a complex router at every hop, which imposes significant communication energy, delay, and throughput overhead. we propose reducing energy and delay, and increasing throughput, using express virtual channels. packets traveling along these virtual express lanes, which connect distant nodes in the network, bypass intermediate routers, significantly reducing router overhead.

Express virtual channels

Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the pervasive communication fabric to connect different processing elements in many-core chips. However, current state-of-the-art packet-switched networks rely on complex routers which increases the communication overhead and energy consumption as compared to the ideal interconnection fabric. In this paper, we try to close the gap between the state-of-the-art packet-switched network and the ideal interconnect by proposing express virtual channels (EVCs), a novel flow control mechanism which allows packets to virtually bypass intermediate routers along their path in a completely non-speculative fashion, thereby lowering the energy/delay towards that of a dedicated wire while simultaneously approaching ideal throughput with a practical design suitable for on-chip networks. Our evaluation results using a detailed cycle-accurate simulator on a range of synthetic traffic and SPLASH benchmark traces show upto 84% reduction in packet latency and upto 23% improvement in throughput while reducing the average router energy consumption by upto 38% over an existing state-of-the-art packet-switched design. When compared to the ideal interconnect, EVCs add just two cycles to the no-load latency, and are within 14% of the ideal throughput. Moreover, we show that the proposed design incurs a minimal hardware overhead while exhibiting excellent scalability with increasing network sizes.

Algorithms for IP network design with end-to-end QoS constraints

The new generation of packet-switching networks is expected to support a wide range of communication-intensive real-time multimedia applications. A key issue in the area is how to devise reasonable packet-switching network design methodologies that allow the choice of the most adequate set of network resources for the delivery of a given mix of services with the desired level of end-to-end Quality of Service (e2e QoS) and, at the same time, consider the traffic dynamics of today’s packet-switching networks. In this paper, we focus on problems that arise when dealing with this subject, namely Buffer Assignment (BA), Capacity Assignment (CA), Flow and Capacity Assignment (FCA), Topology, Flow and Capacity Assignment (TCFA) problems. Our proposed approach maps the end-user’s performance constraints into transport-layer performance constraints first, and then into network-layer performance constraints. This mapping is then considered together with a refined TCP/IP traffic modeling technique, that is both simple and capable of producing accurate performance estimates, for general-topology packet-switching design networks subject to realistic traffic patterns. Subproblems are derived from a general design problem and a collection of heuristic algorithms are introduced for compute approximate solutions. We illustrate examples of network planning/dimensioning considering Virtual Private Networks (VPNs).

Current issues in packet switch design

Addressing the ever growing capacity demand for packet switches, current research focuses on scheduling algorithms or buffer bandwidth reductions. Although these topics remain relevant, our position is that the primary design focus for systems beyond 1 Tb/s must be shifted to aspects resulting from packaging disruptions. Based on trends such as increased link rates and improved CMOS technologies, we derive new design factors for such switch fabrics. For instance, we argue that the packet round-trip transmission time within the fabric has become a major design parameter. Furthermore, we observe that high-speed fabrics have become extremely dependent on serial I/O technology that is both high speed and high density. Finally, we conclude that in developing the architecture, packaging constraints must be put first and not as an afterthought, which also applies to solving the tremendous power consumption challenges.

Wavelength conversion in optical packet switching

A detailed traffic analysis of optical packet switch design is performed. Special consideration is given to the complexity of the optical buffering and the overall switch block structure is considered in general. Wavelength converters are shown to improve the traffic performance of the switch blocks for both random and bursty traffic. Furthermore, the traffic performance of switch blocks with add-drop switches has been assessed in a Shufflenetwork showing the advantage of having converters at the inlets. Finally, the aspect of synchronization is discussed through a proposal to operate the packet switch block asynchronously, i.e. without packet alignment at the input.

Performance of trunk grouping in packet switch design

This paper studies the performance of trunk grouping in packet switch system design, with emphasis on the analysis of maximum throughput, input queue delay and packet loss rate. The trunk grouping technique can be implemented on both sides of the switch. In principle, the output trunk grouping relieves traffic output contentions, while the input trunk grouping, proposed in this paper, prevents individual input links from overloading. The study shows a significant advantage of both input and output trunk groupings in removing local congestions caused by individual links, especially in a highly nonuniform traffic environment. To implement trunk grouping, we suggest not to designate the connection of each virtual circuit to individual links in high speed network protocol design.

A Broadband Packet Switch for Integrated Transport

This paper gives a broadband (total throughput approaching 1 terabit/s) self-routing packet switch design for providing flexible multiple bit-rate broadband services for an end-to-end fiber network. The switch fabric for the slotted broadband packet switch delivers exactly one packet to each output port from one of the input ports which request packet delivery to that output port. The denied requests would try again during the next slot. We discover an effective scheme, implemented by CMOS VLSI with manageable complexity, for performing this function. First, each input port sends a request for a port destination through a Batcher Sorting network, which sorts the request destinations in ascending order so that we may easily purge all but one request for the same destination. The winning request acknowledges its originating port from the output of the Batcher network, with the acknowledgment routed through a Batcher-banyan selfrouting switch. The acknowledged input port then sends the full packet through the same Batcher-banyan switch without any conflict. Unacknowledged ports buffer the blocked packet for reentry in the next cycle. We also give several variations for significantly improved performance. We then study switch performance based on some rudimentary protocols for traffic control. For the basic scheme, we analyze the throughput-delay characteristics for random traffic, modeled by random output port requests and a binomial distribution of packet arrival. We demonstrate with a buffer size of around 20 packets, we can achieve a 50 percent loading with almost no buffer overflow. Maximum throughput of switch is 58 percent. Next, we investigate the performance of the switch in the presence of periodic broadband traffic. We then apply circuit switching techniques and packet priority for high bit-rate services in our packet switch environment. We improve the throughput per port to close to 100 percent by means of parallel switch fabric, while maintaining the periodic nature of the traffic.

Design Examples of System Partitioning and Performance Allocation for VLSI Implementation

Generally, in the telecommunication industry, VLSI implementation is viewed as a means to cost reduction and is attempted only after successively decomposing a system into circuits corresponding to individual printed circuit boards (PCB's). This traditional "circuit-design" approach is unable to cope with and to exploit the potential of VLSI capabilities such as chip density and processing power. The availability of unprecedented processing power and the recognition of "effective endproduct cost" as the true measure for VLSI chip fabrication are leading the change over from integrated circuit design to integrated system design. In this paper, this emerging system design methodology for VLSI implementation and its two elements, system partitioning and performance specification allocation, are illustrated by two design examples; one relating to line-circuit design and the other to a packet-switch design.

Comparative Discussion of Circuit- vs. Packet-Switched Voice

Various other studies have already indicated potential advantage of packet-switching over tradiational circuit-switching concepts for voice communications. This paper explores the robustness of such comparisons for a range of network architectures. In particular, it is demonstrated that network sizing as related to the number of voice channels traversing a particular transmission link, and network topology with respect to the number of tandem links utilized in an end-to-end connection can have significant effects on the system performance. Estimates for end-to-end delay and the efficiency of trunk utilization are developed as a function of network topology to provide the insight necessary to identify network design limitations. A number of packet-switching design approaches, ranging from a pure datagram to a circuit-switching-like mode, are also discussed together with their effects on overall performance.