Packet Parser Research Articles

The Design of a Dynamic Configurable Packet Parser Based on FPGA.

To meet the evolving demands of programmable networks and address the limitations of traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency parser implemented on an FPGA. The architecture consists of three protocol analysis modules and a TCAM-SRAM. Latency is reduced by optimizing the state machine and parallel extraction matching. At the same time, we introduce the chain mapping idea and container concept to formulate the matching and extraction rules of table entries and enhance the extensibility of the parser. Furthermore, our system supports dynamic configuration through SDN control, allowing flexible adaptation to diverse scenarios. Our design has been verified and simulated with a cocotb-based framework. The resulting architecture is implemented on Xilinx Ultrascale+ FPGAs and supports a throughput of more than 80 Gbps, with a maximum latency of only 36 nanoseconds for L4 protocol parsing.

HP4 High-Performance Programmable Packet Parser

Now, header parsing is the main topic in the modern network systems to support many operations such as packet processing and security functions. The header parser design has a significant effect on the network devices' performances (latency, throughput, and resource utilization). However, the header parser design suffers from a lot number of difficulties, such as the incrementing in network throughput and a variety of protocols. Therefore, the programmable hardware packet parsing is the best solution to meet the dynamic reconfiguration and speed needs. Field Programmable Gate Array (FPGA) is an appropriate device for programmable high-speed packet implementation. This paper introduces a novel FPGA High-Performance Programmable Packet Parser architecture (HP4). HP4 automatically generated by the P4 (Programming protocol-independent Packet Processors) to optimize the speed, dynamic reconfiguration, and resource consumption. The HP4 shows a pipelined packet parser dynamic reconfiguration and low latency. In addition to high throughput (over 600 Gb/s), HP4 resource utilization is less than 7.5 percent of Virtex-7 870HT, and latency is about 88 ns. HP4 can use in a high-speed dynamic packet switch and network security.

An efficient packet parser architecture for software-defined 5G networks

Software-defined networks (SDN) has emerged with the capability to program in order to enhance flexibility, management, and testing of new ideas in the next generation of networks by removing current network limitations. Network virtualization and functionalization are critical elements supporting the delivery of future network services, especially in 5G networks. With the integration of virtualization and functionalization, network resources can be provisioned on-demand, and network service functions can be composed and chained dynamically to cater to various requirements. 5G networks are expected to rely heavily on SDN, which has been widely applied in core network design. To have a software-defined 5G network, not only is new spectrum and interface needed from SDN, but also a programmable and efficient hardware infrastructure is required. Admittedly, hardware components and infrastructure play an important role in supporting 5G networks. In other words, the software-defined 5G network data plane must have the required flexibility and programmability to support upcoming needs and technologies. Technological solutions need to respond to actual requests in infrastructure. Packet parsers in the data plane of software-defined 5G networks are one of the most important components because of the variation in the type of network headers and protocols. Each SDN switch needs to identify headers for processing input packets in the data plane, where the packet parser operates. Multiple implementations of packet parsers have been done on different substrates that occupy large hardware resources and areas on chip. However, they are not suitable for software-defined 5G networks. Certain architectures have been presented for packet parsing, aimed at accelerating the process of header parsing, however no attention has been paid toward reducing the area and the volume of the needed hardware resources and programmability in the data plane. This paper presents a new and efficient architecture for packet parsers on Field Programmable Gate Arrays (FPGA), called Efficient FPGA Packet Parser (EFPP) in a designed software-defined 5G network. This architecture emphasizes the removal of Ternary Content Addressable Memory (TCAM) to decrease hardware resources and efficiency in the data plane. Moreover, this architecture uses the chip’s processing speed and reconfiguration capabilities to support new protocols and network headers while maintaining flexibilities on software-defined 5G networks. EFPP is applied to chips on FPGA Xilinx ZedBoard Zynq, and the resources consumed around 7.5% LookUp Table, 1.9% Flip-Flops, and 5.8% of the memory. EFPP was also more area efficient. According to our results, EFPP would reduce the area and volume of hardware compared to other peer works.

HP4 High-Performance Programmable Packet Parser

Now, header parsing is the main topic in the modern network systems to support many operations such as packet processing and security functions. The header parser design has a significant effect on the network devices' performances (latency, throughput, and resource utilization). However, the header parser design suffers from a lot number of difficulties, such as the incrementing in network throughput and a variety of protocols. Therefore, the programmable hardware packet parsing is the best solution to meet the dynamic reconfiguration and speed needs. Field Programmable Gate Array (FPGA) is an appropriate device for programmable high-speed packet implementation. This paper introduces a novel FPGA High-Performance Programmable Packet Parser architecture (HP4). HP4 automatically generated by the P4 (Programming protocol-independent Packet Processors) to optimize the speed, dynamic reconfiguration, and resource consumption. The HP4 shows a pipelined packet parser dynamic reconfiguration and low latency. In addition to high throughput (over 600 Gb/s), HP4 resource utilization is less than 7.5 percent of Virtex-7 870HT, and latency is about 88 ns. HP4 can use in a high-speed dynamic packet switch and network security.

A kangaroo-based intrusion detection system on software-defined networks

In recent years, a new generation of architecture has emerged in the world of computer networks, known as software-defined networking (SDN), that aims to improve and remove the limitations of traditional networks. Although SDN provides viable benefits, it has faced many security threats and vulnerability-related issues. To solve security issues in the SDN, one of the most vital solutions is employing an intrusion detection system (IDS). Merging IDS into the SDN network remains efficient due to the unique features of SDN, such as high manageability, flexibility, and programmability. In this paper, we propose a new approach as a kangaroo-based intrusion detection system (KIDS), which is an SDN-based architecture for attack detection and malicious behaviors in the data plane. Designing a zone-based architecture in the KIDS assists us in achieving a distributed architecture which is scalable in both area and anomaly detection. In the KIDS architecture, the IDS module supplies the flow-based and packet-based intrusion detection components based on monitoring packet parser and Flow tables of the SDN switches. In the proposed approach, the IDS uses consecutive jumps like a kangaroo for announcing the attacks both to the SDN controller and other IDSs, contributing to improved scalability and efficiency. The evaluation of the proposed approach shows an enhanced performance against that of peer approaches in detecting malicious packets.

Performance realization of Bridge Model using Ethernet-MAC for NoC based system with FPGA Prototyping

The System on Chip (SoC) integrates the number of processing elements (PE) with different application requirements on a single chip. The SoC uses bus-based interconnection with shared memory access. However, buses are not scalable and limited to particular interface protocol. To overcome these problems, The Network on Chip (NoC) is an emerging interconnect solution with a scalable and reliable solution over SoC. The bridge model is essential to communicate the NoC based system on SoC. In this article, a cost-effective and efficient bridge model with ethernet-MAC is designed and also the placement of the bride with NoC based system is prototyped on Artix-7 FPGA. The Bridge model mainly contains FIFO modules, Serializer and de-serializer, priority-based arbiter with credit counter, packet framer and packet parser with Ethernet-MAC transceiver Module. The bridge with a single router and different sizes of the NoC based systems with mesh topology are designed using adaptive-XY routing. The performance metrics are evaluated for bridge with NoC in terms of average latency and maximum throughput for different Packet Injection Rate (PIR).

Performance realization of Bridge Model using Ethernet-MAC for NoC based system with FPGA Prototyping

The System on Chip (SoC) integrates the number of processing elements (PE) with different application requirements on a single chip. The SoC uses bus-based interconnection with shared memory access. However, buses are not scalable and limited to particular interface protocol. To overcome these problems, The Network on Chip (NoC) is an emerging interconnect solution with a scalable and reliable solution over SoC. The bridge model is essential to communicate the NoC based system on SoC. In this article, a cost-effective and efficient bridge model with ethernet-MAC is designed and also the placement of the bride with NoC based system is prototyped on Artix-7 FPGA. The Bridge model mainly contains FIFO modules, Serializer and de-serializer, priority-based arbiter with credit counter, packet framer and packet parser with Ethernet-MAC transceiver Module. The bridge with a single router and different sizes of the NoC based systems with mesh topology are designed using adaptive-XY routing. The performance metrics are evaluated for bridge with NoC in terms of average latency and maximum throughput for different Packet Injection Rate (PIR).

Flexible Software-Defined Packet Processing Using Low-Area Hardware

Computer networks are in the Software Defined Networking (SDN) and Network Function Virtualization (NFV) era. SDN brings a whole new set of flexibility and possibilities into the network. The data plane of forwarding devices can be programmed to provide functionality for any protocol, and to perform novel network testing, diagnostics, and troubleshooting. One of the most dominant hardware architectures for implementing the programmable data plane is the Reconfigurable Match Tables (RMT) architecture. RMT's innovative programmable architecture enables support of novel networking protocols. However, there are certain shortcomings associated with its architecture that limit its scalability and lead to an unnecessarily complex architecture. In this paper, we present the details of an alternative packet parser and Match-Action pipeline. The parser sustains tenfold throughput at an area increase of only 32 percent. The pipeline supports unlimited combination of tables at minimum possible cost and provides a new level of flexibility to programmable Match-Action packet processing by allowing custom depth for actions. In addition, it has more advanced field-referencing mechanisms. Despite these architectural enhancements, it has 31 percent less area compared to RMT architecture.

P4-to-blockchain: A secure blockchain-enabled packet parser for software defined networking

Security is one of the most challenging issues in software defined networking (SDN), and causes include the inability to detect the contents of the packets. In addition, file transferring to SDN is a potential attack vector that can be exploited at the network level. On the SDN data plane (i.e. the switch), packets are processed so that their behavior in the network can be determined. Packet parser (PP) acts as the main role of this operation on the switch. PP plays a very important role in identifying packets and supporting protocols and testing new ideas in SDN, which requires packet parsers on the data plane to provide the necessary flexibility and programmability. In recent times, cryptographic ledger technology (also referred to as Blockchain in the literature) has been applied to securely transfer transactions and files in the networks, mainly for crypto payments. In this paper, we propose a new packet parser architecture called Blockchain-enabled Packet Parser (BPP) based on the security characteristics of the blockchain and support for data processing functions with the description of Programming Protocol-Independent Packet Processors (P4) language that has the BPP-independent attribute of the protocol. In the proposed architecture, we provide a mathematical model based on a multivariate correlation approach for attack detection from the observed packet traffic. The implementation of BPP architecture is on Field Programmable Gate Array (FPGA), which is known for its higher processing speed, flexibility, and lower consumption resources. The result indicates that the proposed BPP is able to detect attacks and policy performed on the control plane in how to detect an attack from a packet structure efficiently. Furthermore, the impact of the bandwidth with and without the BPP in hardware environment is evaluated to demonstrate BPP's efficiency.