MEMS Packaging Research Articles

Multilayer Thin Film Getter for Sustainable Vacuum in MEMS Packaging

In this work, we investigate Au/Zr/V/Zr multilayer getters in order to get a sustainable low pressure in a packaging cavity. These films were analyzed by using four probe resistivity measurements, SEM and TEM cross section observations and Energy Dispersive X-Ray Spectrometry (EDX) measurements. It is demonstrated that the activation temperature of a zirconium layer covered with a vanadium layer depends on the vanadium layer thickness. Other experiments demonstrate that Au/Zr/V/Zr multilayer getter films can be activated at low temperature and that suitable sorption properties to get a low pressure in a medium size vacuum package during 9 months can be achieved after activation at 300°C for 1 hour.

High-Resolution E-Jet Enhanced MEMS Packaging

High-resolution electrohydrodynamic inkjet printing has potential to simplify the existing MEMS package fabrication through its additive and digital properties without sacrifices in the I/O density of the package. Initially, the replacement of certain lithographic process steps would lead to decreased material consumption and increased cost-effectiveness of the package fabrication; in long term, the large-scale adoption of additive process steps would enable increasing device customizability and lead to cost-effective fabrication of small batches and even fully tailored device specific MEMS packages. In our work, we have demonstrated the feasibility of this approach by replacing selected lithographic process steps by using high-resolution inkjet technology (Super Inkjet, SIJ Tech.) for metallization of high-density redistribution layers (RDL), metallization of through-silicon-vias (TSV) and fabrication of under bump metallization (UBM). Fully printed high-density redistribution layer (RDL) A fully printed high density RDL in two metallization layers was demonstrated with a combination of Super Inkjet (SIJ) and conventional inkjet printing (DMP-2831). The SIJ was used for the metallization of 5/5 µm W/S high-density circuitry in MET1 and MET2 and DMP for the dielectric layer separating the metallization layers. In order to achieve low resistance conductors with minimal footprint, multilayer printing was employed resulting in a high aspect ratio of over one. The MET1 to MET2 microvia was also additively fabricated by first printing a narrow ~10µm pillar in MET1 with SIJ, then surrounding the pillar with DMP printed dielectric layer and finally connecting the top of the pillar with SIJ printed MET2 conductors. [1] A fully printed RDL increases the customizability of the package fabrication process to a level where each individual interposer on wafer could be fitted with customized RDL to accommodate a specific MEMS device. In addition, the material consumption is reduced significantly since the fully printed RDL does away with global deposition of metal, masking and etching required in standard lithography based metallization. It is also important to notice that these advantages are achieved without sacrificing the density the RDL: the 5/5µm width and spacing for conductors and 10µm microvia diameter are similar to what is achieved with current lithographic processes. Additive metallization of high-density through-silicon-vias (TSV) The sub-femtoliter droplet size of the SIJ and concomitant fast evaporation rate was utilized in rapid metallization of high-density TSVs with top diameter of 23µm and spacing of 10µm. In standard practice CVD, PVD, electroplating or electroless deposition are utilized for metallization of high density TSVs leading to long process time and low level of customizability. The conventional inkjet printing could be used for over 50µm TSV diameters, but it is difficult to achieve stable operation with a 1pl cartridge which could produce small diameter droplets for filling the high density TSVs of 20µm diameter; also the low evaporation rate of the relatively large droplets would prolong the process time since evaporation step would need to be included in the process; in addition, the positioning accuracy of the conventional inkjet printer (e.g. DMP) might not be sufficient for this application. In this regard it was noticed that the SIJ printing has many advantages: first, the sub-femtoliter droplet size leads to fast evaporation rate enabling the metallization of the vias at room temperature without substrate heating or evaporation steps; second, the positioning accuracy of the SIJ stage is under 1µm enabling accurate deposition of the ink in to the TSV; third, since most of the solvent in the droplets is already evaporated during the flight, the chances for creating gas pockets in the filling are reduced. [2] High-resolution inkjet printing for creating smooth UBM The previously discussed approaches for utilizing the high-resolution Super Inkjet printing were restricted to features inside the interposer. However, this fabrication technology also finds utility on the outside of the package, which does not necessarily need such high-density features, but where low surface roughness is important. Highlighting this advantage, a smooth under bump metallization has been fabricated with SIJ on top of a large diameter partially metallized TSV; the TSV has been filled with SIJ printed polymer dielectric. [3] References Laurila et al, “Combination of E-jet and inkjet printing in additive fabrication of multilayer high-density RDL of silicon interposer”, IEEE Trans. Electr. Dev., vol. 64, no. 3, pp. 1217-1224, March 2017 Khorramdel et al, “Metallization of high-density TSVs using Super Inkjet technology”, 2015 IEEE 65th ECTC conf., San Diego, 2015, pp. 41-45 Khorramdel et al, “Inkjet printing technology for increasing the I/O density of 3D TSV interposers”, Microsystems & Nanoengineering, vol. 3, 17002, Apr. 2017

Characteristics of Li-ion micro batteries fully batch fabricated by micro-fluidic MEMS packaging

A cost-effective and reliable technology allowing extreme miniaturization of batteries into glass chips and electronic packages has been developed, employing a dispense-print process for battery electrodes and liquid electrolyte. Lithium-ion micro-batteries (active area 6 × 8 mm2, 0.15–0.3 mAh) with interdigitated electrodes were fabricated, tested and finally compared with the traditional battery architecture of stacked electrodes. Commercial graphite and lithium titanate anode as well as layered nickel cathode materials were used. All the processes for the micro-battery fabrication were established during this work; in particular the micro fluidic electrolyte filling process that allows simultaneous electrolyte supply to all cells on a planar substrate. Electrode mass reproducibility was sufficient for adequate electrode balancing. Current capability similar to the conventional face-to-face electrode configuration was achieved with interdigital electrodes that can be fabricated much easily on a substrate level. The cells were successfully cycled; several 100 cycles can be achieved. Additional results of life-time characteristics and electrochemical impedance spectroscopy are presented as well. These rechargeable micro-batteries can be used for future extremely miniaturized electronic products.

Multilayer Thin Film Getter for Sustainable Vacuum in MEMS Packaging

In this work, we investigate Au/Zr/V/Zr multilayer getters in order to get a sustainable low pressure in a packaging cavity. These films were analyzed by using four probe resistivity measurements, SEM and TEM cross section observations and Energy Dispersive X-Ray Spectrometry (EDX) measurements. It is demonstrated that the activation temperature of a zirconium layer covered with a vanadium layer depends on the vanadium layer thickness. Other experiments demonstrate that Au/Zr/V/Zr multilayer getter films can be activated at low temperature and that suitable sorption properties to get a low pressure in a medium size vacuum package during 9 months can be achieved after activation at 300°C for 1 hour.

Surface activated room-temperature bonding in Ar gas ambient for MEMS encapsulation

Surface activated room-temperature bonding of Si and sapphire wafers in high-purity inert gas ambient was examined. Although surface activated bonding has been mainly performed in high vacuum, Si and sapphire wafers were successfully bonded in Ar gas ambient up to 90 kPa, which is almost atmospheric pressure. The dicing test proved that the bonding prepared in Ar gas ambient was strong enough for MEMS packaging, although the bonding strength was slightly decreased compared with that prepared in vacuum. Transmission electron microscope observation revealed that the bonding interface prepared in Ar gas ambient is almost the same as that prepared in vacuum. It means that Ar atoms in the bonding ambient do not hamper the interatomic bond formation at the bonding interface. Room-temperature bonding in gas ambient enables hermetic packaging of MEMS devices, such as inertia sensors, MEMS switches, and Cs vapor cells for MEMS atomic clocks at various pressures.

Special issue on Design, Test, Integration and Packaging of MEMS and MOEMS, 2016

The 2016 edition of the symposium on Design, Test, Integration and Packaging of MEMS and MOEMS (DTIP), the premier MEMS scientific annual event in Europe, was held in Budapest, Hungary, May 30–June 2, 2016. DTIP’2016, organized by Prof. Marta Rencz and her team from Budapest University of Technology and Economics was the 18th edition and has been extremely appreciated by an hundred of attendees for the quality of both scientific and social programs. Oral and poster presentations were carefully selected by the Program Committee to insure a high scientific level. This symposium brought together participants interested in manufacturing of microstructures and/or in design tools and methods to facilitate the design of these microstructures. This special issue is composed of 24 extended versions of the best papers presented at the symposium. Extended papers have been refereed, along the usual refereeing process in force at Microsystem Technologies. Selected papers, out of 33 proposals, cover a broad range of topics including CAD tools, design methods, multi-physics modelling, thermal evaluation and optimization; test, reliability and failure analysis; sensors and actuators; advances in micro-fabrication, integration and packaging; new materials; advanced characterization techniques. We hope that you will enjoy these contributions as much as we did and if you want to join the DTIP community don’t hesitate to attend our next event or to visit our website.

Investigation on the effects of low-temperature anodic bonding and its reliability for MEMS packaging using destructive and non-destructive techniques

Excellence in the performance of MEMS-based devices such as RF switches, microfluidics, and pressure sensors are well known and by now reported. Operations of these devices are very sensitive to the environmental factors such as contamination, humidity, vibrations etc. Thus, the integration of these micro-devices with the real-life systems could be challenging without a hermetic sealing. A very common practice for these sealing is to bond a recessed cap onto a micromachined wafer using low-temperature wafer bonding mechanism known as anodic bonding or high-temperature sealing techniques such as fusion bonding for vacuum packages. Considering the limit of high-temperature bonding due to thin-film metals like nickel and gold present on the wafer and the induced bow associated with this high-temperature, this paper reveals a devising electrode designed that successfully bonded the samples at a reduced temperature well below at 250 °C. The reliability and effects of this low-temperature bonding between the silicon and Pyrex glass using destructive and non-destructive mechanisms have been investigated in this paper. The tensile strength measurements indicated a superior bonding strength of 14.12 MPa for the sample bonded at 250 °C. The induced bow height reduced from 30.3 µm (at 450 °C) to 0.3 µm (at 250 °C) meaning a significant reduction of bow up to 80.2%. Elemental composition was studied at the interface using energy dispersive X-ray spectroscopy (EDAX). To evaluate the bond quality, infra-red (IR) imaging was performed on the bonded sample pair. The interfaces were examined and analysed by scanning electron microscopy (SEM). Finally, we implemented this technique for a MEMS based pressure sensor application to prove the feasibility of low-temperature anodic bonding.

Technology Transfer for MEMS and Advanced Packaging: Precision Surface Preparation Innovatively Applied to Emerging Technologies

Abstract The purpose of this presentation is to examine how certain mainline silicon substrate and semiconductor wafer manufacturing processes, can be and are being applied to applications in the manufacture of some of the most advanced digital devices including advanced packaging applications. Periodically, the manufacturing steps and procedures of advanced semiconductor devices have changed dramatically enough that they are termed “paradigm shifts.” Two of the more dramatic manufacturing paradigm shifts in our professional lifetimes have been Precision Ultra-Thinning, and Chemical Mechanical Polishing to achieve planarization of substrates and specifically thin films that have been deposited on those substrates. In addition to the many activities in all or nearly all semiconductor IC manufacturing operations (Integrated Circuits), these two advanced technologies are now being applied to the manufacture of MEMS, MOEMS, LEDs, OLEDs, Nanotechnology and their associated Advanced Packaging methods and procedures. In our technology driven world, it is safe to say that hardly anything in the world of microelectronics, semiconductors, and nanotechnology has been invented only for its awe-inspiring beauty alone, with no intrinsic value toward the improvements in form factor (miniaturization), and functional operation (speed, capacity, reliability, etc.). The same can be said about these two interesting technologies.

Study on the failure temperature of Ti/Pt/Au and Pt5Si2–Ti/Pt/Au metallization systems**Project supported by the National Natural Science Foundation of China (No. 61376114).

The Ti/Pt/Au metallization system has an advantage of resisting KOH or TMAH solution etching. To form a good ohmic contact, the Ti/Pt/Au metallization system must be alloyed at 400 °C. However, the process temperatures of typical MEMS packaging technologies, such as anodic bonding, glass solder bonding and eutectic bonding, generally exceed 400 °C. It is puzzling if the Ti/Pt/Au system is destroyed during the subsequent packaging process. In the present work, the resistance of doped polysilicon resistors contacted by the Ti/Pt/Au metallization system that have undergone different temperatures and time are measured. The experimental results show that the ohmic contacts will be destroyed if heated to 500 °C. But if a 20 nm Pt film is sputtered on heavily doped polysilicon and alloyed at 700 °C before sputtering Ti/Pt/Au films, the Pt5Si2–Ti/Pt/Au metallization system has a higher service temperature of 500 °C, which exceeds process temperatures of most typical MEMS packaging technologies.

Special issue on Design, Test, Integration and Packaging of MEMS and MOEMS (DTIP 2015), held in Montpellier, France, April 27–30, 2015

The 2015 edition of the Symposium on Design, Test, Integration and Packaging of MEMS and MOEMS (DTIP) was held in Montpellier, France, 27–30 April 2015. Established in 1999 by our colleague Dr Bernard Courtois, DTIP is definitively the premier MEMS scientific event in Europe. DTIP’2015 was the 17th edition and has been extremely appreciated by an hundred of attendees for the quality of both scientific and social programs. Oral and poster presentations were carefully selected by the Program Committee to insure a high scientific level and awesome plenary speakers have been invited. This Symposium brought together participants interested in manufacturing of microstructures and participants interested in design tools to facilitate the design of these microstructures. This special issue is composed of 20 extended versions of the best papers presented at the Symposium. Extended papers have been refereed, along the usual refereeing process in force at Microsystem Technologies. Selected papers cover a broad range of topics including compact thermal modelling, thermal testing, electrostatic and thermal actuation, simulation, accelerometers, electronic front-end for sensors, magnetic nanoparticles and materials, RF MEMS, Quantum dots, piezoelectric films, Micro-transducers, magnetometers, microfluidic devices, resonant sensors, micro-fabrication, wafer bonding, Packaging, flexible interconnects and MEMS reliability. We hope that you will enjoy these contributions as much as we did and if you want to join the DTIP community do not hesitate to attend our next event or to visit our website.

High temperature MEMS packages: die-attach solutions for LiNbO3 under low bonding pressures

A survey of high temperature die-attach solutions for lithium niobate (LiNbO3) single crystals was conducted and based on that three promising approaches; i.e. eutectic solder, silver sinter-paste and silver-loaded conductive adhesive; were proposed and investigated. A relatively low pressure span (0–4 MPa) was employed, aiming to mitigate the risk of fracture in the brittle die. The mechanical properties of the corresponding die-attach assemblies was examined by a die-shear tester and the reliability of the joints was assessed after isothermal aging at 300 °C. The micro-structural integrity of the bonding was also analyzed by cross-sectional microscopy. The results revealed that silver sinter paste die-attach possesses superior shear strength in comparison to the two other techniques. Cross-sectional failure analysis also indicated a ductile fracture mode throughout the bonding layer for silver-paste and adhesive joints, whereas in soldered assemblies a brittle fracture mode along the interfacial intermetallic compound layer was predominant.

Alternative Metallurgies for MEMS Lid Seal

Abstract MEMS devices are a segment of the electronics industry enjoying explosive growth. With the advent of the internet of things (IoT), the trajectory for growth will continue to be steep and price pressures on both the devices and packaging will be intense. Current MEMS packaging schemes rely heavily on an architecture that employs a metal-can or laminate “lid” attached to the device package with a solder ring. This ring serves to connect the package elements together mechanically and to protect the device from noise (electronic or acoustic) and environmental damage. Like most modern electronic devices, MEMS devices are subject to the challenges imposed by the requirement for lead-free packaging. As with many devices, solder connections formed within the package have a similar composition, and therefore a similar reflow profile, to the solder used to attach the packaged components to a substrate. Devices that yield well at the manufacturer are thus susceptible to field failure at the assembly site induced by remelting of the solder within the package during assembly reflow. Unlike in SIP packages where the solder joints in the module are often encased in mold compound, the ring seal in MEMS devices is exposed and unreinforced resulting in failures such as lid shift, solder flow or flux contamination in the device cavity, and package deconstruction - particularly during rework. These type of post-fabrication yield losses can be very costly. Transient liquid phase (TLPS) sintering paste compositions are a new class of solder replacement materials that can be processed at typical reflow temperatures, but which do not remelt when subjected to subsequent thermal excursions. TLPS pastes combine solder alloy particles and reactive metal particles in proportions such that the solder ‘thermosets’ during a typical solder reflow cycle. This ‘thermosetting’ behavior results in a joint that does not remelt at the original reflow temperature, and thus enables the highly reliable electrical interconnect essential for assemblies that will undergo subsequent reflow excursions. TLPS pastes are similar to solders in many respects. The electrical, thermal and mechanical performance is similar to conventionally used tin-based solders. The TLPS pastes are stored and applied like solder pastes. The reflow cycles used to form the TLPS paste joints are also similar to those for forming solder joints. However, unlike solder, TLPS materials do not change shape during reflow or wet substrates beyond the deposition footprint. Also unlike solder, the metals within the bulk of the TLPS interconnect react with one another resulting in a stable interconnect with a thermally robust bonding structure to joining surfaces, even after subsequent thermal cycles. These attributes present both unique opportunities and unique challenges for addressing MEMS lid seal applications. This paper will explore the key material and engineering challenges for implementation of TLPS paste in MEMS lid seal applications.

Wafer-Level Hermetic Seal Bonding at Low-Temperature with Sub-Micron Gold Particle Using Stencil Printing

Low-temperature hermetic bonding using sub-micron gold (Au) particles has been developed for wafer level packaging of MEMS [1]. The new method of hermetic sealing uses a rim structure covered with sub-micron Au particles (0.3 μm in diameter), which is formed by Au paste (AuRoFUSETM) using a high-precision screen printer with stencil metal mask [2]. As shown in Fig.1 (a), after the alignment between the rim wafer and the metal mask, the printing was completed on the rim structure at a high speed of less than 10 seconds per wafer. The wafer-level printing has been demonstrated with 4 inch wafers in this study. After sintering the paste at 200°C in Fig. 1 (b), the coating thickness of the sub-micron Au particles on the rim top was in a range of 3-5 μm on the entire surface of 4 inch wafer. Then, wafer level thermo-compression bonding between the rim and a diaphragm wafer was performed in a wafer bonding chamber under a pressure of 10-3 Pa at 200°C for 30min with a bonding pressure range of 100-200 MPa. The Au particle pattern was pressed by the rim structure and the height of the pattern was reduced from 3-5 μm to 0.6 μm. The hermetic sealing was successfully realized by dense structure of the sub-micron Au particles as shown in Fig. 1 (c). The deformable property comes from the porous structure of sintered Au, which is advantage in terms of the compliance to surface irregularity as well as the insensitivity to surface roughness. A bonding shear strength measured by a die shear tester is 44 N for 4.3 mm-square rim in 10 μm width. The typical fracture was happened at the inside of the dense Au structure, showing a fractured surface of ductile deformation. After that, the bonded wafer was cut into individual laminates by using a conventional blade dicing.The hermeticity of sealed cavities was confirmed visually by deflection of the diaphragm. The size of diaphragm is 2.4 mm-square, and the concave deflection is -5 μm in atmospheric pressure. Measuring the displacement of the diaphragm precisely, the encapsulated pressure inside the cavity was estimated as 100 Pa. A helium (He) leak rate of sealed cavities was evaluated by an ultra-fine leak test. The detection limit of a usual fine leak test, which is about 1×10-1 2 Pa∙m3/s, is insufficient for the hermeticity measurement of wafer level MEMS packaging. On the other hand, the ultra-fine leak test system using a ‘Capsule-Accumulation Method’ can detect a leak rate down to 4×10-15 Pa∙m3/s (He). In the ‘Capsule-Accumulation Method’, a released He gas from the bonded wafer stack is accumulated during a time of 1,000 seconds in a small-volume capsule, and then introduced into a mass spectrometer. Prior to the measurement of He leak rate, the bonded wafer stacks were immersed in He gas atmosphere at a pressure of 0.617 MPa for 2h or 72h. The samples taken out of the He chamber were kept in air atmosphere before the measurement of He leak rate.Though a small amount of He was detected after the samples were loaded in a measurement chamber, this would indicate that the He initially adsorbed on the Si surface was released to be detected. The measurement showed that the maximum leak rate of the sealed cavity bonded with the sub-micron Au particles was estimated in a range of 10-14 Pa∙m3/s (He), which is sufficient for most of MEMS applications. REFERENCES Hiroyuki Ishida, Toshinori Ogashiwa, Yukio Kanehira, Hiroshi Murai, Takuya Yazaki, Shin Ito, Jun Mizuno, Surface Compliant Bonding Properties of Low-Temperature Wafer Bonding, IEEE ECTC 2013, pp. 1519-1523 T. Ogashiwa, K. Totsu, M. Nishizawa, H. Ishida, Y. Sasaki, M. Miyairi, H. Murai, Y. Kanehira, S. Tanaka, M. Esashi, "Hermetic Seal Bonding at Low-temperature with Sub-micron Gold Particles for Wafer Level Packaging", in Proc. of 48th International Symposium on Microelectronics (IMAPS), Orlando, Florida, USA, October 26-29, 2015, pp. 73-78. Fig.1 Schematic illustration of stencil printing (a), sub-micron Au particle pattern sintered at 200°C (b) and a dense structure after thermo-compression bonding (c). Figure 1

(Invited) Surface Activated Wafer Bonding; Principle and Current Status

The surface activated bonding (SAB) is a method which achieves strong bonding at room temperature. It is assumed that at the bonding interface prepared by SAB atoms bind to each other by the same interatomic bonds with those in bulk materials, such as covalent bond, metallic bond, etc. SAB well matches the wafer direct bonding, because intimate contact at the bonding interface is spontaneously achieved by the attractive force between very smooth wafer surfaces. In SAB, the surfaces of bonded materials are sputter-etched, in other word “cleaned”, before bonding. Various materials, such as semiconductor wafers, single crystal oxide wafers, metal films on wafers, etc. has been successfully bonded. Recently, other surface treatments have been proposed to apply SAB to wide variety of materials. SAB has been used to fabricate integrated substrates for RF-filters for more than 10 years, and has been already applied in MEMS packaging in industry. Other applications, such as power semiconductors, solar cells, etc. are now extensively developed.

Aluminum-Germanium Eutectic Bonding for MEMS: Behaviour and Solidification of Liquid Al-Ge on Different Substrates

In this paper we study the formation and behaviour of liquid Al-Ge alloy, its solidification, the resulting microstructures and the appearance of voids in bonded structure for MEMS packaging. The underneath layer influences the wettability of liquid Al-Ge as well as its solidification which can lead to undesirable Al dendrites. Each underneath layer imposes a critical value for the cooling rate above which dendrites are likely to appear. Blanket and patterned Al/Ge deposited wafers are bonded together with process parameters optimized thanks to previous results. The interfaces present a dendritic-free eutectic structure. Micro-voids are observed at the interfaces between Al and Ge phases. The Kirkendall effect and thermal stresses are two possible reasons for voiding phenomenon.

Study of a through-silicon/substrate via filling method based on the combinative effect of capillary action and liquid bridge rupture

Through-silicon via (TSV) is increasing its importance in advanced device packaging. In this paper, a through-silicon/substrate via filling method based on the combinative effect of liquid bridge rupture and capillary action is proposed and demonstrated. The proposed method is able to achieve alloy vias from the surface of a molten alloy pool. Two different processes were tested in experiments and the results show that one of these processes is able to achieve fully filled vias. In addition, a piece of equipment was specially made for the proposed via filling method. The via filling method studied in this paper has a potential application for TSVs in MEMS packaging.

A folded leg Ka-band RF MEMS shunt switch with amorphous silicon (a-Si) sacrificial layer

Design and fabrication of a folded leg Ka-band RF micro electro mechanical systems (RF MEMS) is presented. The mechanical design is carried out to observe minimum permanent deformation on the MEMS bridge after our in-house MEMS packaging process temperature treatment (200 °C). On the other hand, the actuation voltage is aimed as <30 V and measured as 24---25 V before thermal treatment. Moreover, the switch shows 28---29 V actuation voltage after thermal treatment. The fabricated switch shows ź0.4 dB insertion loss for the up state position at Ka-band, before and after heat treatment. The switch is fabricated on quartz wafer using an in-house surface micromachining process with a new amorphous silicon sacrificial layer structure.

2.5D / 3D IC Landscape: Market and Technology Trends

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&amp;D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain and continue to be investigated, the spotlight is turning to advanced packages. Emerging packages such as fan-out wafer level packages and 2.5D / 3D IC solutions together with upgraded flip chip BGAs aim to revive the cost/performance curve and extend both scaling and functionality roadmaps. Future packages need to tackle the explosion in information exchange translating to high number of I/Os and be able to support heterogeneous integration. This puts particular pressure on die to board interconnects. Technologies to fill the void created in diverging PCB versus IC feature sizes are constantly under development. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect, considered today the most advanced technology, is one emerging option that aims to enable heterogeneous integration. Such a technology is not limited to CMOS scaling in itself, it is rather based on bringing more functionality by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive components…) while reducing the package form factor. This functional diversification is also known as More-than-Moore. This work focuses on the analysis of recent developments and future trends of the 2.5D / 3D IC landscape. What's new since last year? TSV technology has already been utilized for several years within the MEMS and CMOS image sensor (CIS) market, but the news is that it finally seems to be happening within the logic and memory domain. Latest products such as AMD Radeon R9 Fury with its 2.5D configuration including HBM stacks and Samsung 3D TSV stacked DRAM, among others, aim for high volume. Fueled by consumer applications such as smartphones and tablets, the MEMS and CIS markets are expected to exhibit continuous growth over the next several years, while in the high-end market, driven by the need for further performance increase, volatile memory and especially DRAM are finally opening the doors of 2.5D / 3D IC commercial adoption. This analysis will cover 2.5D interposer &amp; 3DIC platforms as well as MEMS and CIS TSV packaging. Market forecasts in terms of wafer starts, market revenue, application segments and end-products will be presented. Furthermore, supply chain activities and major player interactions will be analyzed and 3D integration technology roadmaps will be reviewed. In conclusion, this study will aim at providing comprehensive insight into 2.5D / 3D IC market and technology trends.

Study on the Glass Silicon Anodic Direct Bonding Parameters

&lt;p&gt;By MEMS packaging test platform for bonding process of bonding temperature and bonding time, and test silicon specifications experimental study. Experimental results indicate that when the bonding voltage of 1200V, bonding temperature of 445&lt;sup&gt;0&lt;/sup&gt;C to 455&lt;sup&gt;0&lt;/sup&gt;C, bonding time is 60s,the void fraction is less than 5%.Glass and silicon wafer bonding quality can achieve the best. The experimental results in order to improve the glass silicon bonding quality provide the basis.&lt;/p&gt;

Extending WLCSP Packaging Technology Capabilities to Enable Miniaturized Sensor and MEMS Packaging Applications

WLCSP has been widely deployed in portable computing and communication devices for efficient die level packaging of integrated semiconductor and integrated passive applications. More recently with the proliferation of smart phone capabilities and applications as well as the emergence of Internet of Things and Wearable Electronics, MEMS and sensor devices in minimized package formats have become increasingly pervasive. These include image sensors, light sensors, finger print sensors as well as accelerometer, gyroscope and other MEMS motion sensing devices. It is predicted that the widespread adoption of WLCSP packaging for sensing applications will accelerate the proliferation of the incorporation of multiple sensor technologies within future communication devices. A number of these MEMS/Sensor applications have been able to leverage the existing WLCSP technology infrastructure and has led to opportunities to packaging and cost-effective standardization and miniaturization. On the other hand, some significant new changes to WLCSP process flows have also emerged that have had to be addressed. This paper will provide an overview of MEMS and Sensor applications that are currently or will use 2D, 2.5D or 3D wafer level packaging formats. Process enhancements including the ability to process thinner substrates with the adoption of temporary carrier technologies will also be highlighted.