Package-on-Package Technology Research Articles

Sn-3.0Ag-0.5Cu/Sn-58Bi composite solder joint assembled using a low-temperature reflow process for PoP technology

Package-on-Package (PoP) is a popular technology for fabricating chipsets of accelerated processing units. However, the coefficient of thermal expansion mismatch between Si chips and polymer substrates induces thermal warpage during the reflow process. As such, the reflow temperature and reliability of solder joints are critical aspects of PoP. Although Sn58Bi is a good candidate for low-temperature processes, its brittleness causes other reliability issues. In this study, an in-situ observation was performed on composite solders (CSs) made of an Sn-3.0Ag-0.5Cu (SAC305) solder and an Sn58Bi solder that were mixed during reflow at temperatures of 170 °C (CS-170), 180 °C (CS-180), and 190 °C (CS-190). The volumes of the mixed-solder regions were in the order of CS-190 > CS-180 > CS-170. A calculated Sn58Bi-SAC305 isoplethal section of the Sn-Ag-Cu-Bi quaternary system was employed to elucidate the melting behavior of CS-190. CS-190 with Sn cyclic twin boundary and Bi phase preferred orientation of [0001] was demonstrated by electron backscatter diffraction. Moreover, Cu/CS-190/Cu joints with a shear strength of 46 MPa were formed. CS-190 can reduce the brittleness of SnBi solder owing to the reduced solid-solution hardening with the decrease in the Bi content. These factors can improve the reliability of PoP technology.

Challenge to zero CTE and lower shrinkage organic substrate material for thin CSP package

Along with the advancement in miniaturizing of mobile devices, typified by smart phones and tablet PCs, the semiconductor PKG substrate installed in these devices is demanded to be thinner and higher in density. As one of the most innovative solutions, the PoP (package on package) technology, which has the three-dimensional construction, has been expanding rapidly in recent years. However, thinner PKG such as PoP tends to warp at the assembly process and cause the decrease in the connection reliability. Therefore ultra low CTE (coefficient of thermal expansion) core materials have been needed as a key solution for the reduction of the warpage for PoP. We have already developed and mass-produced ultra low CTE core material named E-770G (CTE value: 1.8 ppm/°C) for this application. However, the demand for lower warpage is still stronger especially for thinner PKG applications. To meet this requirement, we confirmed that not only low CTE but also lower resin shrinkage control gives big impact to warpage. In this paper, we would like to introduce new ultra low CTE and low shrinkage core material, named E-777G for next generation thin CSP. At the same time, we would like to explain the relationship between the warpage and material properties (CTE and resin shrinkage). E-777G has ultra low CTE and low shrinkage. These properties were achieved by applying our original resin system designed by hard segments and soft segments. Hard segments have a stack structure of aromatic ring and the strong intermolecular force between them, which lead to the ultra low CTE and low shrinkage. Soft segments of low elastic modulus can follow approximately the thermal behavior of glass fabric when heated and cooled. Consequently, the material can show the ultra low CTE which is similar to that of glass fabric itself. As a result, E-777G has achieved the ultra low CTE of 0.7 ppm/°C by TMA method which leads to significant reduction of the warpage. In the cooling process after the reflow, the bottom PKG of PoP shows a convex warpage. It is caused by resin shrinkage of substrate in the cooling process. As the method of decreasing resin shrinkage in the cooling process, we focused on decreasing free volume of the resin. By using molecular dynamics simulation, we designed the most suitable resin composition. Confirming the warpage property, we evaluated the warpage behavior of the bottom PKG before/after assembly process. The bottom PKG using E-777G material showed lower warpage than E-770G. We confirmed that not only the ultra low CTE but also low shrinkage of material effectively contributes to the decrease of the warpage.

Materials and soldering challenges in lead-free Package-on-Package (PoP) technology

Purpose– The purpose of this paper is to present challenges met during package-on-package (PoP) technology implementation in real surface-mount technology assembly processes.Design/methodology/approach– The properties and behavior of different combinations of soldering materials, PoP components and soldering profiles were investigated, both in the laboratory and during production trials. The purpose of such an approach was identification of existing problems and challenges in lead-free PoP systems assembly as well as checking which soldering material designed to PoP is more suitable for this technology.Findings– Technological trials are needed to select adequate soldering materials for PoP systems assembly, as laboratory tests of materials alone were not sufficient. The challenges of PoP technology were associated with the equipment utilized, the soldering materials, operational parameters and the soldering profile used for assembly. The localization of defects in PoP systems is very difficult and, in many cases, destructive methods have to be used on solder joints for the assessment and confirmation of failures.Originality/value– This paper shows main materials and soldering challenges in lead-free PoP technology. In particular, the problem related with selection of soldering materials and soldering profiles for PoP was presented. Moreover, the issues that have to be taken into consideration during the planning of a PoP system assembly procedure are presented.

PoP Technology for the Automotive Industry

Package-on-Package (PoP) technology has been in production for commercial and portable electronic applications for many years. The key challenge for PoP in automotive applications is meeting the aggressive defect level requirements. The need for PoP has historically been driven by mobile and tablet applications and an increased demand for more processor and memory performance within smaller spaces. With the maturity and excellent historical performance of PoP technology used with TI OMAPTM processor products, PoP can now be introduced as a reliable packaging technology in the automotive industry. This paper will describe the work involved in the enablement of commercial PoP technology into the automotive industry. The challenges and requirements regarding package design, warpage performance, surface mount (SMT) characterization, and board-level reliability (BLR) performance will all be explained.

Manufacturing Readiness of BVA(TM) Technology for Fine-Pitch Package-on-Package

Package-on-Package (PoP) has become common for packaging the processor and memory subunit in today's smartphones and tablets. Today's PoPs provide only about 300 interconnects between the base and top packages due to physical limitations posed by existing manufacturing methods. As a result, memory data bandwidth is limited to 25.6 GB/s at 1600 MHz DDR signal speeds. With a trend towards System-on-Chip (SoC) mobile processors with multi-core CPU, memory bandwidth requirements are sharply increasing. To meet these needs, a wide IO memory industry standard has emerged to specify 512 memory data interconnects. This standard provides about 4 times current bandwidths (>100 GB/s) even at lower 800 MHz DDR signal speeds. For memory devices to offer 512 data lines, a total of about 1000 interconnects are needed to include the accompanying address, control, power and ground signals required for operation. No current PoP technology can offer 1000 interconnects, due to limited fine-pitch capability within the standard 14mm x 14mm package outline. Although industry expectation is for Through-Silicon-Via (TSV) technology to eventually offer a high-bandwidth solution, TSV manufacturing is still being developed and not expected to be widely available for a number of years. A new high-performance PoP interconnect technology called Bond-Via-Array (BVA [TM]) has been developed to provide high-bandwidth interconnect capability today. A BVA test vehicle package demonstrating 1020 processor to memory interconnects at 0.24mm pitch has been assembled inside the industry-standard 14mm x 14mm package outline. These fine pitch vertical interconnects are achieved utilizing well established wirebond equipment and process. As a result, BVA provides a cost-effective and reliable path to high-performance PoP. This paper details equipment and process developments related to high-volume-manufacturing (HVM) readiness of BVA technology. In addition to assembly process and equipment, test hardware that can accommodate fine pitch wire-tip interconnects needs to be demonstrated for manufacturing readiness. Socket and test hardware development and verification studies utilizing the latest 0.24mm pitch test vehicle are underway in cooperation with a 3rd party test hardware supplier. Goals include demonstrating feasibility of the fine-pitch PoP test approach as well as establishing sources for such hardware. In summary, BVA PoP technology enables 1000+ interconnects in a standard PoP outline while taking advantage of existing materials and infrastructure. To ensure manufacturing readiness, package assembly and test demonstrations are being carried out with third party vendors. Results indicate that with proper design and process optimization, high yield assembly and test is possible, and this technology is ready for high volume manufacturing.

High Performance 3D Package for Wide IO Memory

3D processor-memory packages potentially offer very high performance due to short interconnects between the two chips. Current Package-on-Package (PoP) technology offers less than 300 interconnects between the processor and memory. To meet future bandwidth requirements of greater than 25.8 GB/s bandwidth at low power, wide IO memory in x512 configuration is expected. This memory requires more than 1,000 interconnects and current PoP technologies do not scale to meet these requirements. To address this problem, a new PoP technology called Bond Via Array (BVA) PoP is presented that offers very fine pitch (0.24 mm and lower) and high height/diameter aspect ratio (8:1 and higher). This is achieved by forming free-standing wire-bonds along the periphery of the processor chip and encapsulating the package leaving miniature posts projecting from the top of the package to be connected to the memory package. More than 1,000 interconnects can be formed within the same footprint as current packages. The BVA PoP process development, assembly and reliability test results are presented. The assembly and all reliability tests including Moisture Sensitivity Level (MSL) testing, on-board temperature cycling, high temperature storage, and drop tests were successfully completed. These results demonstrate that the BVA PoP is ready for high volume manufacturing.