P-type Polycrystalline Silicon Thin Film Research Articles

Degradation modeling with spatial mapping method in low temperature poly silicon thin film transistor aged off-state bias

We conducted experimental and quantitative studies on the effects of off-state bias stress of the p-type polycrystalline silicon thin film transistors, and present a degradation model using spatial mapping simulations. In the off-state bias stress condition, the gate induced drain leakage current (GIDL) is determined by the gate and drain voltage (Vgd), and the gate bias stress above a certain bias is accompanied by a change in Vth. The spatial distributions of the electric field and the electron concentration are considered as degradation factors, and are used in the equations for defect creation (DC) and the charge trapping (CT) model. We had to implement different forms of the aging model in the two regions: 1) CT in the poly-Si/SiOX interface, and 2) DC in the channel bulk. Finally, our degradation model allows us to analyze how the GIDL current decreases with various aging conditions, and provides a quantitative relationship between the amount of charge trapping and the amount of defect creation.

New Degradation Model of LTPs TFT Aged Off-State Bias Stress on Flexible Substrate

We conducted experimental and quantitative studies on the effects of off-state bias stress of the p-type polycrystalline silicon thin film transistors (TFTs) on flexible substrate and presented a new degradation model using TCAD simulation. In the off-state bias stress condition, the gate induced drain leakage (GIDL) current is determined by the gate and drain voltage (Vgd) and gate bias stress above a certain bias is accompanied by a change in Vth. To understand and model the underlying mechanism of these results, we developed a spatial probability analysis model with mapping of physical quantity (SPAM). The spatial distribution the E-field and the electron concentration are considered as degradation factors, and are used in the equations for defect creation (DC) and charge trapping (CT) TCAD model. We had to implement different forms of aging model in the two regions: 1) CT in poly-Si/SiOX interface, and 2) DC in the channel bulk (especially, the grain boundary). Finally, our new degradation model allows us to analyze how the GIDL current decreases with various aging conditions and provides a quantitative relationship between the amount of charge trapping and the amount of defect creationI. Fixed negative charge (-) of interface of poly-Si/SiOx(ε(x,y) > εC,f and n(x,y)> nC,f)Qfix (-) (x,y)=αf *[{ε(x,y)-εC,f}/εm,f ]γf_field *[log{n(x,y)/nC,f }]γfn II. Ionized defect density of channel bulk (Grain and GB)(ε(x,y,z) > εC,tA ) NtA (-) =gtA (ε)*exp[-{(EtA-EGA)/WGA}2 ]gtA (ε)= αtA*[{ε(x,y,z)-εC,tA}/εm,tAm ]γtA Figure 1

Gate-induced drain leakage current characteristics of p-type polycrystalline silicon thin film transistors aged by off-state stress

Thin film transistors have become crucial components of several electronic display devices. However, high leakage current is a frustrating impediment to increasing the efficiency of these transistors. We have performed an experimental and quantitative study on the effects of off-state bias stress on the characteristics of a p-type polycrystalline silicon (poly-Si) thin film transistor (TFT). The gate-induced drain leakage (GIDL) current under off-state bias stress conditions was investigated by changing gate-source voltage (Vgs) and drain-source voltage (Vds). Off-state bias stress was found to dramatically increase the threshold Vgs from 1 to 11 V, thereby increasing the voltage needed to turn off the TFT, without causing significant changes in on-state current or subthreshold swing. We developed local defect creation and charge trapping models for a technology computer-aided design simulation platform to understand the mechanisms underlying these observed effects. Using the model, we showed that off-state stress induces charge trapping within the local defects of a high electric field region in the TFT channel near the drain. This reduces the electric field and thermionic field-emission current, which in turn lowers the GIDL current by increasing threshold voltage Vgs.

Comparative study of mobility extraction methods in p-type polycrystalline silicon thin film transistors

Channel mobility in the p-type polycrystalline silicon thin film transistors (poly-Si TFTs) is extracted using Hoffman method, linear region transconductance method and multi-frequency C-V method. Due to the non-negligible errors when neglecting the dependence of gate-source voltage on the effective mobility, the extracted mobility results are overestimated using linear region transconductance method and Hoffman method, especially in the lower gate-source voltage region. By considering of the distribution of localized states in the band-gap, the frequency independent capacitance due to localized charges in the sub-gap states and due to channel free electron charges in the conduction band were extracted using multi-frequency C-V method. Therefore, channel mobility was extracted accurately based on the charge transport theory. In addition, the effect of electrical field dependent mobility degradation was also considered in the higher gate-source voltage region. In the end, the extracted mobility results in the poly-Si TFTs using these three methods are compared and analyzed.

Analysis of low frequency noise characteristics inp-type polycrystalline silicon thin film transistors

Low frequency noises in the p-type polycrystalline silicon thin film transistors are investigated. It shows a pure 1/f[Formula: see text] (with [Formula: see text] near one) noise behavior which can be explained by emission and trapping processes of carriers between trapping states. Subsequently, the gate voltage-dependent drain current noise power spectral densities closely follow the mobility fluctuation model, and the average Hooge’s parameter is then extracted. By considering traditional tunneling processes, the flat-band voltage spectral density is extracted and the concentration of traps in the grain boundary is calculated to be [Formula: see text]. By converting the frequency to tunneling depth of carriers in the gate oxide, the spatial distribution of gate oxide trapped charges are obtained. Finally, the distribution of localized states in the energy band is extracted. The experimental results show an exponential deep states and tail states distribution in the band gap while [Formula: see text] is about [Formula: see text], [Formula: see text] is [Formula: see text][Formula: see text]617 K, [Formula: see text] is [Formula: see text] and [Formula: see text] is [Formula: see text][Formula: see text]265 K.

Total Ionizing Dose Radiation Effects in the P-Type Polycrystalline Silicon Thin Film Transistors**Supported by the National Natural Science Foundation of China under Grant Nos 61574048 and 61204112, the Science and Technology Research Project of Guangdong Province under Grant Nos 2015B090912002 and 2014A030313656, and the Pearl River S&T Nova Program of Guangzhou.

The total ionizing dose radiation effects in the polycrystalline silicon thin film transistors are studied. Transfer characteristics, high-frequency capacitance-voltage curves and low-frequency noises (LFN) are measured before and after radiation. The experimental results show that threshold voltage and hole-field-effect mobility decrease, while sub-threshold swing and low-frequency noise increase with the increase of the total dose. The contributions of radiation induced interface states and oxide trapped charges to the shift of threshold voltage are also estimated. Furthermore, spatial distributions of oxide trapped charges before and after radiation are extracted based on the LFN measurements.

Bias-Temperature- and Light-Induced Instability in Short-Channel (L = 1.5 µm) p-Type Polycrystalline Silicon Thin-Film Transistors on Glass Substrates

We investigated the electrical al characteristics of laser-crystallized polycrystalline silicon thin-film transistors (poly-Si TFTs) under various stresses, such as bias, temperature, and light illumination. The threshold voltage of the short-channel TFTs (LCH = 1.5 µm) was significantly shifted in the negative direction owing to bias temperature stress (ΔVTH = -3.75 V) compared with that found in long-channel TFTs (ΔVTH = -0.32 V) at 100 °C. We also investigated the effects of light illumination on laser-crystallized poly-Si TFTs. In order to improve the reliability of laser-crystallized poly-Si TFTs, we developed a multiple-channel structure fabricated without using any additional processes.

Reliability in Short-Channel p-Type Polycrystalline Silicon Thin-Film Transistor under High Gate and Drain Bias Stress

We have investigated the electrical characteristics of short-channel p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under high gate and drain bias stress. We found that the threshold voltage of short-channel TFTs was significantly shifted in the negative direction owing to high gate and drain bias stress (ΔVTH = -2.08 V), whereas that of long-channel TFTs was rarely shifted in the negative direction (ΔVTH = -0.10 V). This negative shift of threshold voltage in the short-channel TFT may be attributed to interface state generation near the source junction and deep trap state creation near the drain junction between the poly-Si film and the gate insulator layer. It was also found that the gate-to-drain capacitance (CGD) characteristic of the stressed TFT severely stretched for the gate voltage below the flat band voltage VFB. The effects of high gate and drain bias stress are related to hot-hole-induced donor like interface state generation. The transfer characteristics of the forward and reverse modes after the high gate and drain bias stress also indicate that the interface state generation at the gate insulator/channel interface occurred near the source junction region.

Negative Bias Temperature Instability Dominated Degradation of Metal-Induced Laterally Crystallized p-Type Polycrystalline Silicon Thin-Film Transistors

Device degradation of solution-based metal-induced laterally crystallized p-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) is studied under dc bias stresses. While typical negative bias temperature instability (NBTI) or electron injection (EI) is observed under -Vg or -Vd only stress, respectively, no typical hot carrier (HC) degradation can be identified under high -Vd stress combined with either low or high -Vg stress. Instead, mixed NBTI and EI degradation is observed under combined low -Vg and -Vd stresses; and combined degradation of NBTI and HC occurs under high -Vd and moderate -Vg stresses. NBTI is the dominant mechanism in both cases. Grain boundary (GB) trap generation is found to correlate with the NBTI degradation with the same time exponent, suggesting the key role of GB trap generation in poly-Si TFTs' degradation.

Positive Shift of Threshold Voltage in Short-Channel (L = 1.5 µm) p-Type Polycrystalline Silicon Thin-Film Transistor under Off-State Bias Stress

A high-performance p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistor (TFT) was fabricated on a glass substrate. We have investigated the electrical characteristics of short-channel p-type ELA poly-Si TFTs under off-state bias stress. We have found that the threshold voltage of the short-channel TFT (L = 1.5 µm) significantly shifted in the positive direction under off-state bias stress (ΔVTH = 2.71 V), whereas the threshold voltage of long-channel TFT (L = 7 µm) barely moved in the positive direction (ΔVTH = 0.11 V). This positive shift of threshold voltage in the short-channel TFT may be attributed to electron trapping at an interface between the poly-Si film and the gate oxide layer. In addition, we have extracted the length of the drain extension from an equation of the pseudo-lightly doped drain (LDD) model to verify the existence of free hole charges induced near the drain junction. The transfer characteristics of the forward and reverse modes after the off-state bias stress indicate that the electron trapping at the gate insulator/channel interface occurred near the drain junction region. The leakage current of the ELA poly-Si TFT was also suppressed without reducing the on-current level under the off-state bias stress due to the creation of a pseudo-LDD region.

Comparison Study of Metal Induced Lateral Crystallized and Solid-Phase Crystallized Polycrystalline Silicon Thin Film Transistors with Different Channel Thickness

N- and P-type polycrystalline silicon thin film transistors are fabricated with channel thickness of 30 nm and 100 nm by metal induced lateral crystallization (MILC) and conventional solid-phase crystallization (SPC) of amorphous silicon. Significant improvement is obtained for the MILC devices by ultrathin channel layer. But for SPC devices, improvement is not as significant. The possible reasons are proposed and discussed.

Reliability of passivated p-type polycrystalline silicon thin film transistors

We have used NH3, N2O and N2 to passivate the traps in the grain boundaries of the p-type polycrystalline silicon thin film transistors (p-type poly-Si TFTs). Two different stress conditions, drain voltage Vd of-15V and -30V, have been applied to the poly-Si TFTs respectively while the gate voltage Vg were kept at -15V for both conditions and the stress time were 10 minutes at room temperature for all samples. The comparisons of I–V characteristics after stress with and without plasma passivations have been made, and the results indicated that the reliability will become worse for poly-Si TFTs after plasma passivations.