P-type Field-effect Transistors Research Articles

Monolithic 3D integration of back-end compatible 2D material FET on Si FinFET

The performance enhancement of integrated circuits relying on dimension scaling (i.e., following Moore’s Law) is more and more challenging owing to the physical limit of Si materials. Monolithic three-dimensional (M3D) integration has been considered as a powerful scheme to further boost up the system performance. Two-dimensional (2D) materials such as MoS2 are potential building blocks for constructing upper-tier transistors owing to their high mobility, atomic thickness, and back-end-of-line (BEOL) compatible processes. The concept to integrate 2D material-based devices with Si field-effect transistor (FET) is technologically important but the compatibility is yet to be experimentally demonstrated. Here, we successfully integrated an n-type monolayer MoS2 FET on a p-type Si fin-shaped FET with 20 nm fin width via an M3D integration technique to form a complementary inverter. The integration was enabled by deliberately adopting industrially matured techniques, such as chemical mechanical planarization and e-beam evaporation, to ensure its compatibility with the existing 3D integrated circuit process and the semiconductor industry in general. The 2D FET is fabricated using low-temperature sequential processes to avoid the degradation of lower-tier Si devices. The MoS2 n-FETs and Si p-FinFETs display symmetrical transfer characteristics and the resulting 3D complementary metal-oxide-semiconductor inverter show a voltage transfer characteristic with a maximum gain of ~38. This work clearly proves the integration compatibility of 2D materials with Si-based devices, encouraging the further development of monolithic 3D integrated circuits.

An integrate-and-fire neuron circuit made from printed organic field-effect transistors

Neuromorphic circuits that mimic the operation of nerve cells are promising approaches to interface with or emulate the operation of biological neural network. These types of electronic circuits have generally been realised by fabrication using well-established silicon technology but herein we report the fabrication of a simple neuromorphic circuit, specifically, an integrate-and-fire (I&F) circuit, using solution-processed OFETs. It consists of p-type organic field-effect transistors (OFETs) realised with parylene-dielectric, printed silver electrodes and a solution processed semiconductor on a flexible plastic substrate. As the behaviour of the fabricated I&F circuit is predictable by simulation, the reported process allows for customised circuit design and provides the basis to realise a variety of flexible neuromorphic circuit designs. • Neuromorphic circuits can mimic the electrical spiking of nerve cells. • A simple neuromorphic circuit made using printed organic field-effect transistors. • Performance of a printed integrate and fire circuit can be modelled by simulation.

Temperature rise effects on static characteristics of complementary FETs with Si and Ge nanosheets

We simulate the static behavior of Ge-p/Si-n nanosheet complementary FETs (CFETs), where p-type FETs containing Ge nanosheet channels are stacked on top of n-type FETs containing Si nanosheet channels, and we investigate its relation to temperature while comparing it with that of Si-p/Si-n nanosheet CFETs, whose p-type FETs contain Si nanosheet channels. It is found that temperature rise has similar effects on the static characteristics of the two CFETs operating as inverters, although the variations in threshold voltage and noise margin with rising temperature are slightly smaller in the Ge-p/Si-n CFET inverter than in the Si-p/Si-n CFET inverter. The temperature rise effects are fully explained by the temperature dependence of material and carrier properties of Ge and Si.

Modulated wafer-scale WS2 films based on atomic-layer-deposition for various device applications.

Tungsten disulfide (WS2) is promising for potential applications in transistors and gas sensors due to its high mobility and high adsorption of gas molecules onto edge sites. This work comprehensively studied the deposition temperature, growth mechanism, annealing conditions, and Nb doping of WS2 to prepare high-quality wafer-scale N- and P-type WS2 films by atomic layer deposition (ALD). It shows that the deposition and annealing temperature greatly influence the electronic properties and crystallinity of WS2, and insufficient annealing will seriously reduce the switch ratio and on-state current of the field effect transistors (FETs). Besides, the morphologies and carrier types of WS2 films can be controlled by adjusting the processes of ALD. The obtained WS2 films and the films with vertical structures were used to fabricate FETs and gas sensors, respectively. Among them, the Ion/Ioff ratio of N- and P-type WS2 FETs is 105 and 102, respectively, and the response of N- and P-type gas sensors is 14% and 42% under 50 ppm NH3 at room temperature, respectively. We have successfully demonstrated a controllable ALD process to modify the morphology and doping behavior of WS2 films with various device functionalities based on acquisitive characteristics.

Doping-Free Complementary Metal-Oxide-Semiconductor Inverter Based on N-Type and P-Type Tungsten Diselenide Field-Effect Transistors With Aluminum-Scandium Alloy and Tungsten Oxide for Source/Drain Contact

In this study, we experimentally demonstrated concepts for realizing doping-free Tungsten Diselenide (WSe2) complementary metal-oxide-semiconductor (CMOS) inverter by developing alloys and compound metals used as source/drain (S/D) contacts. Aluminum – scandium alloy (AlSc) and tungsten oxide (WOx)-based S/D contacts enable efficient electron and hole injection into WSe2 for n-type and p-type FET operation because the work function (WF) of AlSc and WOx are aligned to neighboring the conduction and valence band edge of WSe2, respectively. A dual-gate bias architecture is used to improve electrical characteristics of FETs and enhance CMOS inverter performance after device fabrication. By utilizing AlSc and WOx-based S/D contacts in conjunction with the dual-gate bias architecture, our fabricated WSe2 CMOS inverter realized a higher gain at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ dd}}$ </tex-math></inline-formula> of 1 V or higher than those in the literatures. Furthermore, the fabricated WSe2 CMOS inverter is operated at a power supply voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ dd}}$ </tex-math></inline-formula> ) of as low as 0.5 V. This study paves the way towards research and development of transition metal dichalcogenides-based devices and circuits.

Complementary Transistors Based on Aligned Semiconducting Carbon Nanotube Arrays.

High-density semiconducting aligned carbon nanotube (A-CNT) arrays have been demonstrated with wafer-scale preparation of materials and have shown high performance in P-type field-effect transistors (FETs) and great potential for applications in future digital integrated circuits (ICs). However, high-performance N-type FETs (N-FETs) have not yet been implemented with A-CNTs, making development of complementary metal-oxide-semiconductor (CMOS) technology, a necessary component for modern digital ICs, impossible. In this work, we reveal the mechanism hindering the realization of A-CNT N-FETs contacted by low-work-function metals and develop corresponding solutions to promote the performance of N-FETs to that of P-type FETs (P-FETs). The fabricated scandium (Sc)-contacted A-CNT N-FET with a 100 nm gate length exhibits an on-state current (Ion) of 800 μA/μm and a peak transconductance (gm) of 250 μS/μm, representing the highest performance of CNT-based N-FETs to date. Moreover, CMOS technology has been developed to realize N- and P-FETs with symmetric high performance based on A-CNTs. The fabricated A-CNT CMOS FETs show electron and hole mobilities of 325 and 241 cm2 V-1 s-1, respectively, which are slightly higher than the corresponding values of Si CMOS transistors. Our scalable fabrication of A-CNT CMOS FETs with comparable electronic performance to Si CMOS will promote the application of CNT-based electronics in digital ICs.

Novel Channel-First Fishbone FETs With Symmetrical Threshold Voltages and Balanced Driving Currents Using Single Work Function Metal Process

In this article, one feasible fabrication approach for novel fishbone FETs using the channel-first and single work function metal (sWFM) processes is proposed and investigated by 3-D technical computer-aided design (TCAD) simulations. Through a small modification on the fabrication process of general gate-all-around (GAA) nanosheet FETs (NSFETs), the special fishbone-like channel composed of vertically stacked Si NSs and sandwiched SiGe nano-fins is experimentally demonstrated by the channel-first process. The simulated electrical characteristics show that the width of the nano-fins should be within 5 nm for a better gate control. Unlike traditional NSFETs, symmetrical threshold voltages ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}\text{s}$ </tex-math></inline-formula> ) for n-type and p-type fishbone FETs can be achieved by using a sWFM, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {V}_{\text {th}}$ </tex-math></inline-formula> is optimized by 99.26% compared with that of NSFETs. Meanwhile, it is also found that the SiGe nano-fins contribute more driving current for p-type devices. Therefore, the proposed fishbone FETs with sWFM not only exhibit significantly enhanced driving current but also provide good balance between the performances of n-type and p-type fishbone FETs with a little extra process cost.

Impact of the Figures of Merit (FoMs) Definitions on the Variability in Nanowire TFET: NEGF Simulation Study

In this article, we investigate the effect of variability in p-type nanowire tunnel FET (TFET) using quantum mechanical transport simulations. The simulations have been carried out using the Nano Electronics Simulation Software (NESS) from the University of Glasgow. Random discrete dopants (RDDs) and work-function variations (WFV) have been investigated in the simulations. Our statistical simulations reveal that key figures of merit (FoMs) such as the current variability generally decrease as the gate voltage decreases, the threshold voltage variability increases as the threshold current increases, and the dependences of these FoM variabilities on criteria become stronger with the switch characteristic ameliorated. Furthermore, it is interesting to find that the band offset in heterostructure can more or less alleviate the current variability, especially around the OFF-state.

Investigation of p-type High Temperature Field Effect Transistor for CMOS Logic Application

In this study, we propose a silicon-based metal oxide semiconductor field effect transistor (MOSFET) device for p-type that can operate at a high temperature (at 573 K). This device can be applied to logic circuits, and furthermore, used in semiconductor chips operating in high temperature environments. Through research, we selected 3C-SiC, which can prevent off-current most effectively, as a material to be applied to the device. After that, technology computer aided design (TCAD) simulation will be used to apply the interface characteristics according to the physical properties of silicon and 3CSiC, and to optimize the current characteristics of device as a logic element. In addition, we investigated a complementary metal oxide semiconductor (CMOS) logic circuit with simulation program with integrated circuit emphasis (SPICE) and verify the inverting characteristics in a high temperature environment of 573 K by applying the device of this study.

(Invited, Digital Presentation) Low Voltage Operation of CMOS Inverter Based on WSe2 n/p FETs

Transition metal dichalcogenides (TMDC) have remarkable properties for the next generation of electronic devices [1]. A complementary metal-oxide-semiconductor (CMOS) inverter consisting of pairs of p-type and n-type field-effect transistor (FET) is a fundamental building block in modern digital electronics [2]. Therefore, realization of both p-type and n-type FETs based on semiconducting TMDC is of particular importance. Among various semiconducting TMDC, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [3]. These prominent features of WSe2 motivates the fabrication and characterization of a CMOS inverter. One of the significant challenges is to develop a high-gain CMOS inverter for operation at a low power supply voltage (Vdd) for future low power digital electronics. Previous studies on a WSe2 CMOS inverter were limited to operation with a low gain of 3 or a high Vdd of more than 1 V under conditions of relatively low gate capacitance and degraded interfacial properties [3-5]. This study addressed these issues by developing a doping technique and gate stack technology to demonstrate the high-gain with low-Vdd operation of a WSe2 CMOS inverter [6]. The focus is on the doping technique of both electrons and holes to a WSe2 layer by simple spin-coating. Of particular interest in this study is the impact of gate stack technology on the CMOS inverter characteristics in low-Vdd operation. In this study, a hybrid self-assembled monolayer (SAM)/aluminum oxide (AlOx) gate dielectric is applied to a WSe2 CMOS inverter for high-gain low-Vdd operation since superior interfacial properties with high gate capacitance have been reported in molybdenum disulfide (MoS2) FETs.For p-type WSe2 FETs, the fluoropolymer CYTOP (AGC, CTX-809A) was applied since polarization in CYTOP due to the difference in electronegativity between C–F bonds generates holes in WSe2. On the other hand, poly(vinyl alcohol) (PVA) was utilized for n-type WSe2 FETs because positive charges in PVA accumulates electrons in WSe2. The resin solutions of both CYTOP and PVA were purchased from a commercial supplier. A heavily doped p-type silicon substrate (p+-Si) was thermally oxidized to form a 60 nm thick silicon dioxide (SiO2) layer for the global back-gate architecture. Palladium (Pd) and gold (Au) as the source and drain contacts for p-type and n-type WSe2 FETs were fabricated by the lift-off process, respectively. An aluminum (Al) gate was prepared and a hybrid SAM/AlOx gate dielectric was formed by oxygen (O2) plasma and an immersion process. After that, mechanically exfoliated WSe2 was transferred with a poly(dimethylsiloxane) (PDMS) stamp. Finally, CYTOP and PVA were deposited by spin-coating for p-type and n-type WSe2 FETs, respectively.Figures 1 (a) and (b) show the Id–Vg characteristics of fabricated FETs. For the p-type WSe2 FET, a small SS of 78 mV/dec and an on/off ratio of about 106 order were observed. On the other hand, the Id–Vg characteristics of the n-type WSe2 FET were degraded compared with those of the p-type WSe2 FET because of the Schottky contacts.Figures 2 (a) and (b) show the transfer characteristics and gain as a function of Vdd in CMOS inverter. The gain of the CMOS inverter increased to as high as 9 at Vdd of 0.5 V.Figure 3 shows the benchmark of this study. Our proposed concepts enabled the operation with high gain at a low Vdd as low as 0.5 V for the WSe2 CMOS inverter, which had not been realized in previous studies. The dangling-bond-free and ultrathin SAM/AlOx gate dielectric has an important role in the low-Vdd operation of the WSe2 CMOS inverter. This study opens up interesting directions for the research and development of TMDC-based devices and circuits.

Vapor-Liquid-Solid Growth of Morphology-Tailorable WS2 toward P-Type Monolayer Field-Effect Transistors.

Although substantial efforts have been made, controllable synthesis of p-type WS2 remains a challenge. In this work, we employ NaCl as a seeding promoter to realize vapor-liquid-solid (VLS) growth of p-type WS2. Morphological evolution, including a one-dimensional (1D) nanowire to two-dimensional (2D) planar domain and 2D shape transition of WS2 domains, can be well-controlled by the growth temperature and sulfur introduction time. A high growth temperature is required to enable planar growth of 2D WS2, and a sulfur-rich environment is found to facilitate the growth of high-quality WS2. Raman and photoluminescence (PL) mappings demonstrate uniform crystallinity and high quantum efficiency of VLS-grown WS2. Moreover, monolayer WS2-based field-effect transistors (FETs) are fabricated, showing p-type conducting behavior, which is different from previous reported n-type FETs from WS2 grown by other methods. First-principles calculations show that the p-type behavior originates from the substitution of Na at the W site, which will form an additional acceptor level above the valence band maximum (VBM). This facile VLS growth method opens the avenue to realize the p-n WS2 homojunctions and p/n-WS2-based heterojunctions for monolayer wearable electronic, photonic, optoelectronic, and biosensing devices and should also be a great benefit to the development of 2D complementary metal-oxide-semiconductor (CMOS) circuit applications.

Hydrophenazine-linked two-dimensional ladder-type crystalline fused aromatic network with high charge transport

•A ladder-type hydrophenazine-linked 2D fused aromatic network (HP-FAN) was realized •The HP-FAN has an inherent semiconducting band gap along with a parallel flat band •The HP-FAN has high intrinsic electrical conductivity without doping •The HP-FAN exhibits a remarkable performance in electronic devices with high mobility Since the advent of graphene, the development of crystalline two-dimensional (2D) organic materials with semiconducting features has been extensively explored for their potential optoelectronic applications. Despite extensive progress in this field, it is still challenging to realize laterally extended organic materials with high electrical transport properties. Here, we report a 2D ladder-type fused aromatic network (FAN) in which backbones are composed of hydrophenazine (HP) linkage (designated HP-FAN). Consequently, its 2D extended delocalization of π-molecular orbitals imparts a semiconducting band gap and facilitates fast intra-chain charge transport. The as-prepared HP-FAN exhibits semiconducting features with calculated and experimental band gaps of approximately 1.44 and 1.54 eV, respectively, with an unusual flat band. The HP-FAN thin flakes, isolated by polydimethylsiloxane stamping, exhibit remarkable performance in a p-type field-effect transistor (FET) and a Hall effect device. Given its laterally extended ladder-type π-conjugated structure, the HP-FAN has extensive potential for applications in thin-film optoelectronic devices. Since the advent of graphene, the development of crystalline two-dimensional (2D) organic materials with semiconducting features has been extensively explored for their potential optoelectronic applications. Despite extensive progress in this field, it is still challenging to realize laterally extended organic materials with high electrical transport properties. Here, we report a 2D ladder-type fused aromatic network (FAN) in which backbones are composed of hydrophenazine (HP) linkage (designated HP-FAN). Consequently, its 2D extended delocalization of π-molecular orbitals imparts a semiconducting band gap and facilitates fast intra-chain charge transport. The as-prepared HP-FAN exhibits semiconducting features with calculated and experimental band gaps of approximately 1.44 and 1.54 eV, respectively, with an unusual flat band. The HP-FAN thin flakes, isolated by polydimethylsiloxane stamping, exhibit remarkable performance in a p-type field-effect transistor (FET) and a Hall effect device. Given its laterally extended ladder-type π-conjugated structure, the HP-FAN has extensive potential for applications in thin-film optoelectronic devices.

P-type electrical contacts for 2D transition-metal dichalcogenides.

Digital logic circuits are based on complementary pairs of n- and p-type field effect transistors (FETs) via complementary metal oxide semiconductor technology. In three-dimensional (3D) or bulk semiconductors, substitutional doping of acceptor or donor impurities is used to achieve p- and n-type FETs. However, the controllable p-type doping of low-dimensional semiconductors such as two-dimensional (2D) transition-metal dichalcogenides (TMDs) has proved to be challenging. Although it is possible to achieve high-quality, low-resistance n-type van der Waals (vdW) contacts on 2D TMDs1-5, obtaining p-type devices by evaporating high-work-function metals onto 2D TMDs has not been realized so far. Here we report high-performance p-type devices on single- and few-layered molybdenum disulfide and tungsten diselenide based on industry-compatible electron beam evaporation of high-work-function metals such as palladium and platinum. Using atomic resolution imaging and spectroscopy, we demonstrate near-ideal vdW interfaces without chemical interactions between the 2D TMDs and 3D metals. Electronic transport measurements reveal that the Fermi level is unpinned and p-type FETs based on vdW contacts exhibit low contact resistance of 3.3 kΩ µm, high mobility values of approximately 190 cm2 V-1 s-1 at room temperature, saturation currents in excess of 10-5 A μm-1 and an on/off ratio of 107. We also demonstrate an ultra-thin photovoltaic cell based on n- and p-type vdW contacts with an open circuit voltage of 0.6 V and a power conversion efficiency of 0.82%.

Heterogeneous Integration of Atomically Thin Semiconductors for Non-von Neumann CMOS.

Atomically thin, 2D, and semiconducting transition metal dichalcogenides (TMDs) are seen as potential candidates for complementary metal oxide semiconductor (CMOS) technology in future nodes. While high-performance field effect transistors (FETs), logic gates, and integrated circuits (ICs) made from n-type TMDs such as MoS2 and WS2 grown at wafer scale have been demonstrated, realizing CMOS electronics necessitates integration of large area p-type semiconductors. Furthermore, the physical separation of memory and logic is a bottleneck of the existing CMOS technology and must be overcome to reduce the energy burden for computation. In this article, the existing limitations are overcome and for the first time, a heterogeneous integration of large area grown n-type MoS2 and p-type vanadium doped WSe2 FETs with non-volatile and analog memory storage capabilities to achieve a non-von Neumann 2D CMOS platform is introduced. This manufacturing process flow allows for precise positioning of n-type and p-type FETs, which is critical for any IC development. Inverters and a simplified 2-input-1-output multiplexers and neuromorphic computing primitives such as Gaussian, sigmoid, and tanh activation functions using this non-von Neumann 2D CMOS platform are also demonstrated. This demonstration shows the feasibility of heterogeneous integration of wafer scale 2D materials.

FUNDAMENTAL LIMITS FOR THE LENGTH OF CONDUCTION CHANNEL IN THE FET ON TRANSITION METALS DICHALCOGENIDE SINGLE LAYER BASE

The modeling of the limits of functionality for the FET with conduction channel on transition metals dichalcogenide single layer base and with different source/drain contacts material was performed in this article. The quantum mechanical transparency of the channel barrier was calculated with allowance for the realistic form of the barrier potential. It is demonstrated, that the FET with 4-nm channel of n-MoS2 and MoS2 (metallic modification) source/drain contacts retains high level of functionality for the range of comparatively low gate and drain voltages (the barrier transparency is lower than ½). The similar FET with Pt source/drain contacts, when Schottky barrier is essentially higher and the barrier transparency is essentially lower, keep it’s functionality for the 2 nm channel as well for all the realistic values of gate and drain voltages. The similar result was obtained for the FET with p-WSe2 channel and Pd contacts as well. The obtained estimations confirm the possibility of the complementary inverter on MoS2 n-type FET and WSe2 p-type FET with ultra-short channels in 2–4 nm range.

Epitaxy of NiTe2 on WS2 for the p-Type Schottky Contact and Increased Photoresponse.

Two-dimensional (2D) transition metal dichalcogenides (TMDCs) have great potential applications in the electronic and optoelectronic devices. Nevertheless, due to the difficulty in the efficient doping of atomic-thickness TMDCs or Fermi level pinning (FLP) effects at the metal/semiconductor interface, most TMDC devices exhibit the n-type conduction polarity, which significantly limits their functional applications based on the p-n junction. Here, 2D semi-metal NiTe2 nanosheets were epitaxially grown on the WS2 monolayer by a two-step chemical vapor deposition route. The microstructure and optical characterizations confirm that the vertically stacked NiTe2/WS2 heterostructures are formed by van der Waals epitaxy. Interestingly, p-type WS2 field-effect transistors can be obtained with the hole mobility of ∼4.22 cm2/V·s, when the epitaxial NiTe2 sheets act as the source/drain electrodes. This is attributed to the decreased FLP effect and hence the low potential barrier for holes at the van der Waals contacts. Furthermore, the photodetectors based on the heterostructures show a 2 orders of magnitude increase in the switch ratio, responsivity, and detectivity and a 1 order of magnitude increase in the rise and decay speeds relative to those based on pristine WS2. This work paves the way to realize the p-type contact for monolayer WS2 with significantly enhanced optoelectronic performance.

Graphene Via Contact Architecture for Vertical Integration of vdW Heterostructure Devices.

Two-dimensional (2D) devices and their van der Waals (vdW) heterostructures attract considerable attention owing to their potential for next-generation logic and memory applications. In addition, 2D devices are projected to have high integration capabilities, while maintaining nanoscale thickness. However, the fabrication of 2D devices and their circuits is challenging because of the high precision required to etch and pattern ultrathin 2D materials for integration. Here, the fabrication of a graphene via contact architecture to electrically connect graphene electrodes (or leads) embedded in vdW heterostructures is demonstrated. Graphene via contacts comprising of edge and fluorinated graphene (FG) electrodes are fabricated by successive fluorination and plasma etching processes. A one-step fabrication process that utilizes the graphene contacts is developed for a vertically integrated complementary inverter based on n- and p-type 2D field-effect transistors (FETs). This study provides a promising method to fabricate vertically integrated 2D devices, which are essential in 2D material-based devices and circuits.

Superior mm-Wave Large Signal Power Amplifier Reliability of p-Type FET in a 45-nm Partially-Depleted Silicon-On-Insulator RF Technology

In this letter, we have explored the DC, small and large-signal RF reliability of the Power Amplifier (PA) cell for mm-wave applications under DC and RF stress. The PA cell comprises of a single transistor that employs 45RFSOI technology. For the first time here, a PA cell consisting of p-channel partially depleted Silicon-On-Insulator (PD-SOI) FET has been investigated for large-signal reliability behavior. At the same stress conditions, the impact of hot carrier degradation (HCD) on a p-channel FET (PFET) PA cell is also compared with the n-channel FET (NFET) PA cell. As the reliability of the PFET PA cell is superior than NFETs, a deeper investigation of hot carrier degradation and its impact on PA cell reliability is carried out. The PA cell is subjected to extensive RF characterization for varying DC stress and RF power at the gate terminal. The behavior of the time slope exponent of the PFET PA cell is studied to understand the nature of defects. Accelerated aging experiments using DC bias at drain/gate terminals and RF power at the gate terminal is performed. These results show that the RF reliability of the PFET PA cell is superior than its counterpart NFET PA cell at mm-wave frequencies.

Performance Enhancement of SnS/h-BN Heterostructure p-Type FET via the Thermodynamically Predicted Surface Oxide Conversion Method.

Searching for the counterpart of well-developed two-dimensional (2D) n-type field effect transistors (FETs) is indispensable for complementary logic circuit applications for 2D devices. Although SnS is regarded as a potential candidate for high-performance p-type FETs, recent experiments only show poor results deviating from the theoretically predicted high mobility. In this research, the serious performance degradation due to the surface oxidation of SnS, which commonly occurs in most 2D materials, is addressed through surface oxide conversion using highly reactive Ti. In this conversion process, which is confirmed by systematic characterization, the reduction of SnS surface oxide is accompanied by the formation of functional titanium oxide, which works as both a conductive intermediate layer to improve the contact property and a buffer layer of the high-k top gate insulator at the channel region. Consequently, a record-high field effect mobility of 87.4 cm2 V-1 s-1 in SnS p-type FETs is achieved. The surface oxide conversion method applied here is consistent with our previous thermodynamic prediction, and this novel technique can be widely introduced to all 2D materials that are vulnerable to oxidation and facilitate the future development of 2D devices.

Wafer-Scale Demonstration of MBC-FET and C-FET Arrays Based on Two-Dimensional Semiconductors.

Two-dimentional semiconductors have shown potential applications in multi-bridge channel field-effect transistors (MBC-FETs) and complementary field-effect transistors (C-FETs) due to their atomic thickness, stackability, and excellent electrical properties. However, the exploration of MBC-FET and C-FET based on large-scale 2D semiconductors is still lacking. Here, based on a reliable vertical stacking of wafer-scale 2D semiconductors, large-scale MBC-FETs and C-FETs using n-type MoS2 and p-type MoTe2 are successfully fabricated. The drive current of an MBC-FET with two layers of MoS2 channel (20µm/10µm) is up to 60µA under 1V bias. Compared with the single-gate MoS2 FET, the carrier mobility of MBC-FET is 2.3 times higher and the sub-threshold swing is 70% smaller. Furthermore, NAND and NOR logic circuits are also constructed based on two vertically stacked MoS2 channels. Then, C-FET arrays are fabricated by 3D integrating n-type MoS2 FET and p-type MoTe2 FET, which exhibit a voltage gain of 7V/V when VDD = 4V. In addition, this C-FET device can directly convert light signals to an electrical digital signal within a single device. The demonstration of MBC-FET and C-FET based on large-scale 2D semiconductors will promote the application of 2D semiconductors in next-generation circuits.