P-type Field-effect Transistors Research Articles

Lowering the Schottky Barrier Height by Quasi-van der Waals Contacts for High-Performance p-Type MoTe2 Field-Effect Transistors.

Two-dimensional (2D) transition-metal dichalcogenides (TMDs) offer advantages over traditional silicon in future electronics but are hampered by the prominent high contact resistance of metal-TMD interfaces, especially for p-type TMDs. Here, we present high-performance p-type MoTe2 field-effect transistors via a nondestructive van der Waals (vdW) transfer process, establishing low contact resistance between the 2D MoTe2 semiconductor and the PtTe2 semimetal. The integration of PtTe2 as contacts in MoTe2 field-effect transistors leads to significantly improved electrical characteristics compared to conventional metal contacts, evidenced by a mobility increase to 80 cm2 V-1 s-1, an on-state current rise to 5.0 μA/μm, and a reduction in Schottky barrier height (SBH) to 48 meV. Such a low SBH in quasi-van der Waals contacts can be assigned to the low electrical resistivity of PtTe2 and the high efficiency of carrier injection at the 2D semimetal/2D semiconductor interfaces. Imaging via transmission electron microscopy reveals that the 2D semimetal/two-dimensional semiconductor interfaces are atomically flat and exceptionally clean. This interface engineering strategy could enable low-resistance contacts based on vdW architectures in a facile manner, providing opportunities for 2D materials for next-generation optoelectronics and electronics.

Efficient Addition Circuits Using Three-Gate Reconfigurable Field Effect Transistors

Reconfigurable FETs (RFETs) are widely recognized as a promising way to overcome conventional CMOS architectures. This paper presents novel addition circuit intentionally designed to exploit the ability of RFETs to operate efficiently on demand as n- or p-type FETs. First, a novel Full Adder (FA) is proposed and characterized. A comparison with other designs shows that the proposed FA achieves a worst-case delay and a dynamic power consumption of up to 43.5% and 79% lower. As a drawback, in terms of the estimated area, it is up to 32% larger than the competitors. Then, the new FA is used to implement Ripple-Carry Adders (RCAs). A 32-bit adder designed as proposed herein reaches an energy–delay product (EDP) ~25.7× and ~141× lower than its CMOS and the RFET-based counterparts.

Manipulation of Charge Transport in MoS2/MoTe2 Field Effect Transistors and Heterostructure by Propagating the Surface Acoustic Wave.

Two-dimensional (2D) materials with atomic-scale thickness are promising candidates to develop next-generation electronic and optoelectronic devices with multiple functions due to their widely tunable physical properties by various stimuli. The surface acoustic wave (SAW) produced at the surface of the piezoelectrical substrate can generate electrical and strain fields simultaneously with micro/nanometer resolution during propagation. It provides a stable and wireless platform to manipulate the rich and fascinating properties of 2D materials. However, the interaction mechanisms between the SAW and 2D materials remain unclear, preventing further development and potential applications of SAW-integrated 2D devices. This work studied the acoustoelectric (AE) charge transport mechanism in 2D materials thoroughly by characterizing the performances of the n-type MoS2 and p-type MoTe2 field effect transistors (FETs) and the MoS2/MoTe2 p-n junction driven by the SAW. As compared to the case driven by the static electrical field alone, the SAW drove the electron and hole transport along the same direction as its propagation, and the generated AE current always had the opposite direction to the AE voltage. In the device level, the 2D FETs showed a significantly reduced subthreshold swing up to around 67% when the SAW was used to drive the channel carriers, indicating that the SAW enhanced the on/off switching speed. Moreover, the MoTe2/MoS2 p-n junction showed a tunable photoresponsivity by the power and propagation direction of the SAW. These findings provide a solid foundation to promote future research and potential applications of SAW-driven multifunctional devices based on 2D materials.

IDTI based copolymers for p-type organic field-effect transistors

Organic semiconductors received more and more attention in the past few years. Development some novel chromophore with the strong electron-deficient to construct donor–acceptor polymers plays a crucial role for the development of the organic semiconductors. A new acceptor indaceno[1,2-b:5,6-b′]dithiophene)-2,7-diylbis(methan-1-yl-1-ylidene))bis(6-bromo-indolin-2-one) (IDTI, M1), as well as a IIDT-based polymer P1 were designed in this work, and for the first time applied in the OFET. The results shows that the P1 present not only a strong aggregation, but also a suitable highest occupied molecular orbital (HOMO) energy level. As a consequent, the P1 exhibited a p-type behavior with the hole mobility up to 0.29 cm2 V−1 s−1. This work demonstrated that the IDTI chromophore is a promising electron-deficient block for the constructing donor–acceptor high performance semiconductor polymers.

Evaluating the performance of p-type organic field-effect transistor using different source–drain electrodes

Evaluating the performance of p-type organic field-effect transistor using different source–drain electrodes

Investigation of thermal stress effects on subthreshold conduction in nanoscale p-FinFET from Multiphysics perspective

The rising temperature due to a self-heating or thermal environment not only degrades the subthreshold performance but also intensifies thermal stress, posing a severe challenge to device performance and reliability design. The thermal stress effects on the ON-state performance of the p-type fin field-effect transistor were previously studied. However, as far as we know, how thermal stress affects its subthreshold conduction remains unclear, which is studied in this manuscript. The impact of thermal stress due to the self-heating of adjacent devices on subthreshold conduction is investigated by solving the quantum transport, thermal conduction, and force balance equations for ballistic transport and dissipative transport with phonon scattering. Then, the thermal stress effects at different ambient temperatures are further discussed and analyzed. The simulation results show that the OFF-state leakage current can be reduced by thermal stress, even up to 9.28% for the (110)/[001] device operating at an ambient temperature of 550 K, and its reduction is the comprehensive result of the thermal stress effects on the band structure, potential profile, carrier distribution, and source-to-drain tunneling. In addition, the thermal stress has no significant effects on subthreshold swing although it can change the magnitude of the subthreshold current. Moreover, the effect of thermal stress on subthreshold conduction is highly dependent on the thermal environment of the device and the crystal orientation of the channel semiconductor material.

2-D Si0.8Ge0.2 source double-gate pocket PTFET for low power application: Modeling and simulation

To process 1-bit of information the small supply voltage (Vdd) and minimal leakage current are needed for transistors. Subthreshold swing (SS) of 60 mV/dec at 300 K is the basic bottleneck in metal oxide semiconductor field effect transistors. DFT in QuantumATK R-2020.09 was used to study Si0.8Ge0.2 band structure and band gap. A p-type tunnel field effect transistor (PTFET) was modeled employing the dual gate concept. Top gate has two metals; source and counter doped pocket are Si0.8Ge0.2. According to the proposed device simulation, the proposed device is showing excellent thermal stability for large on-current (Ion), weak off-current (Ioff), and weak ambipolar current (Iambi) at different temperatures. The proposed device achieves the Ion of 72.44 µA/µm and 3.2 µA/µm at supply voltage of −1 V and −0.5 V, respectively. At −0.5 V of Vdd, current ratio of Ion/Ioff is more than 1012, so device can be used for low power applications.

Single flake homo p–n diode of MoTe2 enabled by oxygen plasma doping

Abstract Two-dimensional (2D) materials play a crucial role as fundamental electrical components in modern electronics and optoelectronics next-generation artificial intelligent devices. This study presents a methodology for creating a laterally uniform p–n junction by using a partial oxygen plasma-mediated strategy to introduce p-type doping in single channel MoTe2 device. The MoTe2 field effect transistors (FETs) show high electron mobility of about ∼23.54 cm2 V−1 s−1 and a current ON/OFF ratio of ∼106 while p-type FETs show hole mobility of about ∼9.25 cm2 V−1 s−1 and current ON/OFF ratio ∼105 along with artificially created lateral MoTe2 p–n junction, exhibited a rectification ratio of ∼102 and ideality factor of ∼1.7 which is proximity to ideal-like diode. Thus, our study showed a diversity in the development of low-power nanoelectronics of next-generation integrated circuits.

Ultrashort channel MoSe2 transistors with selenium atoms replaced at the interface: first-principles quantum-transport study

Realizing n- and p-type transition metal dichalcogenide (TMD)-based field-effect transistors for nanoscale complementary metal oxide semiconductor (CMOS) applications remains challenging owing to undesirable contact resistance. Quantumtransport calculations were performed by replacing single-sided Se atoms of TMD near the interface with As or Br atoms to further improve the contact resistance. Here, partial selenium replacement produced a novel interface with a segment of metamaterial MoSeX (Pt/MoSeX/MoSe2; X = As, Br). Such stable metamaterials exhibit semi-metallicity, and the contact resistance can be thus lowered. Our findings provide insights into the potential of MoSe2-based nano-CMOS logic devices.

Optimized electrical properties of p-type field-effect transistors based on WSe2 grown at moderate temperatures

Two-dimensional transition-metal dichalcogenides (TMDCs) have been pursued for high-performance logic electronic devices, and compatibility with silicon complementary metal-oxide-semiconductor (CMOS) technology is essential. Thus, high-quality material synthesis at reduced temperature is a key challenge for TMDC integration with the back-end-of-line silicon CMOS. In this work, TMDCs have been synthesized at temperatures down to 450 °C on SiO2/Si substrates via chemical vapor deposition. This work highlights the necessity of improving metal precursor mass flux during the low-temperature synthesis of TMDC films. Improved electrical characteristics of the back-gated p-type field-effect transistors based on monolayer WSe2 exhibit an on-current of 14 μA/μm and subthreshold swing of 200 mV/dec.

High-precision and high-speed etching of diamond surfaces using Fe–Ni alloy catalyzed H–O plasma etching

Power devices with low losses are essential for achieving high-efficiency, low-cost, and miniaturized inverters and advance electronic technologies. Recently, diamond-based p-type groove semiconductor field-effect transistors have emerged as a hot research topic. Conventional method of fabricating surface grooves using inductively coupled plasma etching is costly and relatively slow. Here, we realized a novel diamond machining method using Fe–Ni alloy catalyzed H–O microwave plasma etching that can achieve high-rate and high-precision etching of diamond surfaces. Two major factors affecting the etching rate and pattern accuracy, wettability of diamond and carbon solubility with liquid metal, were identified. Oxygen added in H2 plasma allows the wetting increase, resulting in an improvement in uniformity of the etch area, while keeping the etch rate as high as 3 μm/min. The developed approached is promising for low-cost diamond patterning in electronic devices fabrication processes.

Self-Aligned Top-Gate Structure in High-Performance 2D p-FETs via van der Waals Integration and Contact Spacer Doping.

The potential of 2D materials in future CMOS technology is hindered by the lack of high-performance p-type field effect transistors (p-FETs). While utilization of the top-gate (TG) structure with a p-doped spacer area offers a solution to this challenge, the design and device processing to form gate stacks pose serious challenges in realization of ideal p-FETs and PMOS inverters. This study presents a novel approach to address these challenges by fabricating lateral p+-p-p+ junction WSe2 FETs with self-aligned TG stacks in which desired junction is formed by van der Waals (vdW) integration and selective oxygen plasma-doping into spacer regions. The exceptional electrostatic controllability with a high on/off current ratio and small subthreshold swing (SS) of plasma doped p-FETs is achieved with the self-aligned metal/hBN gate stacks. To demonstrate the effectiveness of our approach, we construct a PMOS inverter using this device architecture, which exhibits a remarkably low power consumption of approximately 4.5 nW.

Toward High-Performance p-Type Two-Dimensional Field Effect Transistors: Contact Engineering, Scaling, and Doping.

n-type field effect transistors (FETs) based on two-dimensional (2D) transition-metal dichalcogenides (TMDs) such as MoS2 and WS2 have come close to meeting the requirements set forth in the International Roadmap for Devices and Systems (IRDS). However, p-type 2D FETs are dramatically lagging behind in meeting performance standards. Here, we adopt a three-pronged approach that includes contact engineering, channel length (Lch) scaling, and monolayer doping to achieve high performance p-type FETs based on synthetic WSe2. Using electrical measurements backed by atomistic imaging and rigorous analysis, Pd was identified as the favorable contact metal for WSe2 owing to better epitaxy, larger grain size, and higher compressive strain, leading to a lower Schottky barrier height. While the ON-state performance of Pd-contacted WSe2 FETs was improved by ∼10× by aggressively scaling Lch from 1 μm down to ∼20 nm, ultrascaled FETs were found to be contact limited. To reduce the contact resistance, monolayer tungsten oxyselenide (WOxSey) obtained using self-limiting oxidation of bilayer WSe2 was used as a p-type dopant. This led to ∼5× improvement in the ON-state performance and ∼9× reduction in the contact resistance. We were able to achieve a median ON-state current as high as ∼10 μA/μm for ultrascaled and doped p-type WSe2 FETs with Pd contacts. We also show the applicability of our monolayer doping strategy to other 2D materials such as MoS2, MoTe2, and MoSe2.

P-type cold-source field-effect transistors with TcX 2 and ReX 2 (X = S, Se) cold source electrodes: A computational study

Cold-source field-effect transistors (CS-FETs) have been developed to overcome the major challenge of power dissipation in modern integrated circuits. Cold metals suitable for n-type CS-FETs have been proposed as the ideal electrode to filter the high-energy electrons and break the thermal limit on subthreshold swing (SS). In this work, regarding the p-type CS-FETs, we propose TcX 2 and ReX 2 (X = S, Se) as the injection source to realize the sub-thermal switching for holes. First-principles calculations unveils the cold-metal characteristics of monolayer TcX 2 and ReX 2, possessing a sub-gap below the Fermi level and a decreasing DOS with energy. Quantum device simulations demonstrate that TcX 2 and ReX 2 can enable the cold source effects in WSe2 p-type FETs, achieving steep SS of 29–38 mV/dec and high on/off ratios of (2.3–5.6) × 107. Moreover, multilayer ReS2 retains the cold metal characteristic, thus ensuring similar CS-FET performances to that of the monolayer source. This work underlines the significance of cold metals for the design of p-type CS-FETs.

A Buried Thermal Rail (BTR) Technology to Improve Electrothermal Characteristics of Complementary Field-Effect Transistor (CFET).

The complementary field-effect transistor (CFET) with N-type FET (NFET) stacked on P-type FET (PFET) is a promising device structure based on gate-all-around FET (GAAFET). Because of the high-density stacked structure, the self-heating effect (SHE) becomes more and more severe. Buried thermal rail (BTR) technology on top of the buried power rail (BPR) process is proposed to improve heat dissipation. Through a systematical 3D Technology Computer Aided Design (TCAD) simulation, compared to traditional CFET and CFET with BPR only, the thermal resistance (Rth) of CFET can be significantly reduced with BTR technology, while the drive capability is also improved. Furthermore, based on the proposed BTR technology, different power delivery structures of top-VDD-top-VSS (TDTS), bottom-VDD-bottom-VSS (BDBS), and bottom-VDD-top-VSS (BDTS) were investigated in terms of electrothermal and parasitic characteristics. The Rth of the BTR-BDTS structure is decreased by 5% for NFET and 9% for PFET, and the Ion is increased by 2% for NFET and 7% for PFET.

Fabrication and Characterization of Self-Aligned WSe2 p-Type Field-Effect Transistor

Semiconducting transition metal dichalcogenides (TMDCs) have been growing interests as channel materials in field effect transistors (FET) for next generation low power digital electronics. [1]. Since a complementary metal oxide-semiconductor (CMOS) inverter constructed from pairs of n-type and p-type FETs is a fundamental building blocks in modern digital electronics [2], implementation of both n-type and p-type FETs with semiconducting TMDCs is of particular importance [3]. Among various semiconducting TMDCs, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [4]. These prominent features of WSe2 is suitable for an application to CMOS inverter.One of the significant challenges is to develop a top gate and top contact FET structure with WSe2 for CMOS device integration on the same wafer. In addition, it is desirable to minimize the access region between channel and S/D contact because this access region served as a series resistance to channel resistance, resulting in the lower drain current in FET. This study reports a self-aligned process to fabricate top gate and top contact WSe2 p-type FET. In this self-aligned structure, the gate electrode and source/drain contact edges are automatically positioned and hence there are no overlap or access region between the gate and source/drain. The feature of this proposed method is that the gate stacks was utilized as a mask for self-aligned formation of WOx, which is source/drain contact for efficient hole injection [5]. The focus on this study is the impact of self-aligned structure of p-type WSe2 FET on the electrical characteristics. The effectiveness of proposed process was experimentally demonstrated by the fabrication and characterization of device.Figures 1 shows the self-aligned fabrication process of p-type WSe2 FET. 20 nm-thick SiO2 was formed by dry oxidation of p+-Si substrate. The mechanically exfoliated multi-layer WSe2 was transferred by PDMS stamp. Next, 15 nm-thick Al2O3 was prepared by ALD at 200 oC with H2O. Then, Nickel (Ni) metal was deposited by RF sputtering on Al2O3. Ni metal was patterned for gate electrode with conventional lithography process. After that, A2O3 layer was removed by wet etching. Subsequently, substrate was exposed to oxygen radicals to form WOx used as source/drain contact at surface of WSe2. Second layer of Al2O3 was deposited as an encapsulating passivation layer. After the contact hole opening, the electrical contact pad was fabricated. Finally, forming gas (N2 : H2 = 97 % : 3 %) annealing was performed at 200 oC for 30 min. The top gate length was 5 μm. The gate width was estimated to be 40 μm by optical microscope. The electrical characteristics were measured with a manual probe station in an atmospheric pressure without inert gas purge at room temperature using a precision semiconductor parameter analyzer (Agilent 4156 C).Figures 2 shows the Id–Vg characteristics of fabricated FETs for (a) back gate operation and (b) top gate operation. Representative Id–Vg characteristics of p-type FETs were observed irrespective of back gate and top gate operation. The on/off ratio of about 106 ~ 107 order were obtained for both back gate and top gate operation. Furthermore, the threshold voltage and sub-threshold slope were modulated by varying the substrate bias during gate sweep.This study opens up interesting directions for the research and development of TMDC-based devices.AcknowledgmentsThis study was supported by a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616), a research grant for Tokyo Tech Challenging Research Award, the Samco Foundation and a research grant for Suematsu Award.

(Invited) High-Performance Field-Effect Transistors Based on Two-Dimensional Materials for VLSI Circuits

Introduction Nowadays, the scaling of silicon very large-scale integration(VLSI) technologies has reached channel thicknesses of 7nm. However, further downscaling becomes increasingly difficult as the gate electrostatics require a substantial reduction of the channel thickness to about a fourth of the gate length. As a result, the actual gate length of high-performance(HP) FETs at the current state-of-the-art amounts to 16nm and is projected to stall at 12nm for the 1.5nm node and the following nodes, according to the International Roadmap for Devices and Systems(IRDS)[1]. For these nodes, two-dimensional(2D) materials could have the potential to replace silicon as the channel material. They can maintain sizable mobilities at atomic thicknesses, thus providing enhanced gate control in stacked channel nanosheet transistor structures[2]. Even though FETs based on 2D materials hold the promise to serve as FETs at the front end of the line, numerous challenges still need to be overcome. Downscaling Dimensions For ultra-scaled device designs, 2D materials can be used as a channel in stacked nanosheet FETs. In such a structure, the 2D material is gated from both sides, as depicted in Fig.1(a). By stacking multiple double-gated channels on top of each other, the required on-current density of around 1mA/μm can be achieved[3]. The first experimental demonstrations have achieved sub-5nm gate lengths[4] or, in a different design, a gate pitch of only 42nm[5], meeting the requirements for the 1.5nm node. While these prototypes show that 2D FETs can be scaled down, they have been fabricated in a laboratory. Many challenges must be overcome before such small devices can be fabricated in industry-compatible batch processes which require a high yield and low variability. Contact Engineering In order to enable sufficiently high on-current densities, small contact resistances to 2D semiconductors are required, which are inhibited by the formation of Schottky barriers at the metal to semiconductor interface. Schottky contacts to 2D materials are so prevalent because there is, on one side, a lack of stable doping schemes, and on the other side, pronounced Fermi-level pinning at the metal-to-semiconductor interface. Semi-metallic bismuth contacts can provide low-resistive contacts to n-type MoS2 FETs, as the bismuth suppresses the metal-induced gap states which pin the Fermi-level[6]. This way, a small contact resistance of 123Ωμm has been achieved, reaching the IRDS limit for the 1.5nm node. While comparable results have been realized for antimony contacts to n-type FETs, low-resistive contacts to p-type FETs are more challenging. Gate Stack Design A good gate stack for 2D FETs must provide excellent gate control while maintaining small gate leakage currents, which requires a capacitive equivalent thickness(CET) smaller than 0.9 nm. At these small CETs, a small gate leakage can only be obtained with a high-dielectric constant gate insulator and sizable band offsets, rendering some insulators, e.g. hexagonal boron nitride, unsuitable. Simultaneously, the gate insulator should form a van-der Waals interface with the 2D semiconductor, as otherwise, interface traps degrade the carrier mobility and the sub-threshold slope[7]. Charge traps within the insulator are the root cause of the limited stability and reliability of 2D FETs, as seen by a large hysteresis in the transfer characteristics or in pronounced Bias Temperature Instabilities(BTI). The electrical stability can be improved, if the defect bands in the gate insulator are energetically far away from the semiconductor’s conduction and valence band edges, see Fig.1(b)[8]. Conclusions Despite all the progress achieved within the last decade, the challenges for VLSI integration of 2D materials are enormous. First, stacked 2D FETs with scaled dimensions still need to be realized at an industrial scale. Second, despite low contact resistance demonstrations for n-type FETs, the resistances for p-type FETs are one order of magnitude too high. Finally, one of the most serious obstacles is identifying a suitable gate stack. Even though promising combinations of insulators to semiconductors have been suggested, like Bi2O5Se/Bi2O2Se, CaF2/MoS2 or SrTiO3/MoS2, it is at the moment unclear, which of them provides the best performance. Acknowledgments The authors thank for funding from the European Research Council under grant agreement no. 101055379.

(Invited) Gate Stack Design for Field-Effect Transistors Based on Two-Dimensional Materials

1.Introduction Two-dimensional(2D) materials hold the promise to allow for ultrathin channels built of single atomic monolayers in ultimately scaled field-effect transistors (FETs). Due to this small thickness, an enhanced gate control is achieved while at the same time sizable mobilities in the 2D materials can be maintained[1]. In this way, the on-current density of the devices could potentially be increased to up to 1mA/μm by stacking six nanosheets on top of each other, combining p-type and n-type FETs in vertical integration. Even though FETs based on 2D materials hold a lot of promise, numerous challenges still need to be overcome. One of the most serious obstacles is the identification of a suitable gate stack. Over the last years, several insulators have been suggested, including layered insulators like hBN[2], ionic insulators like CaF2[3], amorphous high-k dielectrics like HfO2[4], see Fig.1. In addition, crystalline perovskites like SrTiO3[5] or native oxides like Bi2SeO5[6] have been explored. However, which of these materials provides the best performance is at the moment unclear and needs to be evaluated according to the criteria of scalability (Section 2), the minimization of charge traps (Section 3), and batch-processing compatible deposition technology for double-gated device designs (Section 4). 2.Scalable Gate Stacks High-performance FETs require a high on/off current ratio and steep subthreshold slopes. In order to preserve these characteristics in devices with ultimately scaled channel lengths, the insulator capacitance needs to be higher than 1.5μFcm-2, corresponding to a capacitive equivalent thickness smaller than 1nm. At the same time, if the insulator thickness becomes too small, the gate leakage current often easily exceeds the low-power limit of 0.015 Acm-2, thereby increasing the standby power consumption in the off-state. In fact, the gate leakage currents through thin hBN layers are high, rendering it unsuitable as a gate insulator for scaled FETs, while CaF2, HfO2 or Bi2SeO5 show promise[7]. 3.Minimizing Charge Traps The gate insulator should form a van der Waals interface with the 2D semiconductor, as otherwise, interface traps will degrade the carrier mobility and the sub-threshold slope[8]. Charge traps within the insulators cause limited stability and reliability of 2D FETs, as seen by a large hysteresis in the transfer characteristics or in Bias Temperature Instabilities. As a consequence, the stability can be enhanced if the defect bands in the gate insulator are energetically far away from the conduction and valence band edges[9]. Thus, the number of electrically active charge traps can be minimized by selecting a suitable combination of 2D semiconductor to insulator or by reducing the width of the defect bands by using crystalline insulators. 4.Deposition Technology Gate insulators need to be deposited on top of 2D semiconductors for top gate formation. However, the inert planes of 2D materials inhibit direct nucleation of insulators from the gaseous phase in an atomic layer deposition process. In this context, a promising approach is to use a self-assembled polymer monolayer to nucleate the precursors[4]. Molecular beam epitaxy is an alternative growth approach for gate insulators which offers the advantage of van der Waals epitaxy for layered materials, where the lattice-matching conditions are relaxed[10]. In order to avoid the growth of the insulator on top of the 2D semiconductor altogether the in-situ oxidation of the 2D semiconductor to its native oxide is a promising option, like for Bi2SeO5. 5.Conclusions Even though many novel insulator systems for 2D FETs have been proposed over the last couple of years, it is still unclear which of them best meets the requirements formulated. The most important questions to be addressed in the future will be to identify systems with reproducibly small interface and border trap densities and high thermal stability and to develop suitable batch-processing compatible top gate deposition methods for these material systems. Acknowledgments The authors thank for funding from the European Research Council under grant agreement no.101055379.

Impact of an Underlying 2DEG on the Performance of a p-Channel MOSFET in GaN.

The influence of an underlying 2-dimensional electron gas (2DEG) on the performance of a normally off p-type metal oxide semiconductor field effect transistor (MOSFET) based on GaN/AlGaN/GaN double heterojunction is analyzed via simulations. By reducing the concentration of the 2DEG, a greater potential can be dropped across the GaN channel, resulting in enhanced electrostatic control. Therefore, to minimize the deleterious impact on the on-state performance, a composite graded back-to-back AlGaN barrier that enables a trade-off between n-channel devices and Enhancement-mode (E-mode) p-channel is investigated. In simulations, a scaled p-channel GaN device with LG = 200 nm, LSD = 600 nm achieves an ION of 65 mA/mm, an increase of 44.4% compared to a device with an AlGaN barrier with fixed Al mole fraction, ION/IOFF of ∼1012, and |Vth| of | - 1.3 V|. For the n-channel device, the back-to-back barrier overcomes the reduction of ION induced by the p-GaN gate resulting in an ION of 860 mA/mm, an increase of 19.7% compared with the counterpart with the conventional barrier with 0.5 V positive Vth shift.

Role of time-dependent foreign molecules bonding in the degradation mechanism of polymer field-effect transistors in ambient conditions.

Long-standing research efforts have enabled the widespread introduction of organic field-effect transistors (OFETs) in next-generation technologies. Concurrently, environmental and operational stability is the major bottleneck in commercializing OFETs. The underpinning mechanism behind these instabilities is still elusive. Here we demonstrate the effect of ambient air on the performance of p-type polymer field-effect transistors. After exposure to ambient air, the device showed significant variations in performance parameters for around 30 days, and then relatively stable behaviour was observed. Two competing mechanisms influencing environmental stability are the diffusion of moisture and oxygen in the metal-organic interface and the active organic layer of the OFET. We measured the time-dependent contact and channel resistances to probe which mechanism is dominant. We found that the dominant role in the degradation of the device stability is the channel resistance rather than the contact resistance. Through time-dependent Fourier transform infrared (FTIR) analysis, we systematically prove that moisture and oxygen cause performance variation in OFETs. FTIR spectra revealed that water and oxygen interact with the polymer chain and perturb its conjugation, thus resulting in degraded performance of the device upon prolonged exposure to ambient air. Our results are important in addressing the environmental instability of organic devices.