P-type Devices Research Articles

Interlayer Engineering of Band Gap and Hole Mobility in p-Type Oxide SnO.

The development of high-performance p-type oxides with wide band gap and high hole mobility is critical for the application of oxide semiconductors in back-end-of-line (BEOL) complementary metal-oxide-semiconductor (CMOS) devices. SnO has been intensively studied as a high-mobility p-type oxide due to its low effective hole mass resulting from the hybridized O-2p/Sn-5s orbital character at the valence band edge. However, SnO has a very small band gap (∼0.7 eV) for practical p-type oxide devices. In this work, we report an engineering method to enhance the band gap and hole mobility in SnO. It is found that both the band gap and the hole mobility of a layer-structured SnO increase with the interlayer stacking spacing change. By exploiting this unique electronic structure feature, we propose expanding the interlayer spacing by interlayer intercalation to engineer the band gap and p-type mobility in SnO. Small molecules like NH3 and CH4 are shown to be capable of expanding the interlayer spacing and of increasing the band gap and hole mobility in SnO and thus could potentially serve as the interlayer intercalants. The results provide a viable way for the experimental realization of wide-band-gap and high hole-mobility p-type SnO for BEOL vertical CMOS device applications.

Ag-Modified Porous Perovskite-Type LaFeO3 for Efficient Ethanol Detection.

Perovskite (ABO3) nanosheets with a high carrier mobility have been regarded as the best candidates for gas-sensitive materials arising from their exceptional crystal structure and physical–chemical properties that often exhibit good gas reactivity and stability. Herein, Ag in situ modified porous LaFeO3 nanosheets were synthesized by the simple and efficient graphene oxide (GO)-assisted co-precipitation method which was used for sensitive and selective ethanol detection. The Ag modification ratio was studied, and the best performance was obtained with 5% Ag modification. The Ag/LaFeO3 nanomaterials with high surface areas achieved a sensing response value (Rg/Ra) of 20.9 to 20 ppm ethanol at 180 °C with relatively fast response/recovery times (26/27 s). In addition, they showed significantly high selectivity for ethanol but only a slight response to other interfering gases. The enhanced gas-sensing performance was attributed to the combination of well-designed porous nanomaterials with noble metal sensitization. The new approach is provided for this strategy for the potential application of more P-type ABO3 perovskite-based gas-sensitive devices.

Performance Limit of Ultrathin GaAs Transistors.

High-electron-mobility group III-V compounds have been regarded as a promising successor to silicon in next-generation field-effect transistors (FETs). Gallium arsenide (GaAs) is an outstanding member of the III-V family due to its advantage of both good n- and p-type device performance. Monolayer (ML) GaAs is the limit form of ultrathin GaAs. Here, a hydrogenated ML GaAs (GaAsH2) FET is simulated by ab initio quantum-transport methods. The n- and p-type ML GaAsH2 metal-oxide-semiconductor FETs (MOSFETs) can well satisfy the on-state current, delay time, power dissipation, and energy-delay product requirements of the International Technology Roadmap for Semiconductors until the gate length is scaled down to 3/4 and 3/5 nm for the high-performance/low-power applications, respectively. Therefore, ultrathin GaAs is a prominent channel candidate for devices in the post-Moore era. The p-type ML GaAsH2 MOSFETs with a 2% uniaxially compressive strain and the unstrained n-type counterparts have symmetrical performance for the high-performance application, making ultrathin GaAs applicable for complementary MOS integrated circuits.

Selective electrochemical etching of cantilever-type SOI-MEMS devices

It is possible to achieve selective electrochemical etching between different materials, such as p- and n-type silicon. However, achieving selective electrochemical etching on two different regions of the same p-type silicon material is a problem that has rarely been considered. Herein, a novel selective electrochemical etching technique for cantilever-type silicon-on-insulator (SOI) wafer-based microswitches is proposed. In this study, a p-type handle layer was selectively etched, and a p-type device layer was passivated. This was achieved using a circuit with two voltage sources: voltages of −1.2 and 0 V were applied to the handle and device layers, respectively. It was found that the proposed etching process can effectively prevent the in-use sticking of a cantilever-type switch. This is accomplished by increasing the gap between the device layer and its underlying handle layer and increasing the roughness of these layers. The technique is applicable to the fabrication of various cantilever-type SOI microelectromechanical systems, irrespective of the resistivity of the SOI wafer.

Quantum transport in p-type narrow channel with DC-biased double finger gate

The quantum transport in a p-type narrow channel device with a DC-biased double finger gate is investigated using a Luttinger four-band Hamiltonian and a propagation matrix approach. The results show that when the potential energy modulation effect produced by the finger gate is large, the quantum transport shows a resonance behavior indicative of large barriers in a double-barrier system. A simple analytical method based on an ideal resonant square quantum well approximation is used to predict the energies of the resonance peaks contributed by the light and heavy holes. The results show that the first conductance peak is formed at 2e2/h and is contributed by the heavy holes. A second conductance resonance peak is formed at 3e2/h due to the semi-reflection of the heavy holes and resonant transmission of the light holes. Finally, a third conductance resonance peak is formed at 4e2/h as a result of the concurrent resonant transmission of the light holes and heavy holes.

Experimental and theoretical study of hole scattering in RF sputtered p-type Cu2O thin films

One of the key materials of interest for p-type oxide semiconductor thin film electronics is cuprous oxide (Cu2O), due to its relatively high hole mobility. In this work, we use experiments, analytical models, and density functional theory calculations to study the scattering mechanisms that determine Hall mobility in two Cu2O samples. First, we examine a polycrystalline Cu2O thin film deposited by RF magnetron sputtering, and second, a single-crystalline Cu2O bulk substrate. Temperature-dependent Hall measurements indicate that neutral impurity and grain boundary scattering are dominant for the polycrystalline Cu2O thin film, while phonon scattering is dominant for single-crystalline Cu2O. Our first-principles calculations show that the room-temperature intrinsic hole mobility of Cu2O is 106 cm2 V−1 s−1, indicating the great promise of the material for p-type electronic devices. This intrinsic mobility is limited by phonon scattering, with the most dominant scattering modes having phonon energies of 88.4 and 17.1 meV. These results indicate that the key pathways to increase the hole mobility in Cu2O thin films are by reducing the impurity concentration and by increasing grain size. Our work thus sets the stage for the future development of high performance Cu2O-based p-type thin film transistors.

Analytic modeling of a hybrid power module based on diamond and SiC devices

Unlike SiC unipolar devices, the on-state resistance of diamond unipolar devices based on bulk conduction has a negative temperature coefficient (NTC) which reduces the conduction losses at high junction temperatures. Thus, in order to associate these opposed temperature coefficients, the current article focuses on the modeling of a hybrid power device composed of a n-type 4H-SiC MOSFET and a p-type diamond bulk FET device. The optimal performances and sizing of SiC and diamond devices are introduced and calculated, as an initial benchmark under the same specifications. Based on an analytical modeling of both switching and conduction losses, junction temperatures and associated heatsink parameters, the hybrid device performances are evaluated for a synchronous buck converter operating at 1200 V–1 A and at an ambient temperature of 300 K. The results described in the manuscript highlight an equilibrium of the hybrid device total losses over a large range of temperatures as well as a reduction by two of the SiC active area. The proposed analysis could be further extended to different voltage/current classes to meet the requirements of alternative applications.

A Polarization-Switching, Charge-Trapping, Modulated Arithmetic Logic Unit for In-Memory Computing Based on Ferroelectric Fin Field-Effect Transistors.

Nonvolatile logic devices are crucial for the development of logic-in-memory (LiM) technology to build the next-generation non-von Neumann computing architecture. Ferroelectric field-effect transistors (Fe FET) are one of the most promising candidates for LiMs because of high compatibility with mainstream silicon-based complementary metal-oxide semiconductor processes, nonvolatile memory, and low power consumption. However, because of the unipolar characteristics of a Fe FET, a nonlinear XOR or XNOR logic gate function is difficult to realize with a single device. In addition, because single Fe polarization switch modulation is available in the devices, a reconfigurable logic gate usually needs multiple devices to construct and realize fewer logic functions. Here, we introduced polarization-switching (PS) and charge-trapping (CT) effects in a single Fe FET and fabricated a multi-field-effect transistor with bipolar-like characteristics based on advanced 10 nm node fin field-effect transistors (PS-CT FinFET) with 9 nm thick Hf0.5Zr0.5O2 films. The special hybrid effects of charge-trapping and polarization-switching enabled eight Boolean logic functions with a single PS-CT FinFET and 16 Boolean logic functions with two complementary PS-CT FinFETs were obtained with three operations. Furthermore, reconfigurable full 1 bit adder and subtractor functions were demonstrated by connecting only two n-type and two p-type PS-CT FinFET devices, indicating that the technology was promising for LiM applications.

Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si.

Sb-based semiconductors are critical p-channel materials for III–V complementary metal oxide semiconductor (CMOS) technology, while the performance of Sb-based metal-oxide-semiconductor field-effect transistors (MOSFETs) is typically inhibited by the low quality of the channel to gate dielectric interface, which leads to poor gate modulation. In this study, we achieve improved electrostatics of vertical GaSb nanowire p-channel MOSFETs by employing robust digital etch (DE) schemes, prior to high-κ deposition. Two different processes, based on buffer-oxide etcher (BOE) 30:1 and HCl:IPA 1:10, are compared. We demonstrate that water-based BOE 30:1, which is a common etchant in Si-based CMOS process, gives an equally controllable etching for GaSb nanowires compared to alcohol-based HCl:IPA, thereby realizing III–V on Si with the same etchant selection. Both DE chemicals show good interface quality of GaSb with a substantial reduction in Sb oxides for both etchants while the HCl:IPA resulted in a stronger reduction in the Ga oxides, as determined by X-ray photoelectron spectroscopy and in agreement with the electrical characterization. By implementing these DE schemes into vertical GaSb nanowire MOSFETs, a subthreshold swing of 107 mV/dec is obtained in the HCl:IPA pretreated sample, which is state of the art compared to reported Sb-based MOSFETs, suggesting a potential of Sb-based p-type devices for all-III–V CMOS technologies.

Improving performance of monolayer arsenene tunnel field-effect transistors by defects.

We systematically investigate the transport properties of monolayer arsenene tunneling field-effect transistors (TFETs) along the armchair and zigzag directions using first-principles calculations based on density functional theory (DFT) combined with the non-equilibrium Green's function (NEGF) approach. We introduce five types of defects at the source-channel interface and study their influences on the device performance. The pristine arsenene TFETs along the armchair direction have large ON-state currents due to the small effective masses, but still cannot meet the International Technology Roadmaps of Semiconductor 2022 (ITRS 2022) requirements for high performance (HP) devices. The adsorption of one and two H atoms can significantly enhance the ON-state currents to above 1412 μA μm−1 and reduce subthreshold swing (SS) to below 60 mV decade−1 for both n- and p-type devices, satisfying the ITRS 2022 requirements for HP devices. Besides, the p-type As and the n-type Li adatoms can improve the performance of p-type and n-type devices, respectively. The pristine arsenene TFETs along the zigzag direction with low ON-state currents already meet the ITRS 2022 requirements for low-power (LP) devices. The performance of the p-type TFETs as LP devices can be improved by p-type SV and the As adatom by increasing the ON-state currents and/or reducing the SS. On the other hand, the adsorption of one H adatom can remarkably increase the ON-state current of the p-type TFET to 1563 μA μm−1 and reduce SS to 34 mV decade−1, allowing the device to work as an HP device. We further confirm that the enhancement of the ON-state currents is due to the shortening of the band-to-band tunneling path through the defect induced gap states. Our calculations provide a theoretical guide to improve the performance of TFETs based on arsenene or other monolayer materials by suitable defects.

Quantum transport of short-gate MOSFETs based on monolayer MoSi2N4.

The high carrier mobility, appropriate band gap and good environmental stability of two-dimensional (2D) MoSi2N4 enable it to be an appropriate channel material for transistors with excellent performance. Therefore, we predict the performance of double-gate (DG) metal-oxide-semiconductor field-effect transistors (MOSFETs) based on monolayer (ML) MoSi2N4 by ab initio quantum-transport calculations. The results show that the on-state current of the p-type device is remarkable when the gate length is greater than 4 nm, which can meet the high performance requirements of the International Technology Roadmap for Semiconductors (ITRS), 2013 version. Moreover, the gate length can be reduced to 3 nm when an underlap (UL) structure is employed in the MOSFET, and the sub-threshold swing, intrinsic delay time and power consumption also perform well. The calculation results reveal that ML MoSi2N4 will be a promising alternative for transistor channel materials in the post-silicon era.

The effective Work-Function of atomic layer deposited TaN thin film using TBTDET precursor and NH3 reactant gas

We investigated the effect of capping metals and post annealing on the effective work function (EWF) of atomic layer deposited (ALD) tantalum nitride (TaN) using a metal oxide semiconductor (MOS) device with HfO2 gate dielectric. The tris(diethylam-ido)(tert-butylimido) tantalum (TBTDET) precursor and ammonia (NH3) were used as the tantalum precursor and the reactant gas, respectively. Increasing ALD TaN thickness leads to higher EWF regardless of the capping metals. When aluminum (Al) is used as the capping metal, the EWF range is 4.06 eV to 4.45 eV, which is suitable for the gate electrode of the n-type device, and for the tungsten (W) capping metal, the EWF range is 4.43 eV to 4.80 eV, acceptable for the gate electrode of the p-type device. These results are attributed that Al causes oxygen-scavenging, resulting in more oxygen vacancies within HfO2, whereas W reacts little with oxygen. The EWF versus ALD TaN thickness dependence of the Al and W capping cases is 55.7 meV/nm and 52.8 meV/nm, respectively. Additional heat treatment further increases EWF further for both cases, which is attributed to the reduction of carbon contents within TaN.

DC and RF analysis of vertical 3D p-type silicon nanotube FET for low power applications

ABSTRACT A vertical p-type 3D silicon nanotube field effect transistor (p-type Si-NTFET) is designed and simulated by using the tool Sentaurus Technology computer-aided design (TCAD). To improve the performance with reduced short channel effects, Si-NTFET device is created with inner and outer gate structures. The performance of the proposed device is analysed in terms of outer gate length. The vertical 3D p-type Si-NTFET gives an on state current (I ON) of −2.084 × 10−3 A/µm, off state current of (I OFF) of −2.457 × 10−12A/µm and subthreshold swing of the p-type Si-NTFET device is 53 mV/dec at V DS of −0.3 V. The obtained I ON/I OFF ratio of the device is 109. The capacitances (C GD, C GG) and the transconductance (g m) and cutoff frequency (f t) of the device are also analysed. The simulated p-type Si-NTFET device has proved that the device is suitable for low-power applications.

Structural, Electronic Band Transition and Optoelectronic Properties of p-Type Transparent Conductive CuCr1–xNixO2 Semiconductor Films

The transparent conductive CuCr1–xNixO2 (0 ≤ x ≤ 8%) films were prepared by sol–gel method with two-step annealing process. The structure, morphology, phonon modes, chemical composition, optical bandgap, and electrical properties were systematically studied. It was found that the crystal quality improves first and then decreases with increasing the Ni content, and the inflection point occurs when the doping content is 2% and all samples have the (00l) preferred orientation. In the visible region, the transmittances of these samples range from 75% to 55% as the Ni dopant increases. On the basis of the theoretical calculation, we are inclined to the view that there are two ways of coexisting electronic transitions. The direct band gap decreases from 3.13 to 3.02 eV, and the indirect band gap decreases from 2.78 to 2.49 eV with increasing Ni content. Transmittance spectra of the CuCrO2 film at the temperatures from 323 to 453 K present the fact that the absorption edge shows a slight redshift, which is due to the lattice thermal expansion and the electron–phonon interaction. Raman spectroscopy shows that Ni doping can substitute the Cr sites and further affect Cu–O bonds, which is caused by oxygen deficiency or a relatively smaller crystallite size. Moreover, it suggested that the nonlinear temperature dependence of phonon frequency and line width is a sign of nonharmonic lattice dynamics. The inherent anharmonic force from the crystal results in energy exchange between harmonic phonon normal modes, thereby promoting thermal balance, and in the lattice. The Cu cations have been confirmed to exist in the valence state of Cu1+, and all doped Ni cations exist in a positive divalent state by XPS. Hall effect measurement shows that the conductivities and carrier concentrations of the doped CuCr1–xNixO2 films can be improved by several orders of magnitude larger than that of undoped CuCrO2. The present work suggests that these well crystallized films without a secondary phase can be applied in future p-type optoelectronic devices.

A Three-Stage Charge Pump With Forward Body Biasing in 28 nm UTBB FD-SOI CMOS

Energy harvesting techniques provide solutions for powering battery-free circuits or even for charging storage elements such as batteries or super capacitors. In this paper a self-starting switched-capacitor approach based on three-stage charge pump that is appropriate to thermoelectric and photo-voltaic energy harvesting, is carried out in a 28 nm ultra-thin buried oxide (UTBB) fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. By taking advantage of the FD-SOI substrate characteristics, the forward-body-biasing (FBB) technique is applied in order to improve switch conductances. In addition, a sizing exploration of standard N-type and flipped-well P-type devices operating as switches is advanced, in order to provide optimum balance between their conductances. Extensive simulation results validate the proper operation of the charge pump at a minimum input voltage of 150 mV, and show a maximum efficiency peak of 63.3% at an input voltage of 350 mV and load a current of 500 nA.

Integration of Si0.7Ge0.3 fin onto a bulk-Si substrate and its P-type FinFET device fabrication

In this study, the integration of a high-mobility Si0.7Ge0.3 fin onto a bulk-Si substrate utilizing a shallow trench isolation (STI) last strategy and its fin field effect transistor (FinFET) device fabrication are investigated. A high-quality Si0.7Ge0.3 fin was first achieved by developing a process of the epitaxial growth of Si0.7Ge0.3, the fin etching of both the Si substrate and the Si0.7Ge0.3, the low-temperature STI densification annealing and the SiN liner. Then, a Si0.7Ge0.3 channel FinFET device was successfully fabricated by employing a newly developed spacer etching process, the annealing of a low temperature source and drain activation, an in-situ O3 passivation process, and an Al2O3/HfO2 bi-layer gate dielectric. As a result, a drive current I on of 331 μA μm−1 under V DS = V GS = −0.8 V was obtained without any strain-induced mobility enhancement technology. Using this bulk FinFET-compatible process, a high I on/I off ratio of ∼5 × 105, an excellent subthreshold slope (SS) of 73 mV decade−1 and a drain induced barrier lowering of 20 mV V−1 were demonstrated. Its excellent SS performance indicates that a good interface quality of the Si0.7Ge0.3 fin is obtained after the fabrication of its FinFET device. The above results confirm that these newly developed processes can provide a potential solution for the integration of high-mobility channels onto a bulk Si substrate and its FinFET device fabrication.

Promising Properties of a Sub-5-nm Monolayer MoSi2N4 Transistor

Two-dimensional (2D) semiconductors have attracted tremendous interests as natural passivation and atomically thin channels that could facilitate continued transistor scaling. However, air-stable 2D semiconductors with high performance were quite elusive. Recently, extremely air-stable MoSi2N4 monolayer had been successfully fabricated [Hong et al., Science 369, 670 (2020)]. To further reveal its potential applications in the sub-5 nm MOSFETs, there is an urgent need to develop integrated circuits. Here we report first-principles quantum transport simulations on the performance limits of n- and p-type sub-5 nm monolayer (ML) MoSi2N4 metal-oxide-semiconductor FETs (MOSFETs). We find that the on-state current in the MoSi2N4 MOSFETs can be effectively manipulated by the length of gate and underlap (UL), as well as the doping concentration. Very strikingly, we also find that the n-type devices the optimized on-state current can reach up to 1390 and 1025 uA/um for the high performance (HP) and low power (LP) applications, respectively, both of which satisfy the International Technology Roadmap for Semiconductors (ITRS) requirements. Whereas, the optimized on-state current can meet the LP application (348 uA/um) for the p-type devices. Finally, we find that the MoSi2N4 MOSFETs have ultra-low subthreshold swing and power delay product, which have potential to realize the high speed and low power consumption devices. Our results show that MoSi2N4 is an ideal 2D channel material for future competitive ultrascaled devices.

Normally-Off p-GaN Gated AlGaN/GaN MIS-HEMTs with ALD-Grown Al2O3/AlN Composite Gate Insulator.

A metal–insulator–semiconductor p-type GaN gate high-electron-mobility transistor (MIS-HEMT) with an Al2O3/AlN gate insulator layer deposited through atomic layer deposition was investigated. A favorable interface was observed between the selected insulator, atomic layer deposition–grown AlN, and GaN. A conventional p-type enhancement-mode GaN device without an Al2O3/AlN layer, known as a Schottky gate (SG) p-GaN HEMT, was also fabricated for comparison. Because of the presence of the Al2O3/AlN layer, the gate leakage and threshold voltage of the MIS-HEMT improved more than those of the SG-HEMT did. Additionally, a high turn-on voltage was obtained. The MIS-HEMT was shown to be reliable with a long lifetime. Hence, growing a high-quality Al2O3/AlN layer in an HEMT can help realize a high-performance enhancement-mode transistor with high stability, a large gate swing region, and high reliability.

Reversing the Polarity of MoS2 with PTFE.

Pristine monolayer molybdenum disulfide (MoS2) demonstrates predominant and persistent n-type semiconducting polarity due to the natural sulfur vacancy, which hinders its electronic and optoelectronic applications in the rich bipolarity area of semiconductors. Current doping strategies in single-layer MoS2 are either too mild to reverse the heavily n-doped polarity or too volatile to create a robust electronic device meeting the requirements of both a long lifetime and compatibility for mass production. Herein, we demonstrate that MoS2 can be transferred onto polytetrafluoroethylene (PTFE), one of the most electronegative substrates. After transfer, the MoS2 photoluminescence exhibits an obvious blueshift from 1.83 to 1.89 eV and a prolonged lifetime, from 0.13 to 3.19 ns. The Fermi level of MoS2 experiences a remarkable 510 meV decrease, transforming its electronic structure into that of a hole-rich p-type semiconductor. Our work reveals a strong p-doping effect and charge transfer between MoS2 and PTFE, shedding light on a new nonvolatile strategy to fabricate p-type MoS2 devices.

Comparison and analysis of Al0.7InAsSb avalanche photodiodes with different background doping polarities

Background doping polarity is a key parameter in the design of numerous electrical and optoelectronic devices. It is especially critical for avalanche photodiodes (APDs). Recently, high-performance APDs have been demonstrated based on the AlInAsSb digital alloy materials system. A critical element of this work was the determination of the background doping polarity of the molecular beam epitaxial grown wafers. In this work, we determine the unintentional background doping polarity of Al0.7InAsSb using the double mesa capacitance-voltage technique. We fabricated two p-i-n Al0.7InAsSb structures: one with p-type background polarity and the other with n-type. The measurements indicate that devices with different background doping polarities show different capacitance relations to the mesa diameters; moreover, the relationship reverses at high voltage in a p-type background device. Subsequent simulations reveal that this reversal is caused by electrical field confinement after the depletion reaches the smaller top mesa. These findings are consistent with reports of reduced surface leakage current in double and triple mesa structures.