Performance Limit of Ultrathin GaAs Transistors.

Abstract

High-electron-mobility group III-V compounds have been regarded as a promising successor to silicon in next-generation field-effect transistors (FETs). Gallium arsenide (GaAs) is an outstanding member of the III-V family due to its advantage of both good n- and p-type device performance. Monolayer (ML) GaAs is the limit form of ultrathin GaAs. Here, a hydrogenated ML GaAs (GaAsH2) FET is simulated by ab initio quantum-transport methods. The n- and p-type ML GaAsH2 metal-oxide-semiconductor FETs (MOSFETs) can well satisfy the on-state current, delay time, power dissipation, and energy-delay product requirements of the International Technology Roadmap for Semiconductors until the gate length is scaled down to 3/4 and 3/5 nm for the high-performance/low-power applications, respectively. Therefore, ultrathin GaAs is a prominent channel candidate for devices in the post-Moore era. The p-type ML GaAsH2 MOSFETs with a 2% uniaxially compressive strain and the unstrained n-type counterparts have symmetrical performance for the high-performance application, making ultrathin GaAs applicable for complementary MOS integrated circuits.