pHEMT Technology Research Articles

A Compact Ku-Band Broadband GaAs Power Amplifier Using an Improved Darlington Power Stage

In this article, a two-stage broadband GaAs power amplifier (PA) is presented, which consists of an improved Darlington power stage and a drive stage. As the most important part of the two-stage PA, the proposed Darlington power stage can simultaneously achieve large bandwidth and watt-level output power. The circuit analysis of the Darlington structure is carried out for large-size transistors. The bandwidth and gain of the Darlington structure are investigated in three cases with source peaking inductor, interconnection inductor, and compensation inductor. A design procedure for the total PA is developed to provide potential guideline. Furthermore, the total PA was fabricated using 0.15- $\mu \text{m}$ GaAs pHEMT technology. The measured maximum gain in the case of a small signal is 25.9 dB, and the 3-dB bandwidth is from 10.7 to 16.7 GHz (43.8% fractional bandwidth). The maximum power of 36 dBm and the maximum power-added efficiency (PAE) of 46.8% are measured at 13 GHz. To the best of our knowledge, the proposed PA exhibits the highest figure of merit (FOM) when compared with the other previously published works.

8-12 GHz pHEMT MMIC Low-Noise Amplifier for 5G and Fiber-Integrated Satellite Applications

The fifth-generation (5G) radio access technology promises to revolutionise integrated earth-space communications applications for ubiquitous, seamless and broadband services. The assigned sub-6 GHz and millimetre-wave 5G frequencies require the sensitivity of the receiver front-end subsystem(s) to detect and amplify the desired signal at a noise floor of less than -90 dBm for a cost-effective infrastructure deployment. This paper presents a broadband monolithic microwave integrated circuit (MMIC) low-noise amplifier (LNA) design based on a 0.15 µm gate length Indium Gallium Arsenide (InGaAs) pseudomorphic high electron mobility transistor (pHEMT) technology for 5G and fiber-integrated satellite communications applications. The designed three-stage 8-12 GHz LNA implements a common-source topology. The MMIC LNA subsystem performance demonstrates an industry-leading in-band gain response of 40 dB; a noise figure of 1.0 dB; and a power dissipation of 43 mW. For a constant bandwidth receiver, the sensitivity changes by approximately 1.5 dB over the operating satellite signal frequency. Similarly, for a variable bandwidth receiver, the sensitivity changes by approximately 1.5 dB over the channel bandwidth. Moreover, the sensitivity margin of the designed LNA is 40 dB and this holds a great promise for real-time radio access component-level reconfiguration applications.

High‐efficiency balanced power amplifier using miniaturized harmonics suppressed coupler

A novel balanced power amplifier (BPA) using compact coupler with rhombus resonators is presented. In this design, a new method is presented to analyze the proposed rhombus-shaped resonator based on the LC equivalent circuit. A new class F power amplifier is designed to improve performances of the BPA. The results show that the performance of the proposed BPA is improved by using the proposed harmonic suppressed coupler at the design structure. The designed BPA operates at 1.25 GHz and delivers 29 dB output power with a gain of 17.9 dB and drain efficiency (DE) of 65.2%. The presented BPA is realized using ATF-34143 transistors in GaAs pHEMT technology and fabricated on the RT/Duroid 5880 substrate with a thickness of 31 mil.

Small-signal modeling and parameter extraction method for a multigate GaAs pHEMT switch

This paper presents an accurate small-signal model for multi-gate GaAs pHEMTs in switching-mode. The extraction method for the proposed model is developed. A 2-gate switch structure is fabricated on a commercial 0.5 μm AlGaAs/GaAs pHEMT technology to verify the proposed model. Excellent agreement has been obtained between the measured and simulated results over a wide frequency range.

A Compact UWB Bandpass Chip Filter on a GaAs Substrate with Modified Chebyshev Structure

Ultra-Wideband (UWB) systems are widely used in low-power, high-speed, high-security short-range wireless communication systems throughout digital homes and offices. In the RF front-end of a UWB system, bandpass filters (BPFs) are used to put through the passband signals and reject the stopband signals. Most UWB BPFs are designed with dielectric materials on circuit boards or LTCC technology. In this paper, a very compact fully integrated UWB chip filter is proposed and designed on a GaAs substrate with nitride as dielectric layers to meet the small size requirement of portable devices for next-generation UWB applications. The filter is constructed with a modified Chebyshev structure. The final filter circuit contains only four inductors instead of six for the conventional Chebyshev filter, which makes the chip more compact and cost effective. The filter is designed and fabricated on a 0.25 μm GaAs pHEMT technology with a chip size of only 0.73 mm × 0.51 mm including the chip edge and scribe line area, while the filter core area is only 0.61 mm × 0.39 mm, including bonding PADs. The measurement results illustrated that the proposed BPF shows a passband covering the frequency range of 3.1–9.0 GHz, the minimum passband insertion loss is only 1.5 dB, the stopband rejection is better than −30 dB throughout frequencies below 2 GHz and above 12 GHz, S11 is less than −16 dB, and S22 is better than −11 dB during the whole passband range. It demonstrated that the proposed filter can be considered as one of the most compact UWB filters.

Bandwidth Improvement of MMIC Single-Pole-Double-Throw Passive HEMT Switches with Radial Stubs in Impedance-Transformation Networks

In this paper, we propose a new configuration for improving the isolation bandwidth of MMIC single-pole-double-throw (SPDT) passive high-electron-mobility transistor (HEMT) switches operating at millimeter frequency range. While the conventional configuration adopted open-stub loading for compensation of the off-state capacitance, radial stubs were introduced in our approach to improve the operational bandwidth of the SPDT switch. Implemented in 0.15 m GaAs pHEMT technology, the proposed configuration exhibited a measured insertion loss of less than 2.5 dB with better than 30 dB isolation level over the frequency range from 33 GHz to 44 GHz. In terms of the bandwidth of operation, the proposed configuration achieved a fractional bandwidth of 28.5% compared to that of 12.3% for the conventional approach. Such superior bandwidth performance is mainly attributed to the less frequency dependent nature of the radial stubs.

An Ultra-Compact On-Chip Reconfigurable Bandpass Filter With Semi-Lumped Topology by Using GaAs pHEMT Technology

A semi-lumped reconfigurable on-chip bandpass filter with GaAs pHEMT technology is presented in this paper. Three order tunable bandpass filter is designed with serial lumped capacitors, parallel resonators, and reconfigurable components. The operating bands are adjusted by field effect transistors and its corresponding gate bias circuits with GaAs technology. The semi-lumped topology, intending to reduce the size of the circuit, is employed to construct the parallel resonators, which are implemented with short-ended stubs and metal-insulator-metal capacitors. The equivalent circuit model is built to interpret the mechanism of the on-chip reconfigurable bandpass filter. Compared with the traditional tunable filters, an ultra-compactness feature and low insertion loss are obtained with the proposed design. The size of the on-chip filter is only 0.8×1.07 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is equivalent to 0.08×0.11 λ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 10 GHz. The presented filter is reconfigurable in two frequency bands, one is centered at 10 GHz with a fraction bandwidth (FBW) of 24.94% and the other is operated at 8.8 GHz with a FBW of 13.35%. The tuning range of the FBW is 30.6%. Good agreements are observed between the simulated and measured S-parameters.

A GaAs Power Detector Design for $C$ -Band Wideband Complex Cross Correlation Measurement

The design and measurement of a power detector circuit based on the 0.15- $\mu \text{m}$ GaAs pHEMT technology and its usage in complex cross correlation measurement are presented in this article. The six-port technology is employed for the calculation of the cross correlation, and the design equations from the requirements of the correlation measurement are provided to guide the power detector design. The relation between the signal-to-noise ratio (SNR) of the correlation results and the load resistor is deduced, which can restrict the resistor value choice for an acceptable SNR. By properly choosing the load resistor and the biasing of the transistor, a power detector circuit is designed with a suppressed output dc voltage variation resulting from the statistic feature of monolithic microwave integrated circuit (MMIC) production. A fabricated detector chip has been mounted onto a printed circuit board and has been characterized. The measurement results show a flat responsivity over 3.5–8 GHz and a 3-nV/ $\sqrt {\mathrm{ Hz}}$ output noise voltage spectrum. The complex cross correlation measurement is implemented using two power detector modules with carefully chosen bias currents. Across the frequency range of 3.5–8 GHz, the measured correlation circles have an amplitude imbalance of 3.5 dB and an axial ratio from 0.85 to 1.15. With an input power of −5 dBm, the measured SNR of the correlator output is above 26 dB.

An $S$ -Band GaAs Multifunction Chip for Transmit/Receive Modules

In this article, a highly integrated $S$ -band prototype multifunction chip (MFC) featuring high integration level, bidirectional operation, reduced number of pads, and optimized power consumption is demonstrated with a GaAs 0.15- $\mu \text{m}$ pHEMT technology. In order to pursue a high integration level, the MFC utilizes four amplifiers, two bidirectional mixers, and compact integrated passive filters. For the sake of power supply pads, the self-biasing technique is adopted with the on-chip power-combining technique. As for the power consumption minimization, when the system voltage is constant, the current reuse technique is selected with optimized transistor size without degradation of the key specifications. The main function for the MFC is to provide double-conversion and gain amplification both in the transmission path and the receiving path on one chip. In transmit mode, the MFC achieves 0-dB gain and 7-dBm $P_{-1\,\mathrm {dB}}$ from 2.6 to 3.2 GHz. The obtained local oscillator (LO)-radio frequency (RF) isolation is better than 50 dB, and the intermediate frequency (IF)-RF isolation is 85 dB. In receive mode, it achieves −5-dB gain with $V_{\mathrm {DD}}$ of the MFC is 5 V. The fabricated MFC occupied 5 mm $\times 5$ mm, which is the largest record area that the process can withstand.

Far-Field-Based Nonlinear Optimization of Millimeter-Wave Active Antenna for 5G Services

This paper presents the design and characterization of millimeter-wave (28/38 GHz), circularly polarized (CP) active antennas, suitable for future 5G services. By augmenting the modeling capabilities of commercially available nonlinear CAD tools, the active antenna design can simultaneously optimize figures of merits for both radiation and nonlinear (NL) performance. The radiating part is computed and optimized layoutwise by means of an artificial neural network (ANN), suitably trained off-line. For the NL design purpose, the harmonic neural network (HNN) of the antenna is subsequently implemented as a standard circuit component, to include the antenna behavior at all the harmonics of its NL regime. This allows avoiding time-consuming electromagnetic (EM)-simulations in the harmonic balance optimization loop. In this way, a well-defined interface between the antenna and the amplifier can be avoided. To demonstrate the effectiveness of the design approach, one active integrated antenna (AIA), consisting of a class AB amplifier feeding a CP patch at 38 GHz, has been fabricated with the standard 0.1- $\mu \text{m}$ AlGaAs-InGaAs pHEMT technology and extensively measured with respect to both the electrical and radiation performances. To reduce fabrication costs, hybrid integration of the antenna and amplifier connection is used, and the antenna is incorporated into the main PCB.

An ultra‐wideband distributed amplifier MMICs based on 0.15‐um GaAs pHEMT technology

AbstractA DC‐30GHz ultra‐wideband distributed amplifier based on the 0.15‐um GaAs process is proposed and characterized. The distributed amplifier has nine power amplifying units with a cascode structure. The measured results show that the amplifier has 16‐dB gain in the frequency range of DC‐30GHz. The output power of 1‐dB compression point is 19 dBm at 10 GHz, and the saturated output power is 25 dBm. The chip size is 3× 1.2 mm.

Schottky Diodes on Heterostructures with Two-Dimensional Electron Gas

The results of studies of the characteristics of contacts with Schottky barriers on a pseudomorphic AlGaAs/InGaAs heterostructure are presented. The Ti-based Schottky diodes were created by a standard pHEMT technology. It is shown that the parameters of the fabricated contacts with Schottky barriers are close to the characteristics of ideal contacts based on aluminum or molybdenum created in the process of molecular beam epitaxy. It is also shown that as compared to the diodes based on AlGaAs homostructures, the measured Schottky barrier height is smaller and the ideality factor is higher in diodes created on pseudomorphic heterostructures. Along with the well-known methods for determining the Schottky-barrier height, we tested a technique based on the measurement of the threshold voltage in diodes with a two-dimensional electron gas.

A Wideband Extended-Dynamic-Range Successive Detection Logarithmic Amplifier Based on 0.15 μm GaAs pHEMT Technology

This paper puts forward an extended-dynamic-range successive detection logarithmic amplifier (SDLA) for [Formula: see text]-band (18–26.5[Formula: see text]GHz) applications. A novel single-transistor power detection unit (PDU) is used instead of a conventional rectifier to effectively improve the dynamic range–bandwidth product of the amplifier. Circuit analysis and mathematical modeling are performed for the proposed PDU and the SDLA, respectively. Transistor level design is carried out for the whole circuit using 0.15[Formula: see text][Formula: see text]m GaAs pseudomorphic high electron mobility transistor (pHEMT) technology. The SDLA presents a wide dynamic range of 75[Formula: see text]dB with a [Formula: see text] 1.5[Formula: see text]dB logarithmic error, over the entire band of interest, and consumes 340[Formula: see text]mW from [Formula: see text] 2.5[Formula: see text]V and –0.8[Formula: see text]V power supplies. All requirements are verified in post-layout simulation using ADS software. Thermal simulation and statistical yield analysis are performed to ensure the robustness of the proposed architecture.

Electronic calibrator MMIC with frequency range up to 50 GHz for vector network analyzers in GaAs pHEMT technology

This paper presents design, simulation and measurements results of electronic calibrator with frequency range up to 50 GHz in GaAs pHEMT technology. MMIC was fabricated by using in-house 0,5 um pHEMT process. Designed MMIC performs SOLT calibration method with additional measures

Resonance gate bias cascode class-E power amplifier in GaAs pHEMT technology

In this paper, switching behavioural of cascode transistor in class-E cascode structure is improved by resonance gate bias (RGB) technique. The proposed technique can be used to increase supply voltage of a cascode class-E power amplifier (PAs) in order to achieve high output power and efficiency. Output power of class-E PAs are limited due to drain–gate stress caused by the switching transient voltages. The RGB technique relaxes the supply voltage limitation due to breakdown voltage (VBD) of the transistor. In addition, reactance compensation components technique is employed to achieve high-power and wide-band class-E PA. To show validity of the proposed RGB technique, two reliable 1-W high-voltage and high-efficiency class-E PAs are fabricated in a 0.25 μm GaAs pseudomorphic high-electron mobility transistor technology. The 1.8 GHz class-E PA achieves 52% power added efficiency (PAE) and 30.6 dBm output power. The designed 2–3 GHz class-E PA has 45% PAE at output power of 30 dBm.

A Seven-Octave Broadband LNA MMIC Using Bandwidth Extension Techniques and Improved Active Load

This paper presents the analysis and design of a novel broadband low-noise amplifier (LNA) with larger than seven-octave bandwidth. To achieve good impedance matching, flat gain, and low noise over larger than seven-octave bandwidth, the combination technique of shunt-resistive feedback, dual inductive-peaking techniques as well as a compact improved active load supporting broadband RF biasing from dc to 20 GHz, is proposed for LNA design. The gain and noise improvement principles of the proposed technique are also analyzed theoretically. Based on the theoretical study, a three-stage LNA with larger than seven-octave bandwidth, i.e. 0.1 to 20 GHz, is designed and verified using a 0.15- $\mu \text{m}$ GaAs pHEMT technology. The LNA experimental results show a high gain of 28.6 dB, good noise figure of 3.1 to 5.8 dB, and output $P_{\mathrm {-1\,\,dB}}$ of 7.8 to 12.7 dBm over the broad frequency range of 0.1 to 20 GHz. The proposed LNA has a compact chip size of only 1.53 mm2 including testing input/output pads.

A Ka-band low power consumption MMIC core chip for T/R modules

This paper presents a Ka-band low power consumption MMIC core chip using commercial 0.15 μm D-mode GaAs pHEMT technology for T/R modules. The core chip consists of two linear gain amplifiers, a SPDT switch, a 5-bit attenuator and a 5-bit phase shifter with a size of 4.8 mm × 2.5 mm. In the receiving mode, the 32–38 GHz core chip results in a gain of 9.0 dB and an output P1dB of –3 dBm. In the transmitting mode, the gain and output P1dB are 11.5 dB and +0 dBm, respectively. The measured rms attenuation error and phase error are 0.7 dB and 3.8°. The power consumption is 150 mW in both work modes. The measured results show that the operating bandwidth, power consumption, gain, rms attenuation error and phase error have been significantly improved compared with the previous reports.

Outside Nominal Operation Analysis and Design Considerations of Inverse-Class-E Power Amplifier

In this paper, design and analysis using analytical expressions for the inverse class-E power amplifier (PA) operating at the outside nominal operation, i.e., class- $\text{E}_{\mathrm{n}}$ PA, is presented. This operation is defined as nonzero current switch (n-ZCS) and nonzero-derivative-current switch (n-ZDCS) conditions. The generalized design equations as a function of design specifications, load resistance, and a given dc-supply voltage are derived. Two degrees of the design freedom achieved thanks to n-ZCS and n-ZDCS that are utilized for the simultaneous satisfaction of design specifications, such as peak-switch-voltage and peak-switch-current along with a given load resistance. The output power capability is affected by n-ZCS and n-ZDCS conditions, which can be obtained in the desired value using the controlled adjustment of introduced deviation parameters. In order to prove the validity of the proposed design methodology, an inverse class-E PA operating in 2 GHz with output power of 23 dBm is implemented in 0.25- $\mu \text{m}$ AlGaAs–InGaAs pHEMT technology. There is a close agreement between the theoretical and simulation results and the measurements of the fabricated prototype PA, which proved the validity of the obtained design expressions.

Analysis and Design of Broadband &lt;italic&gt;LC&lt;/italic&gt;-Ladder FET LNAs Using Noise Match Network

A noise match network for the LC -ladder input network of a broadband inductively source-degenerated common-source (CS) field effect transistor (FET) low-noise amplifier (LNA) is established through noise transformation matrix to derive the noise parameters of a broadband LNA. Analytical formulas for the noise factors of a CS FET LNA with a three-section LC-ladder input network are thus obtained based on the design algorithm of optimal noise and input match developed in this paper. Two 3.7–10.5 GHz two-stage LNAs of the same topology are demonstrated using 0.15- $\mu \text{m}$ pHEMT technology to validate the design methodology. One LNA has all the fully integrated inductors and the other uses two on-chip inductors replaced by two high-Q bondwire inductors for better noise performance. The measurement results show 11-dB power gain with 2.1-dB noise figure for the LNA with the fully integrated inductors and 11-dB power gain with 1.6-dB noise figure for the LNA with two bondwire inductors, respectively.

94‐GHz 360° reflective‐type phase shifter with minimal loss variation using triple‐resonating load technique

This Letter reports a 360° reflective-type phase shifter in 100-nm InGaAs pHEMT technology. A triple-resonating load technique is proposed and the optimum conditions are derived to achieve full 360° phase-shift range and minimise the insertion loss variation. The implemented reflective-type phase shifter achieves a measured phase-shift range of 360° and an insertion loss of 9.0 ± 0.9 dB at 94 GHz. Measured return loss is better than 14 dB across 360° phase-shift range.