P-channel Polysilicon Thin Film Transistors Research Articles

Degradation Characteristics of n- and p-Channel Polycrystalline-Silicon TFTs Under CMOS Inverter Operation

The degradation characteristics of n- and p-channel polysilicon thin-film transistors (TFTs) under circuit operation were investigated by using CMOS inverter circuits consisting of n-channel TFTs with a lightly doped drain (LDD) structure and p-channel TFTs with a single-drain (SD) structure. A new test element made it possible to separately evaluate the degradation characteristics of each type of TFT during CMOS inverter operation. In regard to n-channel LDD TFTs, the device degradation is mainly caused by accumulated dc stress under the condition that the gate voltage is near the threshold voltage and the high drain voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress condition. In p-channel SD TFTs, the device degradation is caused by the mutual interaction between DAHC stress and negative-bias-temperature (NBT) stress. Hole injection due to NBT stress is accelerated by DAHC-stress-induced trapped electrons under inverter-circuit operation. The effect is thus enhanced not only by the increase in the number of hole injections but also by the increase in the number of electron injections. It was found that the device characteristics of p-channel TFTs are more rapidly degraded as the rising time of the input pulse becomes shorter. This degradation is caused by the transient increase in the number of hot electrons, which are generated when holes are emitted from the trap states when the p-channel TFTs are turned off.

Accelerated Negative-Bias Temperature Degradation in Low-Temperature Polycrystalline-Silicon p-Channel TFTs Under Dynamic Stress

The degradation mechanism in p-channel polysilicon thin-film transistors under negative-bias temperature (NBT) stress and pulse stress, which alternates NBT stress and drain-avalanche hot carrier (DAHC) stress, was investigated. An analysis of recovery effects and activation energy suggests that the device degradation under dc-NBT stress is explained by a reaction-diffusion model and limited by hydrogen diffusion. These features are also observed in the case of the device degradation under pulse stress. Pronounced degradation occurs not after DAHC stress application (electron injection) but after NBT stress application (hole injection). NBT stress degradation is locally accelerated after DAHC stress application because the effective gate voltage negatively increases due to trapped electrons during DAHC stress. The trap states and positive charges that were generated by this accelerated NBT stress are considered to be the main cause of device degradation under pulse stress.

Modelling velocity saturation and kink effects in p-channel polysilicon thin-film transistors

Experimental measurements and full-2D numerical simulations show that velocity saturation effects in polysilicon thin-film transistor (TFTs) cannot be neglected in order to obtain a precise modelling of output characteristics. Since full-2D numerical simulations are time consuming and unpractical for circuit simulations, we have developed a new quasi-2D model, that takes into account both velocity saturation effects and the presence of a longitudinal electric field in the Poisson's equation, and includes the effect of parasitic bipolar transistor (PBT) action to reproduce kink effect. The agreement of the quasi-2D model with experimental data from p-channel polysilicon TFTs is very satisfactory even for short channel device, and the presence of a velocity-saturated region with a nearly constant free carrier concentration is reproduced without introducing further assumptions.

Electrical stability in self-aligned p-channel polysilicon thin film transistors

In this work we present a study of the electrical stability of self-aligned p-channel thin film transitor fabricated using excimer laser annealing. The electrical stability was tested performing different bias-temperature stress experiments and we found an increased degradation in devices with large channel width and also for increasing temperatures in the bias-temperature stress performed at zero drain voltage. These results clearly point out to instabilities related to self-heating effects of the devices, showing a substantial increase of the threshold voltage and degradation of the subthreshold region, as well as a transconductance ( G m) increase. From extensive analysis of the phenomenon through numerical simulations, we found that the bias-temperature-stress effects, including G m overshoot, could be perfectly reproduced assuming that degradation is confined in a narrow channel region near the source and/or drain contacts. From the present results we conclude that self-heating triggers some degradation of a spatially limited region of the channel, presumably related to residual damage of the ion-implantation process.

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×1013 el/cm2, a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×1014 el/cm2 was observed.

Annealing temperature effects on the electrical characteristics of p-channel polysilicon thin film transistors

In this work, we studied the effects of different thermal annealing on the electrical characteristics of non-self-aligned low-temperature p-channel polycrystalline silicon (polysilicon) thin film transistors. Different thermal treatments were performed after Al-gate formation at different temperature (200°C, 250°C, 350°C and 450°C) and annealing times. We found that optimal conditions were obtained at 350°C, with transfer characteristics showing a subthreshold slope of 0.5V/dec, field effect mobility >100cm2/Vs and threshold voltage around −3.5V. Hot carrier induced degradation was also analyzed performing bias-stress measurements on devices annealed at 350°C and at different bias stress conditions. The experimental data show that a maximum transconductance degradation is obtained for Vg(stress)−Vt=−4V while bias-stress at Vg=Vt and ∣Vg(stress)∣≫∣Vds(stress)∣ did not produce appreciable changes in both transfer and output characteristics.

Stable p-channel polysilicon thin film transistors fabricated by laser doping technique

In this work we present the electrical characterization of non self-aligned p-channel thin film transistors fabricated by using laser doping technique for source/drain contact formation and gate oxide deposited at room temperature by Electron Cyclotron Resonance Plasma Enhanced Chemical Vapour Deposition. These techniques are suitable for a very low temperature process for TFT fabrication. The output characteristics show a current increase at high drain voltage, (“kink” effect) rather moderate, if compared to self aligned polysilicon TFTs, probably due to the gradual doping profile induced by laser doping process. After bias stress at low gate voltage and high drain voltage condition a strong reduction of kink current has been observed in the output characteristics at high drain voltage, whereas minor changes has been observed in the transfer characteristics. This behaviour is similar to what observed in n-channel Gate Overlapped Thin Film Transistors. In the high gate voltage and high drain voltage bias-stress condition we observed only a rigid shift of the transfer characteristics probably related to charge injection in the gate oxide, while subthreshold slope remains constant.

Effects of Various Hydrogenation Processes on Bias-Stress-Induced Degradation in p-Channel Polysilicon Thin Film Transistors

The bias-stress-induced degradation characteristics of p-channel polysilicon (poly-Si) thin film transistors (TFTs) hydrogenated by plasma, H2 and H2/plasma processes are investigated. It is found that the stress time dependence of the transfer characteristics and the threshold voltage shift is affected by the hydrogenation processes and the quantity of hydrogen in the active channel layer of TFTs. These behaviors are mainly caused by the difference in the generation of defect states, that is, band tail states, deep traps corresponding to dangling bonds at/near the poly-Si/SiO2 interface, and positively charged traps corresponding to Si+ atoms created by H+ ions in the oxide. We propose a model to explain these behaviors.

Mechanisms of Electrical Stress-Induced Degradation in H2/Plasma Hydrogenated n- and p-Channel Polysilicon Thin Film Transistors

The degradation characteristics under various bias stress conditions are systematically investigated in hydrogenated n- and p-channel polysilicon thin film transistors (poly-Si TFTs) with a sidewall spacer. The device characteristics after a relatively long stress in the p-channel TFTs exhibit more serious degradation than those in the n-channel TFTs. Moreover, the stress time dependence of the threshold voltage shift in the former devices shows more complicated behavior than that in the latter. These serious and complicated time-dependent degradation characteristics (induced only in p-channel devices) can be explained by the generation of two defect states in which hydrogen plays an important role: one is positively charged traps that correspond to Si+ atoms generated by the injection of H+ ions into the gate oxide near the source and appear after a certain stress time. The other is deep traps that correspond to dangling bonds generated by the dissociation of Si–H bonds at/near the interface near the source and appear after a long stress time.

Stability of Non-Hydrogenated and Hydrogenated P-Channel Polycrystalline Silicon Thin-Film Transistors

ABSTRACTThe effects of high gate voltage Vg stress on the stability of non-hydrogenated and hydrogenated short p-channel polysilicon thin-film transistors (TFTs) are investigated for operation in the saturation region. The degradation mechanisms were identified from the evolution with stress time of the static device parameters. In non-hydrogenated TFTs, transconductance overshoot and a turnover behavior in the threshold voltage were observed. The results indicate that hot-electron trapping near the drain dominates in the initial stages of stress and channel holes are injected into the gate oxide followed by interface states generation as the stress proceeds further. In hydrogenated TFTs, first an effective shortening of the channel length is observed due to trapping of hot-electrons. As the stress proceeds further, donor-type interface states are generated and the electric field near the drain increases due to built-up of positive charge resulted from trapping of hot-holes in these states.

Mechanism of device instability for unhydrogenatedpolysilicon TFTs under off-state stress

The effects of off-state stress (Vgs = 0 V,Vds = 0 to -20 V) on unhydrogenated p-channelpolysilicon thin-film transistors (TFTs) were studied.It was observed that the post-stressed subthreshold swing isfirst improved due to the annealing effect from the interactionof tunnelling electrons and captured holes. As the stress timeincreases or as the stress bias increases, the generation oftraps caused by tunnelling electrons will cancel out theannealing effect and then degrade the subthreshold swing. Inaddition, the trapping of tunnelling electrons in the gate oxidecauses a shift of threshold voltage. However, improving thequality of the gate oxide interface by oxidation of the channelpolysilicon on submicrometre bottom-gate TFTs can reduce theimpact of the off-state stress.

Dimensional Effects on the Drain Current of N- and P-Channel Polycrystalline Silicon Thin Film Transistors

N-channel and p-channel polysilicon thin film transistors (poly-Si TFTs) with different geometries were fabricated and characterized to study the interactive effects of active channel area on drain current. We find that for both non-passivated and passivated p-TFTs, since no avalanche multiplication is involved, the drain current is increased with reduced active channel area due to the reduction of grain-boundary trap density. In contrast, a somewhat unexpected trap dependence of the kink effect is observed in n-TFTs. Consequently, the dependence of active channel area on drain current differs between non-passivated n-TFTs with large trap density and passivated n-TFTs with small trap density.

A short-channel DC SPICE model for polysilicon thin-film transistors including temperature effects

A semi-empirical analytical model for the DC characteristics of both n- and p-channel polysilicon thin-film transistors is described. The model is suitable for implementation in a SPICE circuit simulator. Our semi-empirical approach results in a physically based model with a minimum of parameters, which are readily related to the device structure and fabrication process. The intrinsic DC model describes all four regimes of operation: leakage, subthreshold, above threshold, and kink. The effects of temperature and channel length are also included in the short-channel model.

A new method for the determination of the channel length reduction in polysilicon thin film transistors (TFTs)

The accurate knowledge of the effective channel length in a polysilicon thin film transistor (TFT) is of great importance. The reduction Δ L of the channel length is due to lateral diffusion from the source and drain contacts into the gate region. The usual method for determining Δ L is based on plotting the straight line 1/ I D versus length mask L m in the linear region and extrapolating the straight line to intersect the x-axis. We show that this method is approximate and leads to an underestimation of the reduction channel length due to the existence of the access resistance. We propose an alternative method based on the saturation current I Dsat using the 1/ I Dsat versus L m plots. We show that this method is more accurate especially when the access resistance of the device is important. The extracted parameters Δ L for n- and p-channel polysilicon TFTs are more compatible with the device performance.

High-performance EEPROMs using N- and P-channel polysilicon thin-film transistors with electron cyclotron resonance N2O-plasma oxide

High-performance EEPROMs using n- and p-channel polysilicon thin-film transistors (poly-Si TFTs) with electron cyclotron resonance (ECR) N/sub 2/O-plasma oxide have been demonstrated. Both programming and erasing were accomplished by Fowler-Nordheim (F-N) tunneling within 1 ms regardless of programming and erasing voltages. The poly-Si TFT EEPROMs have a threshold voltage shift of 4 V between programmed and erased states; furthermore, they maintain a large threshold voltage shift of 2.5 V after 1/spl times/10/sup 5/ program and erase cycles. This is attributed to the excellent charge-to-breakdown (Qbd) up to 10 C/cm/sup 2/ of ECR N/sub 2/O-plasma oxide.

Stability of short-channel P-channel polysilicon thin-film transistors with ECR N2O-plasma gate oxide

Stability of hydrogenated short-channel (/spl les/3 /spl mu/m) p-channel poly-Si TFT's with very thin (12 nm) electron cyclotron resonance N/sub 2/O plasma gate oxide is investigated. The fabricated poly-Si TFT's with gate length not less than 2 /spl mu/m show excellent stability characteristics of less than 0.1 V in the threshold voltage shift and less than 3% in the percent change of transconductance after harsh electrical stresses. In a small |V/sub G/| stress, an effective shortening of channel length is observed due to trapping of hot-electrons and the minimum leakage current is decreased. However, a large |V/sub G/| stress causes more degradation on the subthreshold slope and minimum leakage current due to trapping of hot-holes.

Stability analysis and robust design of polysilicon TFT load 4M SRAM cell by statistical method

Advances in high-density static RAM (SRAM) technology have been focused primarily on the application of p-channel polysilicon (poly-Si) thin film transistors (TFTs) as memory cell loads. The penalty, however, is that the electrical characteristics of poly-Si TFTs, such as on-current (Ion), off-current (Ioff), subthreshold slope (s) and threshold voltage (Vth), have large variations, a problem which becomes much more serious as the device size is reduced. In this paper we model the relation between SRAM stability and variations in poly-Si TFT characteristics by a statistical method. From our model it is found that grain boundary traps play a more important role than any other parameter. The trap density should be uniform and this requirement becomes severe as the operating voltage is scaled down. It is, however, very difficult to control the grain boundary characteristics of poly-Si TFTs. We propose a robust design method as an indirect but cost-effective solution to parameter fluctuation, based on the Taguchi method of off-line quality control, and assure that the output performance is enhanced without varying the fabrication conditions. © 1998 John Wiley & Sons, Ltd.

Threshold voltage, field effect mobility, and gate-to-channel capacitance in polysilicon TFTs

Based on experimental and theoretical studies of n- and p-channel polysilicon thin film transistors with gate W/L ratios from 0.3 to 3.3, we have demonstrated that the threshold voltage extracted from gate to channel capacitance data results in field effect mobility parameters which are independent of device geometry. The parameters extracted using this V/sub t/ allow us to reproduce the I-V characteristics of the n- and p channel TFTs over wide ranges of bias voltages and gate sizes. The C/sub gc/-V/sub GS/ characteristics of polysilicon TFTs are strongly affected by the trapping and de-trapping of carriers. As a result, the measured C/sub gc/ characteristic is a function of measurement frequency and gate length. However, we demonstrate that to the first order, the frequency dispersion of the C/sub gc/ curve can be related to the effective carrier transit time determined using the V/sub GS/ dependent field effect mobility.

Mechanism of device degradation in n- and p-channel polysilicon TFTs by electrical stressing

The effects of electrical stress on hydrogenated n- and p-channel polysilicon thin-film transistors are discussed. The on-state caused the most significant degradation, whereas off-state and accumulation conditions resulted in negligible degradation. The on-state stress degraded the threshold voltage, trap state density, and subthreshold sharpness of both n- and p-channel devices toward perhydrogenated values, and the rates of degradation increased with stressing biases. The field-effect mobility and leakage current, however, were not degraded by stressing. The mechanism of device degradation may be attributed to the metastable creation of midgap states within the polysilicon channel, as opposed to gate dielectric charge trapping or interface state generation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>