P-channel MOS Research Articles

High-Voltage p-Channel Level Shifter Using Charge-Controlled Self-Isolation Structure

In this paper, we report an area-effective 600 V p-channel level shifter using a self-isolation structure without the degradation of blocking capability for the first time. To prevent the degradation of high-voltage isolation performance, the charge in a double reduced surface electric field (RESURF) structure is controlled at the border region between a high-voltage p-channel metal oxide semiconductor field effect transistor (MOSFET) and a high-voltage isolation region. Because of a divided p-offset region in the drift region of the high-voltage p-channel MOSFET and the high-voltage isolation region, parasitic current to the ground (GND) terminal through the isolation region can be ignored. By using the new high-voltage p-channel level shifter, a 400 V level shift operation is confirmed.

Low-Threshold-Voltage HfOxN p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Partially Silicided Platinum Gate Electrode

HfOxN p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) with a low threshold voltage (|Vth|) were successfully fabricated using a partially silicided (PASI) platinum gate electrode for scaled complementary MOS (CMOS). The PASI platinum (PASI-PtSi) gate electrode is composed of a monoclinic-Pt3Si phase in the vicinity of a HfOxN dielectric. The reduced silicon content of the PASI gate electrodes is effective in suppressing the Fermi-level pinning on the Hf-based gate dielectrics which induces a significant |Vth| shift in p-channel MOSFETs. It is shown that the |Vth| of HfOxN p-channel MOSFETs with the PASI-PtSi gate electrode is sufficiently low and applicable to low-standby-power devices. The mobility of the holes at 0.8 MV/cm is as high as about 90% of the universal mobility. It is concluded that the PASI technology in which the gate electrode has a reduced silicon content is useful for scaled CMOSs.

A Simple Negative Bias Temperature Instability Characterization Methodology to Minimize the Immediate Recovery Effect during Measurement

Negative bias temperature instability (NBTI) degradation of p-channel metal–oxide–semiconductor field effect transistors ( p-MOSFETs) is significantly underestimated by using the conventional characterization techniques due to a severe NBTI recovery during the measurements. In this work, a simple characterization method based on the single-point measurement of the saturated drain current is proposed to minimize the unwanted recovery effect. This method is accurate as is proven by a carefully-designed experiment. With this new proposed method, the measurement time is reduced to tens of milliseconds. This method gives a closer-to-real threshold voltage shift, and yields a more reliable power-law factor and thus a more realistic NBTI picture.

Evidence of Deep Energy States from Low Temperature Measurements and Its Role in Charge Trapping in Metal Gate/Hf-Silicate Gate Stacks

Pre-existing electron and hole trap energy levels, lying deep within the bulk high-k bandgap, are experimentally observed from low temperature measurements for the first time in metal organic chemical vapor deposited (MOCVD) TiN/HfSixOy based gate stacks. Their role in trapping under constant voltage and substrate hot hole stress conditions is investigated. Mixed degradation due to both electron and hole trapping in the deep pre-existing bulk traps, which induces a turn-around effect in flatband voltage shift (DVFB), is observed for n-channel MOS capacitors under gate injection. Bulk hole trap generation, which causes DVFB to follow tn power law dependence, is observed for p+-ringed p-channel MOS capacitors under substrate hot hole injection. Activation energies of the stress induced traps and pre-existing deep defects are experimentally found to be different.

Influences of Annealing Temperature on Characteristics of Ge p-Channel Metal Oxide Semiconductor Field Effect Transistors with ZrO2 Gate Dielectrics

The dependence of gate leakage current and p+/n-junction characteristics on annealing temperature is investigated comprehensively in order to obtain good electrical characteristics of Ge p-channel metal oxide semiconductor field effect transistors (p-MOSFETs) with ZrO2 gate dielectrics. The upper limit of annealing temperature is restricted to 500 °C to preserve low gate leakage. Gate leakage current remains low even after Ge incorporation into ZrO2, because ZrO2/Ge gate stacks retain their band alignment to as high as 500 °C. The degradation of gate leakage at the high temperature of 700 °C is due to the emergence of void regions near the interface in the Ge substrate. On the other hand, the lower limit of the annealing temperature is restricted to 400 °C in order to activate dopant boron sufficiently. Good rectifying diode characteristics lead to promising p-MOSFET performance, such as an S-factor of 80 mV/decade. The effective hole mobility of the ZrO2/Ge gate stack without an intentional interfacial layer after annealing at the optimized temperature is as high as 100 cm2/(V·s).

Probing Nanoscale Local Lattice Strains in Advanced Si CMOS Devices by CBED: A Tutorial with Recent Results

The experimental methodology to characterize the nanoscale local lattice strain in advanced Si CMOS devices by using Focused Ion Beam (FIB) system and Convergent Beam Electron Diffraction (CBED) is discussed. Through both high spatial resolution of Transmission Electron Microscopy (TEM) and high strain sensitivity of the CBED technique, compressive lattice strains in the order of 0.001 from the nanoscale Si PMOS channel region are detected. The one-dimensional quantitative strain-mapping is performed by obtaining and simulating high quality CBED patterns with different zone axes such as <230> and <340>.

Investigation and Modeling of Stress Interactions on 90 nm Silicon on Insulator Complementary Metal Oxide Semiconductor by Various Mobility Enhancement Approaches

The interactions of shallow trench isolation (STI) stress and various mobility enhancement approaches in silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) have been systematically studied. Strong interactions between STI stress and contact etch stop layer (CESL) stress on channel mobility were observed which was attributed to the amplification of CESL channel tensile stress with length of diffusion (LOD) reduction. In this work, an almost completely reversed P-channel metal oxide semiconductor field-effect transistor (PMOSFET) mobility-LOD trend in both <110 >/(100) and <100 >/(100) oriented SOI wafers was found, which is caused by the reversed polarity of piezoresistance coefficients. On the other hand, charge pumping leakage was enhanced by the post-gate oxide stress (CESL stress) only, and was not affected by any stress applied prior to the gate oxidation step (STI stress).

Highly and Variably Sensitive Complementary Metal Oxide Semiconductor Active Pixel Sensor Using P-Channel Metal Oxide Semiconductor Field Effect Transistor-Type Photodetector with Transfer Gate

In this paper, a new sensor using a p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with a transfer gate has been designed and fabricated by a 0.35 µm standard complementary metal oxide semiconductor (CMOS) process. The photodetector is composed of a floating gate connected to an n-well and a transfer gate. The transfer gate controls photocurrent flow by controlling the barrier for holes in the PMOSFET-type photodetector. The designed photodetector has similar IDS–VDS characteristics to a conventional PMOSFET when the incident light power instead of the gate voltage is varied. A unit pixel that uses this photodetector consists of a PMOSFET-type photodetector with a transfer gate and four n-channel metal oxide semiconductor field effect transistors (NMOSFETs). Its area is 7.2 ×8.1 µm2. It is confirmed that this photodetector, with a high and variable level of sensitivity, could be applied to an image acquisition system at a low illumination level.

Device Characteristics and Aggravated Negative Bias Temperature Instability in p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Uniaxial Compressive Strain

P-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) featuring poly-SiGe gates and compressive strain channels were investigated. The compressive strain in the channel was deliberately induced in this study by a plasma-enhanced chemical vapor deposition (PECVD) silicon nitride (SiN) capping layer over the gate. Our results indicate for the first time that, while strain channel engineering serves as an effective method to enhance drive current for scaled complementary metal–oxide–semiconductor (CMOS) devices consistent with literature reports, it also simultaneously aggravates the negative bias temperature instability (NBTI) of scaled devices. The aggravated NBTI behavior is ascribed to a higher amount of hydrogen incorporation during SiN deposition as well as a higher strain energy stored in the channel. Saturation phenomena in the shift of threshold voltage and generation of interface states are observed at high stress temperatures and long stress times. Moreover, transconductance degradation in devices with SiN capping is greatly aggravated under high temperature stress.

Piezo-FET Stress-Sensor Arrays for Wire-Bonding Characterization

This paper reports the design, fabrication, and characterization of a two-dimensional stress-sensor array based on a stress-sensor element exploiting the transverse pseudo-Hall effect in metal-oxide-semiconductor (MOS) field effect transistors (FET). P-channel MOS (PMOS) devices were integrated in a 4/spl times/4 stress sensor array with a total area of 120/spl times/120 /spl mu/m/sup 2/. The individual elements of the array are sensitive to the local shear stress in the chip plane. They are selected using a CMOS integrated digital decoder and transmission gates. The new array was characterized using a commercial ball-wedge wire bonding tool and was used for the in situ monitoring of the bonding process. The spatially resolved measurement of the stress distribution underneath and close to a bond pad during the bond wire touch-down is demonstrated. The array is able to resolve variations in the touch-down position of 10 /spl mu/m. The time of 1.6 ms for acquisition of a full frame is currently limited by the experimental setup. To monitor the stress distribution during the bonding process, an aluminum covered stress sensor array similar to a standard bond pad was used. The successful bond formation between a gold ball and the metal bond pad was observed. The bond formation becomes evident as a characteristic, concentrated stress profile with large peak value appearing within 20 ms. The maximum stresses underneath the successfully bonded area exceeds stress levels in unbonded sensor locations by a factor of up to 60.

Strain-induced changes in the gate tunneling currents in p-channel metal–oxide–semiconductor field-effect transistors

Changes in the direct gate tunneling current are measured for strained p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) on (100) wafers for uniaxial and biaxial stress. Decreases/increases in the gate tunneling current for various stresses primarily result from repopulation into a subband with a larger/smaller out-of-plane effective mass. Strain-induced changes in the valence band offset between Si and SiO2 are also important but play a secondary role. Hole tunneling current is found to decrease for biaxial and uniaxial compressive stress and increase for biaxial tensile stress. The hole tunneling data is modeled using k∙p self-consistent solution to Poisson and Schrödinger’s equation, and a transfer matrix method.

Effect of Spacer Scaling on PMOS Transistors

AbstractOur observation is that both the on-current and off-current of state-of-the-art p-channel MOS transistors tend to become larger when the L-shaped spacer becomes smaller due to two different mechanisms: a decrease in the effective channel length Leff (Mechanism A) and a decrease in the series resistance (Mechanism B). In our analysis, we use drain induced barrier lowering (DIBL) as a measure of Leff and we assume that there is a linear relationship between the on-current, the logarithm of the off current and DIBL. Our assumption is supported by our theoretical derivations.

Radiation-induced off-state leakage current in commercial power MOSFETs

The total dose hardness of several commercial power MOSFET technologies is examined. After exposure to 20 krad(SiO/sub 2/) most of the n- and p-channel devices examined in this work show substantial (2 to 6 orders of magnitude) increases in off-state leakage current. For the n-channel devices, the increase in radiation-induced leakage current follows standard behavior for moderately thick gate oxides, i.e., the increase in leakage current is dominated by large negative threshold voltage shifts, which cause the transistor to be partially on even when no bias is applied to the gate electrode. N-channel devices biased during irradiation show a significantly larger leakage current increase than grounded devices. The increase in leakage current for the p-channel devices, however, was unexpected. For the p-channel devices, it is shown using electrical characterization and simulation that the radiation-induced leakage current increase is related to an increase in the reverse bias leakage characteristics of the gated diode which is formed by the drain epitaxial layer and the body. This mechanism does not significantly contribute to radiation-induced leakage current in typical p-channel MOS transistors. The p-channel leakage current increase is nearly identical for both biased and grounded irradiations and therefore has serious implications for long duration missions since even devices which are usually powered off could show significant degradation and potentially fail.

Improvements on Electrical Characteristics of p-Channel Metal–Oxide–Semiconductor Field Effect Transistors with HfO2 Gate Stacks by Post Deposition N2O Plasma Treatment

In this work, we found that employing a post deposition N2O plasma treatment following the deposition of HfO2 film can effectively improve the electrical characteristics of p-type channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) with a HfO2 gate stack in terms of lower gate leakage current, lower interface state density, superior subthreshold swing, higher normalized transconductance and enhanced driving current even though it had led to a slightly higher equivalent oxide thickness (EOT) value of the HfO2 gate stack by around 0.3 nm. In order to clarify the attributes of the improvements, we used charge pumping (CP) measurement to analyze the densities of interface states and bulk traps in the HfO2 gate stacks. The improvements are then ascribed to the higher interface quality offered by the post deposition N2O plasma treatment. Moreover, we found that to more accurately estimate the bulk traps from the CP measurement, the leakage should be taken into account especially at low frequencies. Finally, it was found that the levels of the bulk traps and interface states can be reduced by the N2O plasma treatment, which also helps significantly eliminate the degradation of the gate stack during the subsequent voltage stress.

The impact of non-uniform channel layer growth on device characteristics in state of the Art Si/SiGe/Si p-metal oxide semiconductor field effect transistors

In this study we have highlighted the effect of non-uniform channel layer growth by the direct correlation of the microstructure and electrical characteristics in state-of-the-art pseudomorphic Si/SiGe p-channel metal oxide semiconductor field effect transistor devices fabricated on Si. Two nominally identical sets of devices from adjacent locations of the same wafer were found to have radically different distributions in gate threshold voltages. Due to the close proximity and narrow gate length of the devices, focused ion beam milling was used to prepare a number of thin cross-sections from each of the two regions for subsequent analysis using transmission electron microscopy. It was found that devices from the region giving a very narrow range of gate threshold voltages exhibited a uniform microstructure in general agreement with the intended growth parameters. However, in the second region, which showed a large spread in the gate threshold voltages, profound anomalies in the microstructure were observed. These anomalies consisted of fluctuations in the quality and thickness of the SiGe strained layers. The non-uniform growth of the strained SiGe layer clearly accounted for the poorly controlled threshold voltages of these devices. The results emphasize the importance of good layer growth uniformity to ensure optimum device yield.

Enhanced Hot-Hole Induced Degradation of Strained p-Channel Metal Oxide Semiconductor Transistors in Complementary Metal Oxide Semiconductor Technology with 2.0 nm Gate Oxide

The effects of process-induced strain silicon (PSS) technology on hot-hole induced degradation of p-channel metal oxide semiconductor (PMOS) transistors using 2.0 nm ultra-thin nitrided gate oxides will be reported. An understanding of the effects of strain on hot-hole induced degradation will be very important for sub-65 nm complementary MOS (CMOS) technology since PSS technology was said to be a preferred approach to strain transistors. It was discovered that as source drain diffusion length (Lov) decreased, which then gave rise to high compressive strain (HCS) in the channel region of the PMOS transistor, hot-hole induced degradation was enhanced. The improved direct-current current–voltage (IDCIV) method, which allows us to characterize both interface traps (Nit) and oxide charge traps (Not) generation, suggested that no additional interface trap (ΔNit) generation was created when the strain profile of the channel was changed. However, it was observed that positive charge trappings or slow states was enhanced in HCS PMOS transistors which would lead to enhanced hot hole induced degradation after long term stressing.

Detection of Streptavidin-Biotin Protein Complexes Using Three-Dimensional MOSFET in the Si Micro-Fluidic Channel

To detect the electrical reaction characteristics of streptavidin-biotin protein complexes, a three-dimensional (3-D) p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type biosensor was fabricated in the convex corner of a micro-fluidic channel by tetramethyl ammonium hydroxide (TMAH) anisotropic etching. Au, which has a chemical affinity with thiol, was used as the gate metal for immobilizing a self-assembled monolayer (SAM). The SAM was used to immobilize streptavidin. The hydroxyl group of SAM was bound with the amine group of streptavidin. After that, streptavidin and biotin were bound by their high affinity (Ka∼1015 Mol-1). The measurements were performed in phosphate-buffered saline (PBS; pH 6.4, 20 mM) solution. Ag/AgCl was used as the reference electrode. The bindings of SAM, streptavidin and biotin caused a variation in the drain current of the 3-D MOSFET. To verify the interaction among the SAM, streptavidin and biotin, surface plasmon resonance (SPR) measurement was performed.

Reliability of Strained SiGe Channel p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Ultra-Thin (EOT=3.1 nm) N2O-Annealed SiN Gate Dielectric

The p-channel metal–oxide–semiconductor field-effect transistor (pMOSFET) with 50-nm-thick Si0.85Ge0.15 channel and ultra-thin (EOT=3.1 nm) N2O-annealed SiN gate dielectric has been shown to have well-performing on/off and output characteristics. Several methodologies for the device reliability characterization, such as stress-induced-leakage-current (SILC), drain-avalanche-hot-carrier (DAHC) injection, channel hot-carrier (CHC) injection and negative-bias-temperature-instability (NBTI), have been used and the results were compared. In terms of the long-term degradation, the excellent quality of the N2O-annealed SiN gate dielectric can be firmly obtained because only negligible degradations have been found after stressing no matter which technique was employed. Even so, the experimental results have been compared and we found that the HC degradation is worse than the NBTI degradation and the channel-hot-carrier (CHC) stressing is the worst case for all kinds of reliability testing. Meanwhile, we have also verified that the interface state generation is the dominant mechanism responsible for the HC-induced degradation while the electron trapping dominates the device degradation for the NBTI stressing.

Atomistic analysis of the evolution of boron activation during annealing in crystalline and preamorphized silicon

We use kinetic nonlattice Monte Carlo atomistic simulations to investigate the physical mechanisms for boron cluster formation and dissolution in complementary metal-oxide semiconductor (MOS) processing, and the role of Si interstitials in the different processes. For this purpose, B implants in crystalline Si as well as B implants in preamorphized Si are analyzed. For subamorphizing B implants, a high concentration of Si interstitials overlaps with the B profile and this causes a very quick B deactivation for both low- and high-dose B implants. For B implants in preamorphized silicon, B is activated during the regrowth of the amorphous layer if the B concentration is lower than 1020cm−3 and remains active upon annealing. However, if B concentrations higher than 1020cm−3 are present, as occurs in the formation of extensions in p-channel MOS transistors, B atoms are not completely activated during the regrowth. Moreover, the injection of Si interstitials from the end-of-range defects leads to additional B deactivation in the regrown layer during subsequent annealing. If the end-of-range defects overlap with a B profile, even of relatively low concentration, as it occurs for B pockets in n-channel MOS transistors, very quick and local B deactivation occurs in the high Si-interstitial concentration region.

Properties of Ta–Mo alloy gate electrode for n-MOSFET

As complementary metal oxide semiconductor (CMOS) devices are scaled beyond the 50-nm gate length node, the effective oxide thickness must be below 10 A to reduce short-channel effect and to improve device performance. Polysilicon has been extensively employed as a gate electrode, however, it has recently shown to suffer from instability on high-K dielectrics [1]. In addition, the inversion oxide thickness is increased by about 3–5 A due to polysilicon gate depletion [2]. Based on the above reasons, the investigation of metal gates is critical for scaling of advanced gate stacks [3]. Metal gate electrodes must have suitable work function, process compatibility and thermal/chemical interface stability with underlying gate dielectrics. In order to replace the polysilicon gate while maintaining the proper threshold voltage, work functions of the metal gates for n-channel MOS (NMOS) and p-channel MOS (PMOS) must be close to those of n+ and p+ doped polysilicon, which are close to 4 and 5 eV, respectively [4]. Metals with mid-gap work functions are known to be unsuitable for advanced CMOS devices due to severely degraded short channel characteristics [5]. While several thermally stable metals have been reported as possible gate electrodes for PMOS devices [6], metals having NMOS compatible work function typically suffer from thermal instability. Their high affinity towards oxygen promotes the reduction of the underlying dielectric and the formation of a metal oxide layer [7]. Binary metal alloys have been recently reported [6] and may provide a possible route for NMOS electrodes. In this work, we have investigated the electrical/material properties and thermal stability of a novel binary metal alloy, Ta–Mo, for NMOS gate electrode. Field oxide of 3500 A was grown to define active area on (100) p-type silicon substrate. The gate dielectric was 100 A SiO2 which was thermally grown at 900 . The binary metal alloys were deposited using a UHVPVD sputtering tool with a base pressure of 3 × 10−9 Torr. Sputtering was performed using a Ta target (purity of 99.5%) and a Mo target (purity of 99.95%). As shown