Oxide Transistors Research Articles

Performance investigation of low-power flexible n-ZnO/p-CuO/n-ZnO heterojunction bipolar transistor: Simulation study

Oxide semiconductor-based heterojunction bipolar transistors are widely applicable in flexible, printable, and cost-effective circuit applications. Among earth-abundant metal oxides, zinc oxide and copper oxide inherently show n-type and p-type characteristics, respectively, and their electronic properties can be easily modified during the fabrication process. Accordingly, a planar-type HBT can be achieved by low-temperature growth of the metal-oxide layers on a flexible substrate without the need for further sophisticated processes. In this paper, a double heterojunction bipolar transistor (DHBT) comprised of ZnO layers serving as the emitter and collector regions, along with the CuO layer functioning as the base area is presented. Simulation results demonstrate that the proposed all-metal oxide transistor based on p-CuO/n-ZnO heterojunction enjoys low power consumption owing to the low threshold voltage. High-frequency characterization and DC analysis of the proposed NPN configuration are carried out using the ATLAS/SILVACO package. Our findings reveal that at the base-emitter voltage of 0.55 V, the current gain factor of the device reaches 155, which is larger than those reported in the literature. Furthermore, an ideality factor at the base-emitter voltage of 0.7 V was obtained for the collector-base and emitter-base junctions equal to 1.5 and 1.2, respectively.

Giant Resistive Switching and Lattice Modulation at Full Temperature Range in a Sr‐Doped Nickelate Oxide Transistor

AbstractHow to promote the resistance switching ratio, enlarge the operating temperature range and accelerate the switching speed is at the forefront of ionic gating electronics. Usually, most attention has been paid to materials with metal‐to‐insulator transition (MIT), e.g., VO2 and SmNiO3. Here, Sr‐doped nickelate (Nd0.8Sr0.2NiO3) films which do not exhibit MIT are used for electric field control of H‐doping and to detect the variation of resistance, lattice, and electronic structures. The experimental results directly show a giant resistive switching by more than 105 at the full temperature range (2 K–300 K) and lattice modulation by 3.4%. More importantly, much faster switching speeds can be achieved in Nd0.8Sr0.2NiO3 devices than in nondoped NdNiO3 ones. Such high switching performance is demonstrated to arise from strongly suppressed Ni–O hybridization after H doping. The results of this study provide a new material paradigm for developing energy‐efficient neuromorphic computing. Further, the doping effect on device performance also suggests a novel approach to develop correlated perovskite oxide transistors in order to fulfill practical applications.

Enhanced Stability of Solution-Processed Indium–Zinc–Tin–Oxide Transistors by Tantalum Cation Doping

Highly stable metal oxide thin film transistors (TFTs) are required in high-resolution displays and sensors. Here, we adopt a tantalum cation (Ta5+) doping method to improve the stability of zinc–tin–oxide (ZnSnO) TFTs. The results show that Ta5+-doped TaZnSnO TFT with 1 mol% concentration exhibits excellent stability. Compared with the undoped device, the oxygen vacancy defects of TaZnSnO thin films reduce from 38.05% to 18.70%, and the threshold voltage shift (ΔVth) reduces from 2.36 to 0.71 V under positive bias stress. We attribute the improved stability to the effective suppression of the oxygen vacancy defects, which is confirmed by the XPS results. In addition, we also prepared TaInZnSnO TFT devices with 1 mol% Ta5+ doping concentration. Compared with the 1 mol% Ta5+-doped TaZnSnO TFTs, the μ increases two-fold from 0.12 to 0.24 cm2/Vs, and the Vth decreases from 2.29 to 0.76 V in 1 mol% Ta5+-doped TaInZnSnO TFT with an In:Zn:Sn ratio of 4:4:3, while the device remains highly stable with a ΔVth of only 0.90 V. The injection of Ta5+ provides a novel strategy for the enhancement of the stability in ZnSnO-based TFTs.

Solution processed rare-earth doped high-k dielectrics for low-power IGZO transistors

Low-power metal oxide transistors are highly required in displays, logic circuit and sensors. High quality gate dielectrics with the properties of high dielectric constant, smooth surface, and excellent insulating performance are critical to realize the above mentioned transistors. In this work, we present a universal strategy by using rare-earth (RE) elements (Y, Er and Yb) as dopants to improve the dielectric properties of zirconia film for low-power transistors. Additionally, all the dielectric films are prepared by solution process, which is compatible with low-cost and large-area manufacturing technology. The leakage current densities of zirconia films decrease from 1.27 × 10−5 A/cm2 to 2.8 × 10−7 A/cm2, 6.6 × 10 − 7 A/cm2, and 4.3 × 10−7 A/cm2 by doping a small amount of Y, Er, and Yb in zirconia films, respectively. Furthermore, bottom-gate top-contact indium-gallium-zinc oxide (IGZO) transistors with RE-doped zirconia dielectrics show one order improved current on/off (∼104) ratio and achieve one order improvement in mobility (3.11, 2.85, 2.75 cm2V−1S−1 for Y-, Er-, Yb-doped devices respectively) compared with that of pure zirconia film based devices (0.30 cm2V−1S−1). Moreover, the subthreshold swing (SS) of TFTs based on RE-doped and undoped ZrO2 dielectric films are calculated (0.2, 0.36, 0.21 V/dec for Y-, Er-, Yb-doped devices respectively, and 0.51 V/dec for undoped devices) This study demonstrates the validity of RE ions as dopants in gate dielectrics to achieve high-performance low-power metal oxide transistors.

Aqueous electrolyte-gated solution-processed metal oxide transistors for direct cellular interfaces.

Biocompatible field-effect-transistor-based biosensors have drawn attention for the development of next-generation human-friendly electronics. High-performance electronic devices must achieve low-voltage operation, long-term operational stability, and biocompatibility. Herein, we propose an electrolyte-gated thin-film transistor made of large-area solution-processed indium-gallium-zinc oxide (IGZO) semiconductors capable of directly interacting with live cells at physiological conditions. The fabricated transistors exhibit good electrical performance operating under sub-0.5 V conditions with high on-/off-current ratios (>107) and transconductance (>1.0 mS) over an extended operational lifetime. Furthermore, we verified the biocompatibility of the IGZO surface to various types of mammalian cells in terms of cell viability, proliferation, morphology, and drug responsiveness. Finally, the prolonged stable operation of electrolyte-gated transistor devices directly integrated with live cells provides the proof-of-concept for solution-processed metal oxide material-based direct cellular interfaces.

High-Performance Indium-Based Oxide Transistors with Multiple Channels Through Nanolaminate Structure Fabricated by Plasma-Enhanced Atomic Layer Deposition

An atomic-layer-deposited oxide nanolaminate (NL) structure with 3 dyads where a single dyad consists of a 2-nm-thick confinement layer (CL) (In0.84Ga0.16O or In0.75Zn0.25O), and a barrier layer (BL) (Ga2O3) was designed to obtain superior electrical performance in thin-film transistors (TFTs). Within the oxide NL structure, multiple-channel formation was demonstrated by a pile-up of free charge carriers near CL/BL heterointerfaces in the form of the so-called quasi-two-dimensional electron gas (q2DEG), which leads to an outstanding carrier mobility (μFE) with band-like transport, steep gate swing (SS), and positive threshold voltage (VTH) behavior. Furthermore, reduced trap densities in oxide NL compared to those of conventional oxide single-layer TFTs ensures excellent stabilities. The optimized device with the In0.75Zn0.25O/Ga2O3 NL TFT showed remarkable electrical performance: μFE of 77.1 ± 0.67 cm2/(V s), VTH of 0.70 ± 0.25 V, SS of 100 ± 10 mV/dec, and ION/OFF of 8.9 × 109 with a low operation voltage range of ≤2 V and excellent stabilities (ΔVTH of +0.27, -0.55, and +0.04 V for PBTS, NBIS, and CCS, respectively). Based on in-depth analyses, the enhanced electrical performance is attributed to the presence of q2DEG formed at carefully engineered CL/BL heterointerfaces. Technological computer-aided design (TCAD) simulation was performed theoretically to confirm the formation of multiple channels in an oxide NL structure where the formation of a q2DEG was verified in the vicinity of CL/BL heterointerfaces. These results clearly demonstrate that introducing a heterojunction or NL structure concept into this atomic layer deposition (ALD)-derived oxide semiconductor system is a very effective strategy to boost the carrier-transporting properties and improve the photobias stability in the resulting TFTs.

Controlling the flow of oxygen to explore the study of zinc tin oxide thin film transistors

本研究討論在射頻濺鍍腔體內，控制氬氣氧氣比(Ar:O2)，沉積氧化鋅錫(ZTO)薄膜，透過厚度、穿透率找到最佳條件。接著使用二氧化鉿(HfO2)作為絕緣層，製成氧化鋅錫(ZTO)電晶體，藉由測量電性進行材料分析，發現利用氮氧比為45:5的ZTO薄膜製作而成的薄膜電晶體，有很好的飽和區，臨界電壓為1.26V。<br>我們發現氧氣含量越高時，薄膜的穿透率會越來越高，在可見光的波長間穿透率有85%。再透過量測霍爾效應看出45:5的條件下有較好的載子濃度6.45x1011。原因是在氧氣濃度高的情況下，許多的氧空缺被填滿，改善了載子濃度過高的問題，進而達到飽和且截止的功能。This study discusses in the RF sputtering chamber, controlling the ratio of argon to oxygen (Ar:O2), depositing zinc tin oxide (ZTO) film, and finding the best conditions through thickness and penetration.Then use hafnium dioxide (HfO2) as an insulating layer to make zinc tin oxide (ZTO) transistors. By measuring the electrical properties for material analysis, it is found that the thin film made of ZTO film with a nitrogen-to-oxygen ratio of 45:5 is used. The crystal has a good saturation zone and the critical voltage is 1.26V.We found that the higher the oxygen content, the higher the penetration rate of the film, and the penetration rate between visible light wavelengths is 85%. Through the measurement of the Hall effect, it can be seen that the carrier concentration is 6.45x1011 under the condition of 45:5. The reason is that in the case of high oxygen concentration, many oxygen vacancies are filled, which improves the problem of excessive carrier concentration, and then achieves the function of saturation and cut-off.

Heterojunction Transistors Printed via Instantaneous Oxidation of Liquid Metals

Semiconducting transparent metal oxides are critical high mobility materials for flexible optoelectronic devices such as displays. We introduce the continuous liquid metal printing (CLMP) technique to enable rapid roll-to-roll compatible deposition of semiconducting two-dimensional (2D) metal oxide heterostructures. We leverage CLMP to deposit 10 cm2-scale nanosheets of InOx and GaOx in seconds at a low process temperature (T < 200 °C) in air, fabricating heterojunction thin film transistors with 100× greater Ion/Ioff, 4× steeper subthreshold slope, and a 50% increase in mobility over pure InOx channels. Detailed nanoscale characterization of the heterointerface by X-ray photoelectron spectroscopy, UV-vis, and Kelvin probe elucidates the origins of enhanced electronic transport in these 2D heterojunctions. This combination of CLMP with the electrostatic control induced by the heterostructure architecture leads to high performance (μlin up to 22.6 cm2/(V s)) while reducing the process time for metal oxide transistors by greater than 100× compared with sol-gels and vacuum deposition methods.

Printable Epsilon-Type Structure Transistor Arrays with Highly Reliable Physical Unclonable Functions.

Printed electronics promises to drive the future data-intensive technologies, with its potential to fabricate novel devices over a large area with low cost on nontraditional substrates. In these emerging technologies, there exists a large digital information flow, which requires secure communication and authentication. Physical unclonable functions (PUFs) offer a promising built-in hardware-security system comparable to biometrical data, which can be constructed by device-specific intrinsic variations in the additive manufacturing process of active devices. However, printed PUFs typically exploit the inherent variation in layer thickness and roughness of active devices. The current in devices with enough significant changes to increase the robustness to external environment noise is still a challenge. Here, printable epsilon-type-structure indium tin oxide transistor arrays are demonstrated to construct high-reliability PUFs by modifying the coffee-ring structure. The epsilon-type structure improves the printing scalability, film quality, and device reliability. Furthermore, the print-induced uncertainty along the channel thickness and length can lead to changes in the carrier concentration. Notably, the randomly distributed printing droplets in a small area significantly increase this uncertainty. As a result, the PUFs exhibit near-ideal uniformity, uniqueness, randomness, and reliability. Additionally, the PUFs are resilient against machine-learning-based attacks with a prediction accuracy of only 55% without postprocessing.

Thermal shape morphing of membrane-type electronics based on plastic-elastomer frameworks for 3D electronics with various Gaussian curvatures

This study demonstrates a means of shape morphing planar membrane-type electronic devices into three-dimensional (3D) structures with various Gaussian curvatures using a plastic-elastomer supportive framework consisting of acrylonitrile–butadienestyrene (ABS) lines with tensile stress inside an Ecoflex film. The plastic part, created by extrusion shear printing (ESP), provides the driving force for shape morphing upon thermal annealing, whereas the elastomer part provides a base to mount membrane-type electronic devices and allows a comparably large degree of deformation. To ensure reliable interfacial adhesion in the plastic-elastomer framework, the ABS lines are treated with an allyl-terminated self-assembled monolayer (SAM) for chemical bonding to the Ecoflex layer. To determine control parameters for reliable shape morphing, the annealing conditions (e.g., temperature and time), the printing conditions (e.g., shear rate and pitch), and relative thicknesses of the ABS/Ecoflex are examined. Based on these findings, various 3D structures, including bent, cone, saddle, and dome shapes, can be generated from planar forms using ABS-Ecoflex frameworks, which are also predicted by a mechanical finite element method (FEM) simulation. Furthermore, a metal electrode and a membrane-type indium gallium zinc oxide (IGZO) transistor array are successfully mounted on ABS-Ecoflex frameworks and transformed into curvilinear structures without electrical failure.

A Low-Leakage Zinc Oxide Transistor by Atomic Layer Deposition

In this work, we report an atomic layer deposited (ALD) zinc oxide (ZnO) transistor with low off-state leakage current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> ) ~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${3} \times {10}^{-{18}}$ </tex-math></inline-formula> A/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> at high temperatures up to 147 °C, measured by devices with interdigitated electrodes with a wide channel width ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{W}_{\text {ch}}{)}$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10000~\mu \text{m}$ </tex-math></inline-formula> , where the low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> is still under the detection limit. The impact of ALD growth temperature and annealing on the electrical performance is systematically studied. It is found that low temperature deposition and post deposition annealing are effective to enhance the performance of the ALD ZnO transistors. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {FE}}$ </tex-math></inline-formula> as high as 32.8 cm2/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> , on/off ratio ~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{12}}$ </tex-math></inline-formula> and subthreshold slope (SS) down to 75.3 mV/dec at room temperature are achieved. These results suggest ALD ZnO is a promising channel material for low off-state leakage current device applications.

Heterogeneous Integration of Atomically-Thin Indium Tungsten Oxide Transistors for Low-Power 3D Monolithic Complementary Inverter.

In this work, the authors demonstrate a novel vertically-stacked thin film transistor (TFT) architecture for heterogeneously complementary inverter applications, composed of p-channel polycrystalline silicon (poly-Si) and n-channel amorphous indium tungsten oxide (a-IWO), with a low footprint than planar structure. The a-IWO TFT with channel thickness of approximately 3-4 atomic layers exhibits high mobility of 24 cm2 V-1 s-1 , near ideally subthreshold swing of 63mV dec-1 , low leakage current below 10-13 A, high on/off current ratio of larger than 109 , extremely small hysteresis of 0mV, low contact resistance of 0.44 kΩ-µm, and high stability after encapsulating a passivation layer. The electrical characteristics of n-channel a-IWO TFT are well-matched with p-channel poly-Si TFT for superior complementary metal-oxide-semiconductor technology applications. The inverter can exhibit a high voltage gain of 152V V-1 at low supply voltage of 1.5V. The noise margin can be up to 80% of supply voltage and perform the symmetrical window. The pico-watt static power consumption inverter is achieved by the wide energy bandgap of a-IWO channel and atomically-thin channel. The vertically-stacked complementary field-effect transistors (CFET) with high energy-efficiency can increase the circuit density in a chip to conform the development of next-generation semiconductor technology.

Bionic Research on Multistage Pain Sensitization Based on Ionic Oxide Transistor Array

Bionic Research on Multistage Pain Sensitization Based on Ionic Oxide Transistor Array

Enhanced sub-band gap photosensitivity by an asymmetric source–drain electrode low operating voltage oxide transistor

The photosensitivity of a phototransistor can be enhanced by using an asymmetric work function source–drain (S–D) electrode.

Highly Linear and Symmetric Analog Neuromorphic Synapse Based on Metal Oxide Semiconductor Transistors with Self‐Assembled Monolayer for High‐Precision Neural Network Computation

AbstractThis work presents an analog neuromorphic synapse device consisting of two oxide semiconductor transistors for high‐precision neural networks. One of the two transistors controls the synaptic weight by charging or discharging the storage node, which leads to a conductance change in the other transistor. The programmed weight maintains for more than 300 s as electrons in the storage node are well preserved due to the extremely low off current of the oxide transistor. Ideal synaptic behaviors are achieved by utilizing superior properties of oxide transistors such as a high on/off ratio, low off current, and large‐area uniformity. To further improve the synaptic performance, self‐assembled monolayer treatment is applied for reducing the transistor conductance. The reduction of on current reduces the power consumption, and the reduced off current improves the retention characteristics. There is no noticeable decrease in simulated neural network accuracy even when the measured device‐to‐device variation is intentionally increased by 200%, indicating the possibility of large‐array operation with the synapse device.

Ultrashort 15-nm flexible radio frequency ITO transistors enduring mechanical and temperature stress.

Flexible radio frequency (RF) transistors play an important role in the fast-growing wearable smart sensors for data communication. However, the scaling capability and high-speed performance of the flexible transistor are far below the counterparts on rigid substrates, impeding the gigahertz high-speed applications. Here, we address the scaling and performance bottlenecks in flexible transistors by demonstrating natively flexible RF indium tin oxide transistors with deeply scaled 15-nm-long channel, capable of operating in the 10-GHz frequency range. The record-high cutoff frequency of 11.8GHz and maximum oscillation frequency of 15GHz can rival those on rigid substrates. Furthermore, the robustness of flexible RF transistors was examined, capable of enduring heavy-duty 10,000 bending cycles at 1-mm radius and extreme thermal stress from cryogenic temperature of 4.3K and high temperature of 380K.

Electrospun Stacked Dual‐Channel Transistors with High Electron Mobility Using a Planar Heterojunction Architecture

AbstractThin‐film transistors based on metal oxide semiconductors have become a mainstream technology for application in driving low‐cost backplanes of active matrix liquid crystal displays. Although significant progress has been made in traditional marketable devices based on physical vapor deposition derived metal oxides, it has still been hindered by low yield and poor compatibility. Fortunately, developing solution‐based 1D nanofiber networks to act as the fundamental building blocks for transistor has proven to be a simpler, higher‐throughput approach. However, oxide transistors based on such princesses suffer from degraded carrier mobility and operational instability, preventing the ability of such devices from replacing present polycrystalline Si technologies. Herein, it is shown that double channel heterojunction transistors with high electron mobility (&gt;40 cm2 V−1 s−1) and operational stability can be achieved from electrospun double channels composed of In2O3 and ZnO layers. Adjusting the stacking order and the stacking density of In2O3 and ZnO layers can effectively optimize the interface electron trap, leading to the formation of 2D electron gas and the reduction of stress‐induced instability. These findings further elucidate the significant advance of electrospinning‐derived double channel heterojunction transistors toward practical applications for future low‐cost and high‐performance electronics.

How to print high-mobility metal oxide transistors—Recent advances in ink design, processing, and device engineering

High-throughput printing-based fabrication has emerged as a key enabler of flexible electronics given its unique capability for low-cost integration of circuits based on printed thin film transistors (TFTs). Research in printing inorganic metal oxides has revealed the potential for fabricating oxide TFTs with an unmatched combination of high electron mobility and optical transparency. Here, we highlight recent developments in ink chemistry, printing physics, and material design for high-mobility metal oxide transistors. We consider ongoing challenges for this field that include lowering process temperatures, achieving high speed and high resolution printing, and balancing device performance with the need for high mechanical flexibility. Finally, we provide a roadmap for overcoming these challenges with emerging synthetic strategies for fabricating 2D oxides and complementary TFT circuits for flexible electronics.

Azide-functionalized ligand enabling organic–inorganic hybrid dielectric for high-performance solution-processed oxide transistors

We propose a highly efficient crosslinking strategy for organic–inorganic hybrid dielectric layers using azide-functionalized acetylacetonate, which covalently connect inorganic particles to polymers, enabling highly efficient inter- and intra-crosslinking of organic and inorganic inclusions, resulting in a dense and defect-free thin-film morphology. From the optimized processing conditions, we obtained an excellent dielectric strength of over 4.0 MV cm−1, a high dielectric constant of ~14, and a low surface energy of 38 mN m−1. We demonstrated the fabrication of exceptionally high-performance, hysteresis-free n-type solution-processed oxide transistors comprising an In2O3/ZnO double layer as an active channel with an electron mobility of over 50 cm2 V−1 s−1, on/off ratio of ~107, subthreshold swing of 108 mV dec−1, and high bias-stress stability. From temperature-dependent I–V analyses combined with charge transport mechanism analyses, we demonstrated that the proposed hybrid dielectric layer provides percolation-limited charge transport for the In2O3/ZnO double layer under field-effect conditions.

Printable Coffee‐Ring Structures for Highly Uniform All‐Oxide Optoelectronic Synaptic Transistors

AbstractPrintable oxide transistors have emerged as important optoelectronic synaptic devices to emulate the human visual cognitive system by integrating both photo‐sensing and visual perception functions. However, the inferior electrical performance and low pixel density of printed oxide synaptic transistors impede their implementation of complex neuromorphic computing. Herein, a printable all‐oxide optoelectronic synaptic transistor array based on a modified coffee‐ring structure of indium tin oxide (ITO) is reported. The extraordinary structural design endows the printed ITO transistors with high device uniformity, outstanding electrical performance, and superior process efficiency. Furthermore, a 10 × 12 coffee‐ring structure optoelectronic synaptic transistor array with a high spatial resolution (142 dpi) exhibits durable visual detection and memory behaviors. Meanwhile, an artificial neural network based on the coffee‐ring structure synaptic transistors exhibits high accuracy in the recognition rate. These results promise the efficiency of the exceptional printing strategy in developing advanced optoelectronic synaptic transistors for artificial visual systems.