Oxide Stack Research Articles

Analytical modeling and doping optimization for enhanced analog performance in a Ge/Si interfaced nanowire MOSFET

This paper critically investigates the effect of doping on different device characteristics of a Ge/Si interfaced nanowire MOSFET (GSI-NWM) for analog performance enhancement. The doping of source, channel, and drain has a prominent effect on important device characteristics, which has been investigated through DC and AC analysis performed on the SILVACO TCAD simulator. A numerical computational-based simulation study has been used to investigate the modulation of various device characteristics, such as threshold voltage, cut-off frequency, subthreshold swing, MTPG, current ratio, channel resistance, and transconductance. The investigation revealed a strong dependence of most of these characteristics on the source, channel, and drain doping levels, providing valuable insights into device performance. Proper optimization in doping can significantly improve the performance of the device. A compact physics-based analytical model has been mathematically evaluated and proposed in this work, showing an excellent in-line agreement with the simulated results. This is a novel approach for improving the analog performance parameters of a nanowire MOSFET through doping optimization, which incorporates gate oxide stacking and germanium as a source material. In this work, the biosensing capability of the GSI-NWM has also been discussed and evaluated.

Investigations on 4H-SiC Low Voltage nMOSFETs with Thin Thermal SiO<sub>2</sub>/ Deposited Oxide Gate Dielectric

The poor quality of SiC/SiO2 interface significantly limits the channel mobility, especially in 4H-SiC MOSFETs. Several strategies have been addressed to overcome this issue. Nitridation by NO has been adopted widely by manufactures because nitrogen may replace carbon in some chemical bond at the SiC/SiO2 interface. However, excessive nitridation is not desirable because of pronounced hole-trapping effects near the conduction band. As an alternative gate dielectric, thin SiO2/deposited oxide stack has been investigated in 4H-SiC lateral nMOSFETs. Overall performances were reviewed in aspects of transfer/gm/reverse characteristics, charge pumping method and TLP characteristics.

Simultaneously-doping of HfO2 thin films by Ni with sputtering technique and effect of post annealing on structural and electrical properties

This article reports a detailed structural and electrical characterization study of Ni:HfO2 dielectrics grown by rf and dc sputtering and variations in the rapid thermal annealing temperature. Annealing produced obvious changes in the morphological structure of films and XRD confirmed that the crystallite size increased from 1.3 nm to 14.4 nm with the annealing temperature. XPS showed that the amount of non-lattice oxygen decreased owing to the effects of annealing and resistivity. Dc resistivity measurements showed that the lowest sheet resistance of 1.182 × 106 Ω/□ was achieved by as-deposited films and increased to 70.960 Ω/□ with annealing. Structural differences in films due to the effect of annealing caused equivalent circuit models to vary and different resistance values in electrochemical impedance spectrometry. This study illustrates that HfO2 thin films, boosted by doping and rapid thermal annealing, provide a route toward advanced gate oxide stack structures in electronic devices beyond conventional high-dielectric-constant materials.

Self-Selective Dielectric-Fuse Effect with Ambient Factors in Oxide-Based Memory

A dual-function memory with CMOS compatibility has been presented with the feasibility of future embedded applications. The self-selective memory composed of bilayer oxide stacks is presented with the immunity of sneak-path current (SPC) and improved thermal stability for the high storage class memory array application. Meanwhile, the one-time programmable (OTP) memory is realized by the identical bilayer structure which has improved the yield of dielectric-fuse phenomena by increasing the operating temperature up to 423 K. The physical mechanisms and modeling are investigated with experimental and simulated results. Our results provide pathfinding of high density, CMOS back-end-of-line (BEOL) integration capability, land ow power multi-functionality in the future embedded applications.

Progress in Research and Development of Solid Oxide Cells, Stacks and Systems at Forschungszentrum Jülich

Forschungszentrum Jülich has been involved in the research and development of SOCs for more than 30 years. In this work, selected highlights on material, cell, stack and system development are presented, whereas improving performance and understanding degradation phenomena were in the focus. On cell level, operation in steam, co-electrolysis as well as pure CO2 electrolysis mode was researched. A hierarchical degradation model framework was developed that relates changes at the level of electrode particles to changes in electrode structure, resulting materials properties and overall lifetime-performance. On stack level, progress in clarification and optimization of performance and lifetime relevant processes was made. The role of contaminants, foremost silicon species and sulfur dioxide in feed gases, was investigated to support technical applications. On system level, an rSOC system with an output power of 10 kW in fuel cell mode and an input power of 40 kW in electrolysis mode was developed.

Recent Highlights on Solid Oxide Cells, Stacks and Modules Developments at CEA

Solid Oxide Cell (SOC) technology is considered as an efficient electrolysis technology to produce hydrogen at large scale. It can also operate in fuel cell mode using different fuels (carbon-based or non-carbon based like ammonia), and in reversible mode. Though proofs-of concept have been achieved at different relevant scales for those operating modes, some R&D works still need to be performed to improve performance, durability and cost. Improved and upscaled cells and stacks need to be developed, with a methodology combining multiscale and multiphysics modelling, electrochemical characterization in relevant conditions and advanced post-test analysis. Their integration into modules made of several stacks is also a stepping stone in order to reach multi-MW electrolysers. CEA is working on the whole value chain of SOC technology, from cell development and optimisation to module design and operation through stack upscaling. Recent achievements on those aspects will be presented.

Solid Oxide Stack Development at Elcogen

Elcogen solid oxide stacks are key enablers of the transition to a new energy scenario. This work provides an overview of the latest development activities at Elcogen. Throughout this manuscript, advancements on the stack level will be discussed with main focus on the flexibility and robustness of the elcoStack® in different operating modes. Such advancements are contextualized within the scaling up activities of the company, which will prepare Elcogen for the large scale deployment of solid oxide technology.

Ferroelectric Nanopillar Field-Effect Transistors: Quantum Transport Simulations Based on a Three-Dimensional Phase Field

A ferroelectric field-effect transistor (FEFET) with a cylindrical ferroelectric (FE) nanopillar embedded in the gate oxide stack is proposed and investigated. The device utilizes the multiple polar topological states, which can be stabilized in a nanoscale regime. To correctly simulate the proposed FEFET, a full three-dimensional phase-field-based quantum transport model is developed where nonequilibrium Green's function, Poisson, and time-dependent Ginzburg-Landau equations are self-consistently solved. Using the in-house tool, we theoretically demonstrate that the nanopillar FEFET exhibits multibit operation of six-level states with a reasonable memory window (MW) and sufficiently large difference in the current between the states. We also investigate the short-channel effect on the proposed FEFET and assess its scalability. MW linearly increases as the gate length decreases, because the polarization bound charges of the FE nanopillar induce the quasi-bound-states on the channel region and thus degrade the gate controllability.

Quantum Effect Dependent Modelling of Short Channel Junctionless Double Gate Stack(SC-JL-DG) MOSFET for High Frequency Analog Applications

In this paper, the quantum effect has been induced on Junctionless (JL)-Double Gate metal-oxide-semiconductor field-effect transistors (JL-DGMOSFET) with gate oxide stack to study its effect on different device parameters like surface potential, threshold voltage, Id, Vg, gm, channel length etc. The study has been extended on Ion/Ioff change w.r.t. the variation in spacer width for varied channel thickness. In order to extend the efficacy of the results an analytical model has been formulated. The analytical model is developed by incorporating the Schrodinger equation in the conventional 2-D Poisson's equation, which has further been solved by applying the boundary conditions to obtain the final expression for potential and change in threshold voltage (Vth). The device parameters are in accordance for both the simulated and analytical results. The simulation work has been supported by the ATLAS device simulation.

Improvement of memory performance of 3-D NAND flash memory with retrograde channel doping

The examination of the effect of retrograde channel doping on reliability and performance of 3-D junction-free NAND based flash memory is done for this paper. Specifically, we study the program characteristics, data retention capability junction-free NAND flash memory with half pitch range from 35 nm to 12 nm. Based on our analysis, we highlight that the retrograde channel doping approach can improve not only the SCEs but also the program speed and data control time for 3-D junction-free NAND flash memory, without varying the oxide stack in charge trap-based flash memory.

Performance Analysis of Gate Engineered High-K Gate Oxide Stack SOI Fin-FET for 5 nm Technology

Abstract: This paper analyses the performance of 5 nm gate length gate engineered oxide stack silicon on insulator (SOI) fin field-effect transistor (OS-Fin-FET) for the first time. The high dielectric (High-K) value of the material-based gate oxide stack structure increases both the analog and the radio frequency (RF) performance of the Fin-FET device when compared to standard single gate oxide material structures. The work function of the engineered gate structure further helps in advancing the performance of the device in terms of on current (Ion), off current (Ioff) and the ratio of Ion/Ioff. The proposed OS-FinFET device improves on current (Ion) of the device by 12% in comparison to the high-K dielectric gate oxidebased FinFET device. Simulation of the device is further extended to study different electrical characteristics of the proposed device under other biasing conditions, to estimate enhanced analog and RF performance where the device is highly suitable for low power and high-speed applications. Overall, the proposed device shows improvement in existing architectures of the devices. Technology computer-aided design (TCAD) tool is used to perform entire simulations of the proposed device with 5 nm gate length. Aim: To enhance analog and RF performance of the Fin-FET device at 5 nm gate length. Background: Design of the sub-10 nm Fin-FET device undergoes charge shearing phenomena because of the minimum distance between source and drain. This problem is addressed by using High-K spacer over substrate but it leads to increase in the channel resistance and adverse short channel effects. A combination of different high-K dielectric materials can eliminate this performance. Hence most of the studies concentrated on spacer region and failed to consider channel region. This study tries to improve analog performance of the device using the approach of gate engineering with gate stack approach. Objective: The main objective of this study is to increase on current (Ion) of the device by implementing gate engineering approach, by choosing dual work function-based gate with oxide stack approach. The High-K dielectric material-based gate oxide reduces leakage current, decreases off current which will increase the ratio of Ion/Ioff. Methods: The dual work function gate material is taken with gate oxide stack approach by considering different High-K dielectric materials like HfO2, TiO2 with thin SiO2 layer as the interactive layer. Simulation of the device is carried out using TCAD Tool and results are compared with existing literature, to validate the results. Results: The proposed architecture of the Fin-FET device delivers excellent results in terms of on current and subthreshold characteristics compared to existing literature. The proposed device gives high on current of 0.027 A and current ratio of 1.08X104. Conclusion: A complete comparative analysis is carried out with existing literature on the proposed device, where the proposed device resulted in high performance. The proposed device improves 12% compared to existing literature, which is highly suitable for low power applications.

Metal oxide encapsulated by 3D graphene oxide creates a nanocomposite with enhanced organic adsorption in aqueous solution.

The presence of organic contaminants (OCs) in aquatic systems is a threat to ecological and human health. Adsorption by graphene-based adsorbent is a promising technique for OC removal and we previously fabricated crumpled graphene balls (CGBs), via a novel nano-spray drying technique, which show robust adsorptive performance. Yet, since CGBs contain non-accessible surface area due to 2D graphene stacking, the goal of this research was to investigate the efficacy of maximizing the accessible CGB surface by synthesizing a nanocomposite composed of metal oxide nanoparticles encapsulated by crumpled graphene oxide (MGC). The metal oxides reduce graphene oxide stacking, expand the internal adsorptive surface area, and boost the adsorptive capacity of the MGC. MGC (fumed SiO2 or SiO2) exhibit an enhanced Langmuir adsorption capacity (qm, normalized by the % carbon) for an OC model, methylene blue (MB), achieving improvements of 60-86% compared to CGB, 3-4 fold compared to powder activated carbon (PAC) and 6-7 fold compared to granular activated carbon (GAC). MGCs display rapid adsorption reaching equilibrium after 9-12min of contact and remaining stable in wastewater effluent /surface water. A cost-efficiency comparison reveals MGCs achieve one ton of MB removal at similar or lower material costs than that of PAC/GAC.

Mathematical Modeling and Thermal Control of a 1.5 kW Reversible Solid Oxide Stack for 24/7 Hydrogen Plants

Solid oxide technology has gained importance due to its higher efficiencies compared to other current hydrogen technologies. The reversible mode allows working with both technologies (SOEC-SOFC), which makes it very attractive for mixed operations, both storage and generation, increasing its usage and therefore the viability of the technology implementation. To improve the performance of reversible stacks, developing adequate control strategies is of great importance. In order to design these strategies, suitable models are needed. These control-oriented models should be simple for an efficient controller design, but also they should include all phenomena that can be affected by the control law. This article introduces a control-oriented modeling of a reversible solid oxide stack (rSOS) for the implementation of control strategies considering thermal and degradation effects. The model is validated with experimental data of a 1.5 kW laboratory prototype, analyzing both polarization curves and dynamic responses to different current profiles and compositions. An error of less than 3% between the model and experimental responses has been obtained, demonstrating the validity of the proposed control-oriented model. The proposed model allows performing new and deeper analysis of the role of reversible solid oxide cells in 24/7 generation plants with renewable energy sources.

Area selective deposition of ruthenium on 3D structures

Trends in device miniaturization have driven the adoption of new materials that, in turn, have enabled significant advancements in the field of process engineering and integration for semiconductor technology. Continued progress for device scaling is necessary and can be enabled by advances in lithographic techniques and deposition schemes. Thin-film deposition for spacers and etch stop layers has become a mainstay to enable and extend traditional 2D scaling into the 3D realm for fabricating advanced semiconductor devices. For processing 3D structures, controlled film deposition with subnanometer resolution in high aspect ratio features is desired. Area selective deposition (ASD) can be a powerful response to such a challenge. ASD is a type of thin-film deposition technique scheme that can be used to eliminate the need for several expensive and time-consuming lithography steps with fewer performance penalties. In this work, we show ASD of ruthenium (Ru) on 3D molybdenum (Mo)–silicon oxide (SiO2) stacks by utilizing the inherent substrate preference of the Ru precursor to a H-terminated surface. In the best selectivity condition, our results show growth of ∼5 nm Ru on Mo, with no film growth on SiO2. Changes in Ru growth kinetics were observed after dilute hydrofluoric acid (DHF) treatment for both surfaces. Post-DHF treatment, the Ru growth rate on Mo was reduced by 5%. However, on SiO2 (after incubation delay), the growth rate was reduced by 94% compared to untreated surfaces. This translates to a very high difference in the growth rate of Ru on Mo vs SiO2, even after considering the incubation delay. Finally, by using 3D topologies with high aspect ratio holes, we have highlighted that it is important to deconvolute the effects of precursor depletion and selectivity. To the best of our knowledge, this is the first demonstration of ASD of Ru on 3D structures without the use of any blocking layers. Therefore, these results demonstrate a new paradigm for ASD in 3D features.

Flexible Liquid‐Based Continuous Direct‐Current Tribovoltaic Generators Enable Self‐Powered Multi‐Modal Sensing

AbstractFlexible tribovoltaic direct‐current (DC) generators are urgently expected by wearable applications. Traditional rigid contact‐separation type tribovoltaic DC generators normally have non‐ignorable friction loss and cannot sustain outstanding outputs. This hinders their serviceability in continuous motion scenarios. Here, flexible liquid‐based DC generators (FLGs) with metal‐liquid‐semiconductor indium gallium zinc oxide (IGZO) stack structures are reported. The FLG with Pt/H2O/IGZO structure delivers a peak short‐circuit current density up to 2.3 µA cm−2, a peak open‐circuit voltage up to 620 mV, and a power density up to 0.1 µW cm−2. The differences in the properties of different liquid–solid interfaces are studied by density functional theory, showing that the bond formation, charge‐transfer‐induced dipole electric field at the solid‐liquid interface, and the built‐in electric field are responsible for the generation and separation of electron‐hole pairs to form continuous DC. The proposed FLG can keep excellent performance even after >5 × 104 shaking cycles or exposing to ambient conditions for 30 days, showing extraordinary stability. Besides charging capacitors or driving LEDs, the FLG is further demonstrated to work for self‐powered multifunctional sensing, enabling pressure, position‐posture, or temperature detections. This design offers potential solutions and novel possibilities for next‐generation self‐powered wearable electronics.

Performance Study of DM-DG-OS JL-MOSFET based Biosensor in Detecting Charged Nanometric Biospecies

In this paper, for the first time, a dual-metal double-gate with oxide stack (low-k/high-k) junctionless MOSFET (DM-DG-OS JL-MOSFET) based sensor device has been explored for finding its suitability in detecting charged nanometric biospecies under dry environment condition. The analysis of sensing performance of the device for such detection is made in terms of the absolute and the relative changes in threshold voltage (Vth). The influence of work-function difference of dual metal gate electrodes, along with the position of nanogap cavity, on the sensing metrics has been thoroughly investigated. The impact of the cavity dimensions on sensitivity parameters of the projected device is also studied. An optimum cavity dimension, for channel length (Lch) of 1 µm, is found to be 400 nm × 10 nm in yielding measurable sensitivity parameters for charged nanometric biospecies detection. A device with 1-µm Lch exhibits superior sensitivity performance in terms of percentage improvements in the absolute and the relative changes in Vth for a higher drain-side gate-metal work-function (ϕM2) relative to source-side gate-metal work-function (ϕM1) for source-side cavity (400 nm × 10 nm) compared to the case when ϕM1>ϕM2 and the cavity is located near drain-side. Respective performance enhancements are found to be 30.7% and 74% for detection of negatively charged nanometric biospecies. The sensor devices with Lch of 50 nm show the similar trend.

Temperature Stable Piezoelectric Imprint of Epitaxial Grown PZT for Zero-Bias Driving MEMS Actuator Operation.

In piezoelectric transducer applications, it is common to use a unipolar operation signal to avoid switching of the polarisation and the resulting nonlinearities of micro-electromechanical systems. However, semi-bipolar or bipolar operation signals have the advantages of less leakage current, lower power consumption and no additional need of a DC−DC converter for low AC driving voltages. This study investigates the potential of using piezoelectric layers with an imprint for stable bipolar operation on the basis of epitaxially grown lead zirconate titanate cantilevers with electrodes made of a metal and metal oxide stack. Due to the manufacturing process, the samples exhibit high crystallinity, rectangular shaped hysteresis and a high piezoelectric response. Furthermore, the piezoelectric layers have an imprint, indicating a strong built-in field, which shifts the polarisation versus electric field hysteresis. To obtain the stability of the imprint, laser doppler vibrometry and switching current measurements were performed at different temperatures, yielding a stable imprinted electric field of −1.83 MV/m up to at least 100 °C. The deflection of the cantilevers was measured with a constant AC driving voltage while varying the DC bias voltage to examine the influence of the imprint under operation, revealing that the same high deflection and low nonlinearities, quantified by the total harmonic distortion, can be maintained down to low bias voltages compared to unipolar operation. These findings demonstrate that a piezoelectric layer with a strong imprint makes it possible to operate with low DC or even zero DC bias, while still providing strong piezoelectric response and linear behaviour.

Stacking and Twisting of Freestanding Complex Oxide Thin Films.

The integration of dissimilar materials in heterostructures has long been acornerstone of modern materials science-seminal examples are 2D materials and van der Waals heterostructures. Recently, new methods have been developed that enable the realization of ultrathin freestanding oxide films approaching the 2D limit. Oxides offer new degrees of freedom, due to the strong electronic interactions, especially the 3d orbital electrons, which give rise to rich exotic phases. Inspired by this progress, a new platform for assembling freestanding oxide thin films with different materials and orientations into artificial stacks with heterointerfaces is developed. It is shown that the oxide stacks can be tailored by controlling the stacking sequences, as well as the twist angle between the constituent layers with atomically sharp interfaces, leading to distinct moiré patterns in the transmission electron microscopy images of the full stacks. Stacking and twisting is recognized as a key degree of structural freedom in 2D materials but, until now, has never been realized for oxide materials. This approach opens unexplored avenues for fabricating artificial 3D oxide stacking heterostructures with freestanding membranes across a broad range of complex oxide crystal structures with functionalities not available in conventional 2D materials.

The Effect of Deposition Conditions on Heterointerface‐Driven Band Alignment and Resistive Switching Properties

AbstractTitanium nitride and hafnium oxide stack have been widely used in various resistive memory elements since the materials are complementary‐metal‐oxide‐semiconductor compatible. The understanding of the interface properties between the electrode and the oxide is important in designing the memory behavior. To bridge this understanding, HfOx grown using plasma enhanced atomic layer deposition (PEALD) and thermal atomic layer deposition (TALD) are compared, in terms of band alignment and electrical performances in the HfOx/PEALD TiN stacks. X‐ray photoelectron spectroscopy reveals a thicker interfacial TiO2 layer in the PEALD HfOx/TiN stack whose interface resembles more to the PEALD HfOx/TiO2 interface (conduction band offset ΔEC = 1.63 eV), whereas the TALD HfOx stack interface resembles more to the TALD HfOx/TiN interface (ΔEC = 2.22 eV). The increase in the forming voltage and the early onset of reverse filament formation (RFF) in the I–V measurements for the PEALD HfOx stack confirms the presence of the thicker interfacial layer; the early onset of RFF is likely related to a smaller ΔEC. The findings show the importance of understanding the intricate details of the material stack, where ΔEC difference and the presence of a thicker TiO2 interfacial layer due to different deposition procedures affect the device performance.

(Digital Presentation) Optimization of MIM Rectifiers for Terahertz Rectennas

There is a significant demand for harvesting renewable infrared (IR) energy from unused heat sources. The rectifying antenna (rectenna) device has the ability to capture alternating current (AC) IR radiation and rectify it into usable direct current (DC) electricity. Metal-Insulator-Metal (MIM) diodes have shown to be the most prominent contenders for rectenna applications. This is due to their ultra-fast current transport mechanism in the femtosecond range by means of quantum mechanical tunnelling. Optical rectification at 28.3 THz has recently been demonstrated by rectenna devices based on MInM diodes using Au/Al2O3/Ti [1] and Ti/TiO2/ZnO/Al [2] configurations. Although the results are promising, the overall conversion efficiency is quite low, 2.05 × 10-14 [1], mainly due to the poor rectification properties of the diodes. Other recent research [3-5] has focused on the combination of stoichiometric and non-stoichiometric oxides with the aim of engineering the barrier heights to achieve low dynamic resistance (R0 ), high responsivity (β0 ) and asymmetry (η0 ) at zero-bias where the results are very promising for self-biased rectennas. The most recent experimental breakthrough was achieved by Ni/NiO/AlOx/CrAu bowtie rectennas that feature a device area of 0.035 µm2, low R0 of 13 kΩ and high β0 of 0.5 A/W. The results show that 5.1% coupling efficiency and 1.7 × 10−8% power conversion efficiency can be achieved with correct optimization of oxide stack. Furthermore, the most recent theoretical study [6] shows that the β0 of the MI2M diodes can be further improved to ~ 5 A/W by keeping the impedance match between the diode and the antenna at around 100 Ω. The proposed Ti/1 nm TiO2/1 nm Nb2O5/Ti rectenna design can achieve diode cut-off frequency (fc ) of 17 THz and resistance × capacitance (RC) time constant of 9 fs assuming the diode area of 0.01 µm2. Liverpool group has demonstrated recently [7,8] the effect of resonant tunnelling in non-cascaded (Al/Ta2O5/Nb2O5/Al2O3/Al) and cascaded (Al/Nb2O5/Al2O3/Ta2O5/Al) triple insulator diode structures with an oxide thickness ratio of 1:3:1 (in nm) deposited by atomic layer deposition (ALD). The diodes exhibit superior β = 5 A/W at 0.2 V and η = 12 at 0.1 V, with a drawback of high R0 due to high barrier heights between the metal/oxide layers.In this paper, we further optimize the MInM diode configurations so that the metal/oxide barrier is significantly lowered to ~ 0.1 eV. This is achieved by using the combinations of rectenna contender oxides such as Al2O3, NiO and ZnO that have high electron affinity and low dynamic permittivity [9]. Ultra-thin (≤ 5 nm) insulating layers were fabricated using radio frequency (RF) magnetron sputtering and ALD. Metal electrodes were deposited by thermal evaporation and RF sputtering using shadow mask, photolithography and nanolithography processes. The device areas range from 100 µm × 100 µm, 1 µm × 1 µm and 100 nm × 100 nm depending on the patterning process to observe the effect of device scaling on the conduction mechanisms and direct current (DC) rectification properties. The deposited oxide layers were measured by variable angle spectroscopic ellipsometry (VASE) to ascertain their thickness, uniformity and optical constants. DC current voltage measurements were performed on fabricated diodes to evaluate key rectification parameters such as R0 , β0 , η and non-linearity (fNL ) around zero-bias. Complementary theoretical calculations were performed to substantiate the experimental results and allow comparison of different MInM diode configurations such as NiO/Al2O3, ZnO/Al2O3, NiO/ZnO and NiO/ZnO/Al2O3. This work shows that the coupling efficiency at IR cut-off frequencies can be improved by optimizing the barriers in MInM rectifiers. References. [1] Jayaswal et al.,Materials Today Energy, 7, 1-9 (2018); [2] Elsharabasy et al., IEEE J. Photovoltaics, 9, 1232, (2019); [3] Matsuura et al., Sci. Rep. 9, 1-7 (2019); [4] Weerakkody et al., ACS Appl. Nano Mater. 4, 2470–2475 (2021); [5] Belkadi et al., Nat. Commun., 12, 1–6 (2021); [6] Elsharabasy et al., Results Mater. 11, 100204 (2021); [7] Mitrovic et al., ECS Trans. 72, 287 (2016); [8] Tekin et al., Solid State Electron. 185, 108096 (2021); [9] Mitrovic et al., Materials, 14, 5218 (2021).